sata_sil.c revision a0cf733b333eeeafb7324e2897448006c693c26c
1/* 2 * sata_sil.c - Silicon Image SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2005 Red Hat, Inc. 9 * Copyright 2003 Benjamin Herrenschmidt 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Documentation for SiI 3112: 31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 32 * 33 * Other errata and documentation available under NDA. 34 * 35 */ 36 37#include <linux/kernel.h> 38#include <linux/module.h> 39#include <linux/pci.h> 40#include <linux/init.h> 41#include <linux/blkdev.h> 42#include <linux/delay.h> 43#include <linux/interrupt.h> 44#include <linux/device.h> 45#include <scsi/scsi_host.h> 46#include <linux/libata.h> 47 48#define DRV_NAME "sata_sil" 49#define DRV_VERSION "2.0" 50 51enum { 52 /* 53 * host flags 54 */ 55 SIL_FLAG_NO_SATA_IRQ = (1 << 28), 56 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), 57 SIL_FLAG_MOD15WRITE = (1 << 30), 58 59 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 60 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, 61 62 /* 63 * Controller IDs 64 */ 65 sil_3112 = 0, 66 sil_3112_no_sata_irq = 1, 67 sil_3512 = 2, 68 sil_3114 = 3, 69 70 /* 71 * Register offsets 72 */ 73 SIL_SYSCFG = 0x48, 74 75 /* 76 * Register bits 77 */ 78 /* SYSCFG */ 79 SIL_MASK_IDE0_INT = (1 << 22), 80 SIL_MASK_IDE1_INT = (1 << 23), 81 SIL_MASK_IDE2_INT = (1 << 24), 82 SIL_MASK_IDE3_INT = (1 << 25), 83 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, 84 SIL_MASK_4PORT = SIL_MASK_2PORT | 85 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, 86 87 /* BMDMA/BMDMA2 */ 88 SIL_INTR_STEERING = (1 << 1), 89 90 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ 91 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ 92 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ 93 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ 94 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ 95 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ 96 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ 97 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ 98 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ 99 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ 100 101 /* SIEN */ 102 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ 103 104 /* 105 * Others 106 */ 107 SIL_QUIRK_MOD15WRITE = (1 << 0), 108 SIL_QUIRK_UDMA5MAX = (1 << 1), 109}; 110 111static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 112#ifdef CONFIG_PM 113static int sil_pci_device_resume(struct pci_dev *pdev); 114#endif 115static void sil_dev_config(struct ata_port *ap, struct ata_device *dev); 116static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); 117static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 118static void sil_post_set_mode (struct ata_port *ap); 119static irqreturn_t sil_interrupt(int irq, void *dev_instance); 120static void sil_freeze(struct ata_port *ap); 121static void sil_thaw(struct ata_port *ap); 122 123 124static const struct pci_device_id sil_pci_tbl[] = { 125 { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, 126 { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, 127 { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, 128 { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, 129 { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, 130 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, 131 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, 132 133 { } /* terminate list */ 134}; 135 136 137/* TODO firmware versions should be added - eric */ 138static const struct sil_drivelist { 139 const char * product; 140 unsigned int quirk; 141} sil_blacklist [] = { 142 { "ST320012AS", SIL_QUIRK_MOD15WRITE }, 143 { "ST330013AS", SIL_QUIRK_MOD15WRITE }, 144 { "ST340017AS", SIL_QUIRK_MOD15WRITE }, 145 { "ST360015AS", SIL_QUIRK_MOD15WRITE }, 146 { "ST380023AS", SIL_QUIRK_MOD15WRITE }, 147 { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, 148 { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, 149 { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, 150 { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, 151 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, 152 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, 153 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, 154 { } 155}; 156 157static struct pci_driver sil_pci_driver = { 158 .name = DRV_NAME, 159 .id_table = sil_pci_tbl, 160 .probe = sil_init_one, 161 .remove = ata_pci_remove_one, 162#ifdef CONFIG_PM 163 .suspend = ata_pci_device_suspend, 164 .resume = sil_pci_device_resume, 165#endif 166}; 167 168static struct scsi_host_template sil_sht = { 169 .module = THIS_MODULE, 170 .name = DRV_NAME, 171 .ioctl = ata_scsi_ioctl, 172 .queuecommand = ata_scsi_queuecmd, 173 .can_queue = ATA_DEF_QUEUE, 174 .this_id = ATA_SHT_THIS_ID, 175 .sg_tablesize = LIBATA_MAX_PRD, 176 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 177 .emulated = ATA_SHT_EMULATED, 178 .use_clustering = ATA_SHT_USE_CLUSTERING, 179 .proc_name = DRV_NAME, 180 .dma_boundary = ATA_DMA_BOUNDARY, 181 .slave_configure = ata_scsi_slave_config, 182 .slave_destroy = ata_scsi_slave_destroy, 183 .bios_param = ata_std_bios_param, 184 .suspend = ata_scsi_device_suspend, 185 .resume = ata_scsi_device_resume, 186}; 187 188static const struct ata_port_operations sil_ops = { 189 .port_disable = ata_port_disable, 190 .dev_config = sil_dev_config, 191 .tf_load = ata_tf_load, 192 .tf_read = ata_tf_read, 193 .check_status = ata_check_status, 194 .exec_command = ata_exec_command, 195 .dev_select = ata_std_dev_select, 196 .post_set_mode = sil_post_set_mode, 197 .bmdma_setup = ata_bmdma_setup, 198 .bmdma_start = ata_bmdma_start, 199 .bmdma_stop = ata_bmdma_stop, 200 .bmdma_status = ata_bmdma_status, 201 .qc_prep = ata_qc_prep, 202 .qc_issue = ata_qc_issue_prot, 203 .data_xfer = ata_mmio_data_xfer, 204 .freeze = sil_freeze, 205 .thaw = sil_thaw, 206 .error_handler = ata_bmdma_error_handler, 207 .post_internal_cmd = ata_bmdma_post_internal_cmd, 208 .irq_handler = sil_interrupt, 209 .irq_clear = ata_bmdma_irq_clear, 210 .scr_read = sil_scr_read, 211 .scr_write = sil_scr_write, 212 .port_start = ata_port_start, 213 .port_stop = ata_port_stop, 214 .host_stop = ata_pci_host_stop, 215}; 216 217static const struct ata_port_info sil_port_info[] = { 218 /* sil_3112 */ 219 { 220 .sht = &sil_sht, 221 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, 222 .pio_mask = 0x1f, /* pio0-4 */ 223 .mwdma_mask = 0x07, /* mwdma0-2 */ 224 .udma_mask = 0x3f, /* udma0-5 */ 225 .port_ops = &sil_ops, 226 }, 227 /* sil_3112_no_sata_irq */ 228 { 229 .sht = &sil_sht, 230 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | 231 SIL_FLAG_NO_SATA_IRQ, 232 .pio_mask = 0x1f, /* pio0-4 */ 233 .mwdma_mask = 0x07, /* mwdma0-2 */ 234 .udma_mask = 0x3f, /* udma0-5 */ 235 .port_ops = &sil_ops, 236 }, 237 /* sil_3512 */ 238 { 239 .sht = &sil_sht, 240 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 241 .pio_mask = 0x1f, /* pio0-4 */ 242 .mwdma_mask = 0x07, /* mwdma0-2 */ 243 .udma_mask = 0x3f, /* udma0-5 */ 244 .port_ops = &sil_ops, 245 }, 246 /* sil_3114 */ 247 { 248 .sht = &sil_sht, 249 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 250 .pio_mask = 0x1f, /* pio0-4 */ 251 .mwdma_mask = 0x07, /* mwdma0-2 */ 252 .udma_mask = 0x3f, /* udma0-5 */ 253 .port_ops = &sil_ops, 254 }, 255}; 256 257/* per-port register offsets */ 258/* TODO: we can probably calculate rather than use a table */ 259static const struct { 260 unsigned long tf; /* ATA taskfile register block */ 261 unsigned long ctl; /* ATA control/altstatus register block */ 262 unsigned long bmdma; /* DMA register block */ 263 unsigned long bmdma2; /* DMA register block #2 */ 264 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ 265 unsigned long scr; /* SATA control register block */ 266 unsigned long sien; /* SATA Interrupt Enable register */ 267 unsigned long xfer_mode;/* data transfer mode register */ 268 unsigned long sfis_cfg; /* SATA FIS reception config register */ 269} sil_port[] = { 270 /* port 0 ... */ 271 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, 272 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, 273 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, 274 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, 275 /* ... port 3 */ 276}; 277 278MODULE_AUTHOR("Jeff Garzik"); 279MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); 280MODULE_LICENSE("GPL"); 281MODULE_DEVICE_TABLE(pci, sil_pci_tbl); 282MODULE_VERSION(DRV_VERSION); 283 284static int slow_down = 0; 285module_param(slow_down, int, 0444); 286MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); 287 288 289static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) 290{ 291 u8 cache_line = 0; 292 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); 293 return cache_line; 294} 295 296static void sil_post_set_mode (struct ata_port *ap) 297{ 298 struct ata_host *host = ap->host; 299 struct ata_device *dev; 300 void __iomem *addr = host->mmio_base + sil_port[ap->port_no].xfer_mode; 301 u32 tmp, dev_mode[2]; 302 unsigned int i; 303 304 for (i = 0; i < 2; i++) { 305 dev = &ap->device[i]; 306 if (!ata_dev_enabled(dev)) 307 dev_mode[i] = 0; /* PIO0/1/2 */ 308 else if (dev->flags & ATA_DFLAG_PIO) 309 dev_mode[i] = 1; /* PIO3/4 */ 310 else 311 dev_mode[i] = 3; /* UDMA */ 312 /* value 2 indicates MDMA */ 313 } 314 315 tmp = readl(addr); 316 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); 317 tmp |= dev_mode[0]; 318 tmp |= (dev_mode[1] << 4); 319 writel(tmp, addr); 320 readl(addr); /* flush */ 321} 322 323static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) 324{ 325 unsigned long offset = ap->ioaddr.scr_addr; 326 327 switch (sc_reg) { 328 case SCR_STATUS: 329 return offset + 4; 330 case SCR_ERROR: 331 return offset + 8; 332 case SCR_CONTROL: 333 return offset; 334 default: 335 /* do nothing */ 336 break; 337 } 338 339 return 0; 340} 341 342static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) 343{ 344 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); 345 if (mmio) 346 return readl(mmio); 347 return 0xffffffffU; 348} 349 350static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) 351{ 352 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); 353 if (mmio) 354 writel(val, mmio); 355} 356 357static void sil_host_intr(struct ata_port *ap, u32 bmdma2) 358{ 359 struct ata_eh_info *ehi = &ap->eh_info; 360 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); 361 u8 status; 362 363 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { 364 u32 serror; 365 366 /* SIEN doesn't mask SATA IRQs on some 3112s. Those 367 * controllers continue to assert IRQ as long as 368 * SError bits are pending. Clear SError immediately. 369 */ 370 serror = sil_scr_read(ap, SCR_ERROR); 371 sil_scr_write(ap, SCR_ERROR, serror); 372 373 /* Trigger hotplug and accumulate SError only if the 374 * port isn't already frozen. Otherwise, PHY events 375 * during hardreset makes controllers with broken SIEN 376 * repeat probing needlessly. 377 */ 378 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 379 ata_ehi_hotplugged(&ap->eh_info); 380 ap->eh_info.serror |= serror; 381 } 382 383 goto freeze; 384 } 385 386 if (unlikely(!qc || qc->tf.ctl & ATA_NIEN)) 387 goto freeze; 388 389 /* Check whether we are expecting interrupt in this state */ 390 switch (ap->hsm_task_state) { 391 case HSM_ST_FIRST: 392 /* Some pre-ATAPI-4 devices assert INTRQ 393 * at this state when ready to receive CDB. 394 */ 395 396 /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 397 * The flag was turned on only for atapi devices. 398 * No need to check is_atapi_taskfile(&qc->tf) again. 399 */ 400 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 401 goto err_hsm; 402 break; 403 case HSM_ST_LAST: 404 if (qc->tf.protocol == ATA_PROT_DMA || 405 qc->tf.protocol == ATA_PROT_ATAPI_DMA) { 406 /* clear DMA-Start bit */ 407 ap->ops->bmdma_stop(qc); 408 409 if (bmdma2 & SIL_DMA_ERROR) { 410 qc->err_mask |= AC_ERR_HOST_BUS; 411 ap->hsm_task_state = HSM_ST_ERR; 412 } 413 } 414 break; 415 case HSM_ST: 416 break; 417 default: 418 goto err_hsm; 419 } 420 421 /* check main status, clearing INTRQ */ 422 status = ata_chk_status(ap); 423 if (unlikely(status & ATA_BUSY)) 424 goto err_hsm; 425 426 /* ack bmdma irq events */ 427 ata_bmdma_irq_clear(ap); 428 429 /* kick HSM in the ass */ 430 ata_hsm_move(ap, qc, status, 0); 431 432 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 433 qc->tf.protocol == ATA_PROT_ATAPI_DMA)) 434 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); 435 436 return; 437 438 err_hsm: 439 qc->err_mask |= AC_ERR_HSM; 440 freeze: 441 ata_port_freeze(ap); 442} 443 444static irqreturn_t sil_interrupt(int irq, void *dev_instance) 445{ 446 struct ata_host *host = dev_instance; 447 void __iomem *mmio_base = host->mmio_base; 448 int handled = 0; 449 int i; 450 451 spin_lock(&host->lock); 452 453 for (i = 0; i < host->n_ports; i++) { 454 struct ata_port *ap = host->ports[i]; 455 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); 456 457 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) 458 continue; 459 460 /* turn off SATA_IRQ if not supported */ 461 if (ap->flags & SIL_FLAG_NO_SATA_IRQ) 462 bmdma2 &= ~SIL_DMA_SATA_IRQ; 463 464 if (bmdma2 == 0xffffffff || 465 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) 466 continue; 467 468 sil_host_intr(ap, bmdma2); 469 handled = 1; 470 } 471 472 spin_unlock(&host->lock); 473 474 return IRQ_RETVAL(handled); 475} 476 477static void sil_freeze(struct ata_port *ap) 478{ 479 void __iomem *mmio_base = ap->host->mmio_base; 480 u32 tmp; 481 482 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ 483 writel(0, mmio_base + sil_port[ap->port_no].sien); 484 485 /* plug IRQ */ 486 tmp = readl(mmio_base + SIL_SYSCFG); 487 tmp |= SIL_MASK_IDE0_INT << ap->port_no; 488 writel(tmp, mmio_base + SIL_SYSCFG); 489 readl(mmio_base + SIL_SYSCFG); /* flush */ 490} 491 492static void sil_thaw(struct ata_port *ap) 493{ 494 void __iomem *mmio_base = ap->host->mmio_base; 495 u32 tmp; 496 497 /* clear IRQ */ 498 ata_chk_status(ap); 499 ata_bmdma_irq_clear(ap); 500 501 /* turn on SATA IRQ if supported */ 502 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) 503 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); 504 505 /* turn on IRQ */ 506 tmp = readl(mmio_base + SIL_SYSCFG); 507 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); 508 writel(tmp, mmio_base + SIL_SYSCFG); 509} 510 511/** 512 * sil_dev_config - Apply device/host-specific errata fixups 513 * @ap: Port containing device to be examined 514 * @dev: Device to be examined 515 * 516 * After the IDENTIFY [PACKET] DEVICE step is complete, and a 517 * device is known to be present, this function is called. 518 * We apply two errata fixups which are specific to Silicon Image, 519 * a Seagate and a Maxtor fixup. 520 * 521 * For certain Seagate devices, we must limit the maximum sectors 522 * to under 8K. 523 * 524 * For certain Maxtor devices, we must not program the drive 525 * beyond udma5. 526 * 527 * Both fixups are unfairly pessimistic. As soon as I get more 528 * information on these errata, I will create a more exhaustive 529 * list, and apply the fixups to only the specific 530 * devices/hosts/firmwares that need it. 531 * 532 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted 533 * The Maxtor quirk is in the blacklist, but I'm keeping the original 534 * pessimistic fix for the following reasons... 535 * - There seems to be less info on it, only one device gleaned off the 536 * Windows driver, maybe only one is affected. More info would be greatly 537 * appreciated. 538 * - But then again UDMA5 is hardly anything to complain about 539 */ 540static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) 541{ 542 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO; 543 unsigned int n, quirks = 0; 544 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 545 546 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 547 548 for (n = 0; sil_blacklist[n].product; n++) 549 if (!strcmp(sil_blacklist[n].product, model_num)) { 550 quirks = sil_blacklist[n].quirk; 551 break; 552 } 553 554 /* limit requests to 15 sectors */ 555 if (slow_down || 556 ((ap->flags & SIL_FLAG_MOD15WRITE) && 557 (quirks & SIL_QUIRK_MOD15WRITE))) { 558 if (print_info) 559 ata_dev_printk(dev, KERN_INFO, "applying Seagate " 560 "errata fix (mod15write workaround)\n"); 561 dev->max_sectors = 15; 562 return; 563 } 564 565 /* limit to udma5 */ 566 if (quirks & SIL_QUIRK_UDMA5MAX) { 567 if (print_info) 568 ata_dev_printk(dev, KERN_INFO, "applying Maxtor " 569 "errata fix %s\n", model_num); 570 dev->udma_mask &= ATA_UDMA5; 571 return; 572 } 573} 574 575static void sil_init_controller(struct pci_dev *pdev, 576 int n_ports, unsigned long port_flags, 577 void __iomem *mmio_base) 578{ 579 u8 cls; 580 u32 tmp; 581 int i; 582 583 /* Initialize FIFO PCI bus arbitration */ 584 cls = sil_get_device_cache_line(pdev); 585 if (cls) { 586 cls >>= 3; 587 cls++; /* cls = (line_size/8)+1 */ 588 for (i = 0; i < n_ports; i++) 589 writew(cls << 8 | cls, 590 mmio_base + sil_port[i].fifo_cfg); 591 } else 592 dev_printk(KERN_WARNING, &pdev->dev, 593 "cache line size not set. Driver may not function\n"); 594 595 /* Apply R_ERR on DMA activate FIS errata workaround */ 596 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) { 597 int cnt; 598 599 for (i = 0, cnt = 0; i < n_ports; i++) { 600 tmp = readl(mmio_base + sil_port[i].sfis_cfg); 601 if ((tmp & 0x3) != 0x01) 602 continue; 603 if (!cnt) 604 dev_printk(KERN_INFO, &pdev->dev, 605 "Applying R_ERR on DMA activate " 606 "FIS errata fix\n"); 607 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); 608 cnt++; 609 } 610 } 611 612 if (n_ports == 4) { 613 /* flip the magic "make 4 ports work" bit */ 614 tmp = readl(mmio_base + sil_port[2].bmdma); 615 if ((tmp & SIL_INTR_STEERING) == 0) 616 writel(tmp | SIL_INTR_STEERING, 617 mmio_base + sil_port[2].bmdma); 618 } 619} 620 621static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 622{ 623 static int printed_version; 624 struct ata_probe_ent *probe_ent = NULL; 625 unsigned long base; 626 void __iomem *mmio_base; 627 int rc; 628 unsigned int i; 629 int pci_dev_busy = 0; 630 631 if (!printed_version++) 632 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 633 634 rc = pci_enable_device(pdev); 635 if (rc) 636 return rc; 637 638 rc = pci_request_regions(pdev, DRV_NAME); 639 if (rc) { 640 pci_dev_busy = 1; 641 goto err_out; 642 } 643 644 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 645 if (rc) 646 goto err_out_regions; 647 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 648 if (rc) 649 goto err_out_regions; 650 651 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); 652 if (probe_ent == NULL) { 653 rc = -ENOMEM; 654 goto err_out_regions; 655 } 656 657 INIT_LIST_HEAD(&probe_ent->node); 658 probe_ent->dev = pci_dev_to_dev(pdev); 659 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; 660 probe_ent->sht = sil_port_info[ent->driver_data].sht; 661 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; 662 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; 663 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; 664 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; 665 probe_ent->irq = pdev->irq; 666 probe_ent->irq_flags = IRQF_SHARED; 667 probe_ent->port_flags = sil_port_info[ent->driver_data].flags; 668 669 mmio_base = pci_iomap(pdev, 5, 0); 670 if (mmio_base == NULL) { 671 rc = -ENOMEM; 672 goto err_out_free_ent; 673 } 674 675 probe_ent->mmio_base = mmio_base; 676 677 base = (unsigned long) mmio_base; 678 679 for (i = 0; i < probe_ent->n_ports; i++) { 680 probe_ent->port[i].cmd_addr = base + sil_port[i].tf; 681 probe_ent->port[i].altstatus_addr = 682 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; 683 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; 684 probe_ent->port[i].scr_addr = base + sil_port[i].scr; 685 ata_std_ports(&probe_ent->port[i]); 686 } 687 688 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, 689 mmio_base); 690 691 pci_set_master(pdev); 692 693 /* FIXME: check ata_device_add return value */ 694 ata_device_add(probe_ent); 695 kfree(probe_ent); 696 697 return 0; 698 699err_out_free_ent: 700 kfree(probe_ent); 701err_out_regions: 702 pci_release_regions(pdev); 703err_out: 704 if (!pci_dev_busy) 705 pci_disable_device(pdev); 706 return rc; 707} 708 709#ifdef CONFIG_PM 710static int sil_pci_device_resume(struct pci_dev *pdev) 711{ 712 struct ata_host *host = dev_get_drvdata(&pdev->dev); 713 714 ata_pci_device_do_resume(pdev); 715 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, 716 host->mmio_base); 717 ata_host_resume(host); 718 719 return 0; 720} 721#endif 722 723static int __init sil_init(void) 724{ 725 return pci_register_driver(&sil_pci_driver); 726} 727 728static void __exit sil_exit(void) 729{ 730 pci_unregister_driver(&sil_pci_driver); 731} 732 733 734module_init(sil_init); 735module_exit(sil_exit); 736