1173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/* 2f3c677b997757326e1f29d33060719a6a5091950Forrest Shi * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. 3173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 4173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Author: 5173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 6173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 7173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 8173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * This is free software; you can redistribute it and/or modify 9173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * it under the terms of the GNU General Public License as published by 10173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * the Free Software Foundation; either version 2 of the License, or 11173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * (at your option) any later version. 12173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 13173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 14173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#ifndef __DMA_FSLDMA_H 15173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define __DMA_FSLDMA_H 16173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 17173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/device.h> 18173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/dmapool.h> 19173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/dmaengine.h> 20173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 21173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/* Define data structures needed by Freescale 22173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * MPC8540 and MPC8349 DMA controller. 23173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 24173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_CS 0x00000001 25173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_CC 0x00000002 26173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_CA 0x00000008 27173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EIE 0x00000040 28173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_XFE 0x00000020 29173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EOLNIE 0x00000100 30173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EOLSIE 0x00000080 31173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EOSIE 0x00000200 32173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_CDSM 0x00000010 33173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_CTM 0x00000004 34173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EMP_EN 0x00200000 35173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EMS_EN 0x00040000 36173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_DAHE 0x00002000 37173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_SAHE 0x00001000 38173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 39f3c677b997757326e1f29d33060719a6a5091950Forrest Shi/* 40f3c677b997757326e1f29d33060719a6a5091950Forrest Shi * Bandwidth/pause control determines how many bytes a given 41f3c677b997757326e1f29d33060719a6a5091950Forrest Shi * channel is allowed to transfer before the DMA engine pauses 42f3c677b997757326e1f29d33060719a6a5091950Forrest Shi * the current channel and switches to the next channel 43f3c677b997757326e1f29d33060719a6a5091950Forrest Shi */ 44f3c677b997757326e1f29d33060719a6a5091950Forrest Shi#define FSL_DMA_MR_BWC 0x08000000 45f3c677b997757326e1f29d33060719a6a5091950Forrest Shi 46173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/* Special MR definition for MPC8349 */ 47173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MR_EOTIE 0x00000080 48a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder#define FSL_DMA_MR_PRC_RM 0x00000800 49173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 50173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_CH 0x00000020 51f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei#define FSL_DMA_SR_PE 0x00000010 52173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_CB 0x00000004 53173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_TE 0x00000080 54173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_EOSI 0x00000002 55173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_EOLSI 0x00000001 56173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_EOCDI 0x00000001 57173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SR_EOLNI 0x00000008 58173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 59173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SATR_SBPATMU 0x20000000 60173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000 61173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000 62173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000 63173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000 64173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000 65173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 66173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DATR_DBPATMU 0x20000000 67173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000 68173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000 69173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000 70173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 71173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_EOL ((u64)0x1) 72173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_SNEN ((u64)0x10) 73173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_EOSIE 0x8 74173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_NLDA_MASK (~(u64)0x1f) 75173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 76173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu 77173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 78173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_TE 0x80 79173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_CH 0x20 80173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_PE 0x10 81173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_EOLNI 0x08 82173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_CB 0x04 83173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_EOSI 0x02 84173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_DGSR_EOLSI 0x01 85173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 86a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Virotypedef u64 __bitwise v64; 87a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Virotypedef u32 __bitwise v32; 88a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro 89173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistruct fsl_dma_ld_hw { 90a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro v64 src_addr; 91a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro v64 dst_addr; 92a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro v64 next_ln_addr; 93a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro v32 count; 94a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro v32 reserve; 95173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} __attribute__((aligned(32))); 96173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 97173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistruct fsl_desc_sw { 98173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_dma_ld_hw hw; 99173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct list_head node; 100eda34234578fd822c950fd06b5c5ff7ac08b3001Dan Williams struct list_head tx_list; 101173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct dma_async_tx_descriptor async_tx; 102173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} __attribute__((aligned(32))); 103173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 104a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstruct fsldma_chan_regs { 10531f4306c83a2daa3e348056b720de511bffe5a9bIra Snyder u32 mr; /* 0x00 - Mode Register */ 10631f4306c83a2daa3e348056b720de511bffe5a9bIra Snyder u32 sr; /* 0x04 - Status Register */ 107a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro u64 cdar; /* 0x08 - Current descriptor address register */ 108a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro u64 sar; /* 0x10 - Source Address Register */ 109a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro u64 dar; /* 0x18 - Destination Address Register */ 110a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro u32 bcr; /* 0x20 - Byte Count Register */ 111a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro u64 ndar; /* 0x24 - Next Descriptor Address Register */ 112173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei}; 113173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 114a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstruct fsldma_chan; 115173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_MAX_CHANS_PER_DEVICE 4 116173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 117a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstruct fsldma_device { 118e7a29151de1bd52081f27f149b68074fac0323beIra Snyder void __iomem *regs; /* DGSR register base */ 119173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct device *dev; 120173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct dma_device common; 121a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; 122173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei u32 feature; /* The same as DMA channels */ 12377cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi int irq; /* Channel IRQ */ 124173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei}; 125173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 126a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/* Define macros for fsldma_chan->feature property */ 127173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_LITTLE_ENDIAN 0x00000000 128173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_BIG_ENDIAN 0x00000001 129173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 130173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_IP_MASK 0x00000ff0 131173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_IP_85XX 0x00000010 132173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_IP_83XX 0x00000020 133173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 134173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000 135173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define FSL_DMA_CHAN_START_EXT 0x00002000 136173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 137a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstruct fsldma_chan { 138b158471ef63bf399165db96e945a828096502d9dIra Snyder char name[8]; /* Channel name */ 139e7a29151de1bd52081f27f149b68074fac0323beIra Snyder struct fsldma_chan_regs __iomem *regs; 140173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cookie_t completed_cookie; /* The maximum cookie completed */ 141173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei spinlock_t desc_lock; /* Descriptor operation lock */ 1429c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct list_head ld_pending; /* Link descriptors queue */ 1439c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct list_head ld_running; /* Link descriptors queue */ 144173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct dma_chan common; /* DMA common channel */ 145173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct dma_pool *desc_pool; /* Descriptors pool */ 146173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct device *dev; /* Channel device */ 147173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei int irq; /* Channel IRQ */ 148173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei int id; /* Raw id of this channel */ 149173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct tasklet_struct tasklet; 150173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei u32 feature; 151f04cd40701deace2efb9edd7120e59366bda2118Ira Snyder bool idle; /* DMA controller is idle */ 152173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 153a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable); 154a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable); 155a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size); 156738f5f7e1ae876448cb7d9c82bea258b69386647Ira Snyder void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size); 157a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder void (*set_request_count)(struct fsldma_chan *fsl_chan, int size); 158173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei}; 159173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 160a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common) 161173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) 162173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) 163173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 164173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#ifndef __powerpc64__ 165173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic u64 in_be64(const u64 __iomem *addr) 166173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 167a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro return ((u64)in_be32((u32 __iomem *)addr) << 32) | 168a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro (in_be32((u32 __iomem *)addr + 1)); 169173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 170173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 171173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic void out_be64(u64 __iomem *addr, u64 val) 172173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 173a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro out_be32((u32 __iomem *)addr, val >> 32); 174a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro out_be32((u32 __iomem *)addr + 1, (u32)val); 175173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 176173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 177173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/* There is no asm instructions for 64 bits reverse loads and stores */ 178173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic u64 in_le64(const u64 __iomem *addr) 179173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 180a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) | 181a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro (in_le32((u32 __iomem *)addr)); 182173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 183173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 184173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic void out_le64(u64 __iomem *addr, u64 val) 185173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 186a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro out_le32((u32 __iomem *)addr + 1, val >> 32); 187a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro out_le32((u32 __iomem *)addr, (u32)val); 188173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 189173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#endif 190173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 191173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define DMA_IN(fsl_chan, addr, width) \ 192173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 193173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei in_be##width(addr) : in_le##width(addr)) 194173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define DMA_OUT(fsl_chan, addr, val, width) \ 195173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 196173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei out_be##width(addr, val) : out_le##width(addr, val)) 197173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 198173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define DMA_TO_CPU(fsl_chan, d, width) \ 199173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 200a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro be##width##_to_cpu((__force __be##width)(v##width)d) : \ 201a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro le##width##_to_cpu((__force __le##width)(v##width)d)) 202173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#define CPU_TO_DMA(fsl_chan, c, width) \ 203173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 204a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro (__force v##width)cpu_to_be##width(c) : \ 205a4e6d5d3817ebae167e78e5957cd9e624be200c7Al Viro (__force v##width)cpu_to_le##width(c)) 206173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 207173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#endif /* __DMA_FSLDMA_H */ 208