gpio-pl061.c revision 3ab52475447641a6facf6ee5450bea24e477b811 
1/*
2 * Copyright (C) 2008, 2009 Provigent Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
9 *
10 * Data sheet: ARM DDI 0190B, September 2000
11 */
12#include <linux/spinlock.h>
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/bitops.h>
20#include <linux/workqueue.h>
21#include <linux/gpio.h>
22#include <linux/device.h>
23#include <linux/amba/bus.h>
24#include <linux/amba/pl061.h>
25#include <linux/slab.h>
26#include <asm/mach/irq.h>
27
28#define GPIODIR 0x400
29#define GPIOIS  0x404
30#define GPIOIBE 0x408
31#define GPIOIEV 0x40C
32#define GPIOIE  0x410
33#define GPIORIS 0x414
34#define GPIOMIS 0x418
35#define GPIOIC  0x41C
36
37#define PL061_GPIO_NR	8
38
39struct pl061_gpio {
40	/* We use a list of pl061_gpio structs for each trigger IRQ in the main
41	 * interrupts controller of the system. We need this to support systems
42	 * in which more that one PL061s are connected to the same IRQ. The ISR
43	 * interates through this list to find the source of the interrupt.
44	 */
45	struct list_head	list;
46
47	/* Each of the two spinlocks protects a different set of hardware
48	 * regiters and data structurs. This decouples the code of the IRQ from
49	 * the GPIO code. This also makes the case of a GPIO routine call from
50	 * the IRQ code simpler.
51	 */
52	spinlock_t		lock;		/* GPIO registers */
53
54	void __iomem		*base;
55	int			irq_base;
56	struct irq_chip_generic	*irq_gc;
57	struct gpio_chip	gc;
58};
59
60static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
61{
62	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
63	unsigned long flags;
64	unsigned char gpiodir;
65
66	if (offset >= gc->ngpio)
67		return -EINVAL;
68
69	spin_lock_irqsave(&chip->lock, flags);
70	gpiodir = readb(chip->base + GPIODIR);
71	gpiodir &= ~(1 << offset);
72	writeb(gpiodir, chip->base + GPIODIR);
73	spin_unlock_irqrestore(&chip->lock, flags);
74
75	return 0;
76}
77
78static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
79		int value)
80{
81	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
82	unsigned long flags;
83	unsigned char gpiodir;
84
85	if (offset >= gc->ngpio)
86		return -EINVAL;
87
88	spin_lock_irqsave(&chip->lock, flags);
89	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
90	gpiodir = readb(chip->base + GPIODIR);
91	gpiodir |= 1 << offset;
92	writeb(gpiodir, chip->base + GPIODIR);
93
94	/*
95	 * gpio value is set again, because pl061 doesn't allow to set value of
96	 * a gpio pin before configuring it in OUT mode.
97	 */
98	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
99	spin_unlock_irqrestore(&chip->lock, flags);
100
101	return 0;
102}
103
104static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
105{
106	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
107
108	return !!readb(chip->base + (1 << (offset + 2)));
109}
110
111static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
112{
113	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
114
115	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
116}
117
118static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
119{
120	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
121
122	if (chip->irq_base <= 0)
123		return -EINVAL;
124
125	return chip->irq_base + offset;
126}
127
128static int pl061_irq_type(struct irq_data *d, unsigned trigger)
129{
130	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
131	struct pl061_gpio *chip = gc->private;
132	int offset = d->irq - chip->irq_base;
133	unsigned long flags;
134	u8 gpiois, gpioibe, gpioiev;
135
136	if (offset < 0 || offset >= PL061_GPIO_NR)
137		return -EINVAL;
138
139	raw_spin_lock_irqsave(&gc->lock, flags);
140
141	gpioiev = readb(chip->base + GPIOIEV);
142
143	gpiois = readb(chip->base + GPIOIS);
144	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
145		gpiois |= 1 << offset;
146		if (trigger & IRQ_TYPE_LEVEL_HIGH)
147			gpioiev |= 1 << offset;
148		else
149			gpioiev &= ~(1 << offset);
150	} else
151		gpiois &= ~(1 << offset);
152	writeb(gpiois, chip->base + GPIOIS);
153
154	gpioibe = readb(chip->base + GPIOIBE);
155	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
156		gpioibe |= 1 << offset;
157	else {
158		gpioibe &= ~(1 << offset);
159		if (trigger & IRQ_TYPE_EDGE_RISING)
160			gpioiev |= 1 << offset;
161		else if (trigger & IRQ_TYPE_EDGE_FALLING)
162			gpioiev &= ~(1 << offset);
163	}
164	writeb(gpioibe, chip->base + GPIOIBE);
165
166	writeb(gpioiev, chip->base + GPIOIEV);
167
168	raw_spin_unlock_irqrestore(&gc->lock, flags);
169
170	return 0;
171}
172
173static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
174{
175	struct list_head *chip_list = irq_get_handler_data(irq);
176	struct list_head *ptr;
177	struct pl061_gpio *chip;
178	struct irq_chip *irqchip = irq_desc_get_chip(desc);
179
180	chained_irq_enter(irqchip, desc);
181	list_for_each(ptr, chip_list) {
182		unsigned long pending;
183		int offset;
184
185		chip = list_entry(ptr, struct pl061_gpio, list);
186		pending = readb(chip->base + GPIOMIS);
187		writeb(pending, chip->base + GPIOIC);
188
189		if (pending == 0)
190			continue;
191
192		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
193			generic_handle_irq(pl061_to_irq(&chip->gc, offset));
194	}
195	chained_irq_exit(irqchip, desc);
196}
197
198static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
199{
200	struct irq_chip_type *ct;
201
202	chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
203					      chip->base, handle_simple_irq);
204	chip->irq_gc->private = chip;
205
206	ct = chip->irq_gc->chip_types;
207	ct->chip.irq_mask = irq_gc_mask_clr_bit;
208	ct->chip.irq_unmask = irq_gc_mask_set_bit;
209	ct->chip.irq_set_type = pl061_irq_type;
210	ct->chip.irq_set_wake = irq_gc_set_wake;
211	ct->regs.mask = GPIOIE;
212
213	irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
214			       IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
215}
216
217static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
218{
219	struct pl061_platform_data *pdata;
220	struct pl061_gpio *chip;
221	struct list_head *chip_list;
222	int ret, irq, i;
223	static DECLARE_BITMAP(init_irq, NR_IRQS);
224
225	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
226	if (chip == NULL)
227		return -ENOMEM;
228
229	pdata = dev->dev.platform_data;
230	if (pdata) {
231		chip->gc.base = pdata->gpio_base;
232		chip->irq_base = pdata->irq_base;
233	} else if (dev->dev.of_node) {
234		chip->gc.base = -1;
235		chip->irq_base = 0;
236	} else {
237		ret = -ENODEV;
238		goto free_mem;
239	}
240
241	if (!request_mem_region(dev->res.start,
242				resource_size(&dev->res), "pl061")) {
243		ret = -EBUSY;
244		goto free_mem;
245	}
246
247	chip->base = ioremap(dev->res.start, resource_size(&dev->res));
248	if (chip->base == NULL) {
249		ret = -ENOMEM;
250		goto release_region;
251	}
252
253	spin_lock_init(&chip->lock);
254	INIT_LIST_HEAD(&chip->list);
255
256	chip->gc.direction_input = pl061_direction_input;
257	chip->gc.direction_output = pl061_direction_output;
258	chip->gc.get = pl061_get_value;
259	chip->gc.set = pl061_set_value;
260	chip->gc.to_irq = pl061_to_irq;
261	chip->gc.ngpio = PL061_GPIO_NR;
262	chip->gc.label = dev_name(&dev->dev);
263	chip->gc.dev = &dev->dev;
264	chip->gc.owner = THIS_MODULE;
265
266	ret = gpiochip_add(&chip->gc);
267	if (ret)
268		goto iounmap;
269
270	/*
271	 * irq_chip support
272	 */
273
274	if (chip->irq_base <= 0)
275		return 0;
276
277	pl061_init_gc(chip, chip->irq_base);
278
279	writeb(0, chip->base + GPIOIE); /* disable irqs */
280	irq = dev->irq[0];
281	if (irq < 0) {
282		ret = -ENODEV;
283		goto iounmap;
284	}
285	irq_set_chained_handler(irq, pl061_irq_handler);
286	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
287		chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
288		if (chip_list == NULL) {
289			clear_bit(irq, init_irq);
290			ret = -ENOMEM;
291			goto iounmap;
292		}
293		INIT_LIST_HEAD(chip_list);
294		irq_set_handler_data(irq, chip_list);
295	} else
296		chip_list = irq_get_handler_data(irq);
297	list_add(&chip->list, chip_list);
298
299	for (i = 0; i < PL061_GPIO_NR; i++) {
300		if (pdata) {
301			if (pdata->directions & (1 << i))
302				pl061_direction_output(&chip->gc, i,
303						pdata->values & (1 << i));
304			else
305				pl061_direction_input(&chip->gc, i);
306		}
307	}
308
309	return 0;
310
311iounmap:
312	iounmap(chip->base);
313release_region:
314	release_mem_region(dev->res.start, resource_size(&dev->res));
315free_mem:
316	kfree(chip);
317
318	return ret;
319}
320
321static struct amba_id pl061_ids[] = {
322	{
323		.id	= 0x00041061,
324		.mask	= 0x000fffff,
325	},
326	{ 0, 0 },
327};
328
329static struct amba_driver pl061_gpio_driver = {
330	.drv = {
331		.name	= "pl061_gpio",
332	},
333	.id_table	= pl061_ids,
334	.probe		= pl061_probe,
335};
336
337static int __init pl061_gpio_init(void)
338{
339	return amba_driver_register(&pl061_gpio_driver);
340}
341subsys_initcall(pl061_gpio_init);
342
343MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
344MODULE_DESCRIPTION("PL061 GPIO driver");
345MODULE_LICENSE("GPL");
346