intel_ringbuffer.h revision 78501eac34f372bfbeb4e1d9de688c13efa916f6
18187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai#ifndef _INTEL_RINGBUFFER_H_ 28187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai#define _INTEL_RINGBUFFER_H_ 38187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 48187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistruct intel_hw_status_page { 578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 __iomem *page_addr; 68187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai unsigned int gfx_addr; 78187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct drm_gem_object *obj; 88187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai}; 98187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 10870e86ddc2d110124812b277643ed0f2767148eeDaniel Vetter#define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base)) 11870e86ddc2d110124812b277643ed0f2767148eeDaniel Vetter#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val) 126c0e1c556ee659cd8c976cd175c0b70e209acb92Daniel Vetter#define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base)) 136c0e1c556ee659cd8c976cd175c0b70e209acb92Daniel Vetter#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) 14570ef608591aa1c7f7cb615c2d33b30246179da1Daniel Vetter#define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base)) 15570ef608591aa1c7f7cb615c2d33b30246179da1Daniel Vetter#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) 167f2ab69913135f0377a1dfc1da5695b64107d3caDaniel Vetter#define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base)) 177f2ab69913135f0377a1dfc1da5695b64107d3caDaniel Vetter#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val) 18870e86ddc2d110124812b277643ed0f2767148eeDaniel Vetter 198187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistruct drm_i915_gem_execbuffer2; 208187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistruct intel_ring_buffer { 218187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai const char *name; 229220434a8768902cd9cf248709972678b74aa8c1Chris Wilson enum intel_ring_id { 239220434a8768902cd9cf248709972678b74aa8c1Chris Wilson RING_RENDER = 0x1, 249220434a8768902cd9cf248709972678b74aa8c1Chris Wilson RING_BSD = 0x2, 25549f7365820a212a1cfd0871d377b1ad0d1e5723Chris Wilson RING_BLT = 0x4, 269220434a8768902cd9cf248709972678b74aa8c1Chris Wilson } id; 27333e9fe94d00ce8c334d91099449b9948bf76b92Daniel Vetter u32 mmio_base; 288187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai unsigned long size; 298187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai void *virtual_start; 308187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct drm_device *dev; 318187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct drm_gem_object *gem_object; 328187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 338187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai unsigned int head; 348187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai unsigned int tail; 35780f0ca3e0cd3f0677d9149b7e14bf0878d1dbdcChris Wilson int space; 368187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct intel_hw_status_page status_page; 378187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 388187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai u32 irq_gem_seqno; /* last seq seem at irq time */ 398187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai u32 waiting_gem_seqno; 408187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai int user_irq_refcount; 4178501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson void (*user_irq_get)(struct intel_ring_buffer *ring); 4278501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson void (*user_irq_put)(struct intel_ring_buffer *ring); 438187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 4478501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson int (*init)(struct intel_ring_buffer *ring); 458187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 4678501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson void (*write_tail)(struct intel_ring_buffer *ring, 47297b0c5be3b6e08890cbd7149313408847e81715Chris Wilson u32 value); 4878501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson void (*flush)(struct intel_ring_buffer *ring, 4978501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 invalidate_domains, 5078501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 flush_domains); 5178501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 (*add_request)(struct intel_ring_buffer *ring, 5278501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 flush_domains); 5378501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 (*get_seqno)(struct intel_ring_buffer *ring); 5478501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, 5578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson struct drm_i915_gem_execbuffer2 *exec, 5678501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson struct drm_clip_rect *cliprects, 5778501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson uint64_t exec_offset); 588187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 598187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai /** 608187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * List of objects currently involved in rendering from the 618187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * ringbuffer. 628187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * 638187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * Includes buffers having the contents of their GPU caches 648187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * flushed, not necessarily primitives. last_rendering_seqno 658187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * represents when the rendering involved will be completed. 668187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * 678187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * A reference is held on the buffer while on this list. 688187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai */ 698187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct list_head active_list; 708187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 718187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai /** 728187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * List of breadcrumbs associated with GPU requests currently 738187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * outstanding. 748187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai */ 758187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct list_head request_list; 768187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 77a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson /** 78641934069d29211baf82afb93622a426172b67b6Chris Wilson * List of objects currently pending a GPU write flush. 79641934069d29211baf82afb93622a426172b67b6Chris Wilson * 80641934069d29211baf82afb93622a426172b67b6Chris Wilson * All elements on this list will belong to either the 81641934069d29211baf82afb93622a426172b67b6Chris Wilson * active_list or flushing_list, last_rendering_seqno can 82641934069d29211baf82afb93622a426172b67b6Chris Wilson * be used to differentiate between the two elements. 83641934069d29211baf82afb93622a426172b67b6Chris Wilson */ 84641934069d29211baf82afb93622a426172b67b6Chris Wilson struct list_head gpu_write_list; 85641934069d29211baf82afb93622a426172b67b6Chris Wilson 86641934069d29211baf82afb93622a426172b67b6Chris Wilson /** 87a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson * Do we have some not yet emitted requests outstanding? 88a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson */ 89a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson bool outstanding_lazy_request; 90a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson 918187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai wait_queue_head_t irq_queue; 928187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai drm_local_map_t map; 938187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai}; 948187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 958187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistatic inline u32 968187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haiintel_read_status_page(struct intel_ring_buffer *ring, 9778501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson int reg) 988187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai{ 9978501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson return ioread32(ring->status_page.page_addr + reg); 1008187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai} 1018187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 10278501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 10378501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonint intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 10478501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_ring_begin(struct intel_ring_buffer *ring, int n); 10578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson 10678501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonstatic inline void intel_ring_emit(struct intel_ring_buffer *ring, 10778501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 data) 108e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson{ 10978501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson iowrite32(data, ring->virtual_start + ring->tail); 110e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson ring->tail += 4; 111e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson} 112e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson 11378501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_ring_advance(struct intel_ring_buffer *ring); 1148187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 11578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonu32 intel_ring_get_seqno(struct intel_ring_buffer *ring); 1168187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 1175c1143bbecf50184ff7cad6287b4e0993bacbd9fXiang, Haihaoint intel_init_render_ring_buffer(struct drm_device *dev); 1185c1143bbecf50184ff7cad6287b4e0993bacbd9fXiang, Haihaoint intel_init_bsd_ring_buffer(struct drm_device *dev); 119549f7365820a212a1cfd0871d377b1ad0d1e5723Chris Wilsonint intel_init_blt_ring_buffer(struct drm_device *dev); 1208187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 12178501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonu32 intel_ring_get_active_head(struct intel_ring_buffer *ring); 12278501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_ring_setup_status_page(struct intel_ring_buffer *ring); 12379f321b7e676bd54f563c5ce513588aa90b2cc21Daniel Vetter 1248187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai#endif /* _INTEL_RINGBUFFER_H_ */ 125