intel_ringbuffer.h revision c8c99b0f0dea1ced5d0e10cdb9143356cc16b484
18187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai#ifndef _INTEL_RINGBUFFER_H_ 28187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai#define _INTEL_RINGBUFFER_H_ 38187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 41ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilsonenum { 50206e353a0416ad63ce07f53c807c2c725633b87Akshay Joshi RCS = 0x0, 60206e353a0416ad63ce07f53c807c2c725633b87Akshay Joshi VCS, 70206e353a0416ad63ce07f53c807c2c725633b87Akshay Joshi BCS, 80206e353a0416ad63ce07f53c807c2c725633b87Akshay Joshi I915_NUM_RINGS, 91ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson}; 101ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson 118187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistruct intel_hw_status_page { 1278501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 __iomem *page_addr; 138187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai unsigned int gfx_addr; 1405394f3975dceb107a5e1393e2244946e5b43660Chris Wilson struct drm_i915_gem_object *obj; 158187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai}; 168187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 17b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) 18b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) 19cae5852dcaa1139b198e13ebd3aeb7f3c065f875Zou Nan hai 20b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) 21b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) 22cae5852dcaa1139b198e13ebd3aeb7f3c065f875Zou Nan hai 23b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) 24b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) 25cae5852dcaa1139b198e13ebd3aeb7f3c065f875Zou Nan hai 26b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) 27b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) 28cae5852dcaa1139b198e13ebd3aeb7f3c065f875Zou Nan hai 29b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) 30b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) 31870e86ddc2d110124812b277643ed0f2767148eeDaniel Vetter 32b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) 33b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) 34b7287d8054d219b3009f7ca82edf24f89fd363e5Ben Widawsky#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) 351ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson 368187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistruct intel_ring_buffer { 378187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai const char *name; 389220434a8768902cd9cf248709972678b74aa8c1Chris Wilson enum intel_ring_id { 399220434a8768902cd9cf248709972678b74aa8c1Chris Wilson RING_RENDER = 0x1, 409220434a8768902cd9cf248709972678b74aa8c1Chris Wilson RING_BSD = 0x2, 41549f7365820a212a1cfd0871d377b1ad0d1e5723Chris Wilson RING_BLT = 0x4, 429220434a8768902cd9cf248709972678b74aa8c1Chris Wilson } id; 43333e9fe94d00ce8c334d91099449b9948bf76b92Daniel Vetter u32 mmio_base; 44311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson void __iomem *virtual_start; 458187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct drm_device *dev; 4605394f3975dceb107a5e1393e2244946e5b43660Chris Wilson struct drm_i915_gem_object *obj; 478187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 488c0a6bfef165ccdbf5d73afb9dd660107b0c98d5Chris Wilson u32 head; 498c0a6bfef165ccdbf5d73afb9dd660107b0c98d5Chris Wilson u32 tail; 50780f0ca3e0cd3f0677d9149b7e14bf0878d1dbdcChris Wilson int space; 51c2c347a9eeda1b9b69c8fc393fd933747fbb2e11Chris Wilson int size; 5255249baaa5cd188ebd9acdb047eeaed8092e4a93Chris Wilson int effective_size; 538187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct intel_hw_status_page status_page; 548187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 550dc79fb2a36efcadbb39bd8b28933d8aa40408b1Chris Wilson spinlock_t irq_lock; 5601a03331e5fe91861937f8b8e72c259f5e9eae67Chris Wilson u32 irq_refcount; 570f46832fab779a9a3314ce5e833155fe4cf18f6cChris Wilson u32 irq_mask; 58b2223497b44a4701d1be873d1e9453d7f720043bChris Wilson u32 irq_seqno; /* last seq seem at irq time */ 59db53a302611c06bde01851f61fa0675a84ca018cChris Wilson u32 trace_irq_seqno; 60b2223497b44a4701d1be873d1e9453d7f720043bChris Wilson u32 waiting_seqno; 611ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson u32 sync_seqno[I915_NUM_RINGS-1]; 62b13c2b96bf15b9dd0f1a45fd788f3a3025c5aec6Chris Wilson bool __must_check (*irq_get)(struct intel_ring_buffer *ring); 631ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson void (*irq_put)(struct intel_ring_buffer *ring); 648187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 6578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson int (*init)(struct intel_ring_buffer *ring); 668187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 6778501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson void (*write_tail)(struct intel_ring_buffer *ring, 68297b0c5be3b6e08890cbd7149313408847e81715Chris Wilson u32 value); 69b72f3acb71646de073abdc070fe1108866c96634Chris Wilson int __must_check (*flush)(struct intel_ring_buffer *ring, 70b72f3acb71646de073abdc070fe1108866c96634Chris Wilson u32 invalidate_domains, 71b72f3acb71646de073abdc070fe1108866c96634Chris Wilson u32 flush_domains); 723cce469cab880ef8990d2d16d745bf85443fc998Chris Wilson int (*add_request)(struct intel_ring_buffer *ring, 733cce469cab880ef8990d2d16d745bf85443fc998Chris Wilson u32 *seqno); 7478501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 (*get_seqno)(struct intel_ring_buffer *ring); 7578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, 76c4e7a4146798ce22c229dd21ed31f59f07c4119eChris Wilson u32 offset, u32 length); 778d19215be8254f4f75e9c5a0d28345947b0382dbZou Nan hai void (*cleanup)(struct intel_ring_buffer *ring); 78c8c99b0f0dea1ced5d0e10cdb9143356cc16b484Ben Widawsky int (*sync_to)(struct intel_ring_buffer *ring, 79c8c99b0f0dea1ced5d0e10cdb9143356cc16b484Ben Widawsky struct intel_ring_buffer *to, 80c8c99b0f0dea1ced5d0e10cdb9143356cc16b484Ben Widawsky u32 seqno); 818187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 82c8c99b0f0dea1ced5d0e10cdb9143356cc16b484Ben Widawsky u32 semaphore_register[3]; /*our mbox written by others */ 83c8c99b0f0dea1ced5d0e10cdb9143356cc16b484Ben Widawsky u32 signal_mbox[2]; /* mboxes this ring signals to */ 848187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai /** 858187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * List of objects currently involved in rendering from the 868187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * ringbuffer. 878187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * 888187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * Includes buffers having the contents of their GPU caches 898187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * flushed, not necessarily primitives. last_rendering_seqno 908187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * represents when the rendering involved will be completed. 918187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * 928187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * A reference is held on the buffer while on this list. 938187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai */ 948187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct list_head active_list; 958187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 968187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai /** 978187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * List of breadcrumbs associated with GPU requests currently 988187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai * outstanding. 998187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai */ 1008187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai struct list_head request_list; 1018187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 102a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson /** 103641934069d29211baf82afb93622a426172b67b6Chris Wilson * List of objects currently pending a GPU write flush. 104641934069d29211baf82afb93622a426172b67b6Chris Wilson * 105641934069d29211baf82afb93622a426172b67b6Chris Wilson * All elements on this list will belong to either the 106641934069d29211baf82afb93622a426172b67b6Chris Wilson * active_list or flushing_list, last_rendering_seqno can 107641934069d29211baf82afb93622a426172b67b6Chris Wilson * be used to differentiate between the two elements. 108641934069d29211baf82afb93622a426172b67b6Chris Wilson */ 109641934069d29211baf82afb93622a426172b67b6Chris Wilson struct list_head gpu_write_list; 110641934069d29211baf82afb93622a426172b67b6Chris Wilson 111641934069d29211baf82afb93622a426172b67b6Chris Wilson /** 112a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson * Do we have some not yet emitted requests outstanding? 113a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson */ 1145d97eb69bd4767ce9973360881fa6ad161510fb0Chris Wilson u32 outstanding_lazy_request; 115a56ba56c275b1c2b982c8901ab92bf5a0fd0b757Chris Wilson 1168187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai wait_queue_head_t irq_queue; 1178187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai drm_local_map_t map; 1188d19215be8254f4f75e9c5a0d28345947b0382dbZou Nan hai 1198d19215be8254f4f75e9c5a0d28345947b0382dbZou Nan hai void *private; 1208187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai}; 1218187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 1228187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haistatic inline u32 1231ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilsonintel_ring_sync_index(struct intel_ring_buffer *ring, 1241ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson struct intel_ring_buffer *other) 1251ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson{ 1261ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson int idx; 1271ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson 1281ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson /* 1291ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson * cs -> 0 = vcs, 1 = bcs 1301ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson * vcs -> 0 = bcs, 1 = cs, 1311ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson * bcs -> 0 = cs, 1 = vcs. 1321ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson */ 1331ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson 1341ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson idx = (other - ring) - 1; 1351ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson if (idx < 0) 1361ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson idx += I915_NUM_RINGS; 1371ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson 1381ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson return idx; 1391ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson} 1401ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilson 1411ec14ad3132702694f2e1a90b30641cf111183b9Chris Wilsonstatic inline u32 1428187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan haiintel_read_status_page(struct intel_ring_buffer *ring, 14378501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson int reg) 1448187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai{ 14578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson return ioread32(ring->status_page.page_addr + reg); 1468187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai} 1478187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 148311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson/** 149311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * Reads a dword out of the status page, which is written to from the command 150311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 151311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * MI_STORE_DATA_IMM. 152311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 153311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * The following dwords have a reserved meaning: 154311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 155311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 0x04: ring 0 head pointer 156311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 0x05: ring 1 head pointer (915-class) 157311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 0x06: ring 2 head pointer (915-class) 158311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 0x10-0x1b: Context status DWords (GM45) 159311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 0x1f: Last written status offset. (GM45) 160311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * 161311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson * The area from dword 0x20 to 0x3ff is available for driver usage. 162311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson */ 163311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson#define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg) 164311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 165311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson#define I915_GEM_HWS_INDEX 0x20 166311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson#define I915_BREADCRUMB_INDEX 0x21 167311bd68e024f9006db66cbadc3bd9f62fd663f4bChris Wilson 16878501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 16996f298aa9c9fc9b7c8a2ebaf8c195d178f570e09Ben Widawsky 170e1f99ce6cac3b6a95551642be5ddb5d9c46bea76Chris Wilsonint __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 17196f298aa9c9fc9b7c8a2ebaf8c195d178f570e09Ben Widawskystatic inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) 17296f298aa9c9fc9b7c8a2ebaf8c195d178f570e09Ben Widawsky{ 173a94919eaddaa3fede1df8563ce4d761a75374645Chris Wilson return intel_wait_ring_buffer(ring, ring->size - 8); 17496f298aa9c9fc9b7c8a2ebaf8c195d178f570e09Ben Widawsky} 17596f298aa9c9fc9b7c8a2ebaf8c195d178f570e09Ben Widawsky 176e1f99ce6cac3b6a95551642be5ddb5d9c46bea76Chris Wilsonint __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 17778501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson 17878501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonstatic inline void intel_ring_emit(struct intel_ring_buffer *ring, 17978501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson u32 data) 180e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson{ 18178501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilson iowrite32(data, ring->virtual_start + ring->tail); 182e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson ring->tail += 4; 183e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson} 184e898cd221db65273bfc102fa20e4e228e0b8c7e1Chris Wilson 18578501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_ring_advance(struct intel_ring_buffer *ring); 1868187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 18778501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonu32 intel_ring_get_seqno(struct intel_ring_buffer *ring); 1888187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 1895c1143bbecf50184ff7cad6287b4e0993bacbd9fXiang, Haihaoint intel_init_render_ring_buffer(struct drm_device *dev); 1905c1143bbecf50184ff7cad6287b4e0993bacbd9fXiang, Haihaoint intel_init_bsd_ring_buffer(struct drm_device *dev); 191549f7365820a212a1cfd0871d377b1ad0d1e5723Chris Wilsonint intel_init_blt_ring_buffer(struct drm_device *dev); 1928187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai 19378501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonu32 intel_ring_get_active_head(struct intel_ring_buffer *ring); 19478501eac34f372bfbeb4e1d9de688c13efa916f6Chris Wilsonvoid intel_ring_setup_status_page(struct intel_ring_buffer *ring); 19579f321b7e676bd54f563c5ce513588aa90b2cc21Daniel Vetter 196db53a302611c06bde01851f61fa0675a84ca018cChris Wilsonstatic inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) 197db53a302611c06bde01851f61fa0675a84ca018cChris Wilson{ 198db53a302611c06bde01851f61fa0675a84ca018cChris Wilson if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) 199db53a302611c06bde01851f61fa0675a84ca018cChris Wilson ring->trace_irq_seqno = seqno; 200db53a302611c06bde01851f61fa0675a84ca018cChris Wilson} 201db53a302611c06bde01851f61fa0675a84ca018cChris Wilson 202e8616b6ced6137085e6657cc63bc2fe3900b8616Chris Wilson/* DRI warts */ 203e8616b6ced6137085e6657cc63bc2fe3900b8616Chris Wilsonint intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); 204e8616b6ced6137085e6657cc63bc2fe3900b8616Chris Wilson 2058187a2b70e34c727a06617441f74f202b6fefaf9Zou Nan hai#endif /* _INTEL_RINGBUFFER_H_ */ 206