16ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "drmP.h" 26ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "drm_mode.h" 36ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_reg.h" 46ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_drv.h" 56ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_crtc.h" 66ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_hw.h" 76ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 86ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 96ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) 106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); 126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) 166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); 186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) 226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 23b334f2b3b68c35fd86a0cbc90ecee40e63ba2f37Maarten Maathuis nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; 246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, 256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_PRAMDAC_CU_START_POS, 266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | 276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); 286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggscrtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtcstate->CRTC[index]); 356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = nv_crtc->base.dev; 416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_crtc *crtc = &nv_crtc->base; 446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = 466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs MASK(NV_CIO_CRE_HCUR_ASI) | 476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); 486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = 496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); 506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); 536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; 546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type == NV_40) 596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_fix_nv40_hw_cursor(dev, nv_crtc->index); 606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsint 636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_cursor_init(struct nouveau_crtc *crtc) 646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc->cursor.set_offset = nv04_cursor_set_offset; 666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc->cursor.set_pos = nv04_cursor_set_pos; 676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc->cursor.hide = nv04_cursor_hide; 686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc->cursor.show = nv04_cursor_show; 696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return 0; 706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 72