nvc0_graph.c revision ea5f2786a0942832f32deb7c507531b766028356
1/* 2 * Copyright 2010 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25#include <linux/firmware.h> 26 27#include "drmP.h" 28 29#include "nouveau_drv.h" 30#include "nouveau_mm.h" 31#include "nvc0_graph.h" 32 33static void nvc0_graph_isr(struct drm_device *); 34static void nvc0_runk140_isr(struct drm_device *); 35static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan); 36 37void 38nvc0_graph_fifo_access(struct drm_device *dev, bool enabled) 39{ 40} 41 42struct nouveau_channel * 43nvc0_graph_channel(struct drm_device *dev) 44{ 45 return NULL; 46} 47 48static int 49nvc0_graph_construct_context(struct nouveau_channel *chan) 50{ 51 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 52 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; 53 struct nvc0_graph_chan *grch = chan->pgraph_ctx; 54 struct drm_device *dev = chan->dev; 55 int ret, i; 56 u32 *ctx; 57 58 ctx = kmalloc(priv->grctx_size, GFP_KERNEL); 59 if (!ctx) 60 return -ENOMEM; 61 62 nvc0_graph_load_context(chan); 63 64 nv_wo32(grch->grctx, 0x1c, 1); 65 nv_wo32(grch->grctx, 0x20, 0); 66 nv_wo32(grch->grctx, 0x28, 0); 67 nv_wo32(grch->grctx, 0x2c, 0); 68 dev_priv->engine.instmem.flush(dev); 69 70 ret = nvc0_grctx_generate(chan); 71 if (ret) { 72 kfree(ctx); 73 return ret; 74 } 75 76 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); 77 if (ret) { 78 kfree(ctx); 79 return ret; 80 } 81 82 for (i = 0; i < priv->grctx_size; i += 4) 83 ctx[i / 4] = nv_ro32(grch->grctx, i); 84 85 priv->grctx_vals = ctx; 86 return 0; 87} 88 89static int 90nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) 91{ 92 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 93 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; 94 struct nvc0_graph_chan *grch = chan->pgraph_ctx; 95 struct drm_device *dev = chan->dev; 96 int i = 0, gpc, tp, ret; 97 u32 magic; 98 99 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM, 100 &grch->unk408004); 101 if (ret) 102 return ret; 103 104 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM, 105 &grch->unk40800c); 106 if (ret) 107 return ret; 108 109 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096, 110 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER, 111 &grch->unk418810); 112 if (ret) 113 return ret; 114 115 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM, 116 &grch->mmio); 117 if (ret) 118 return ret; 119 120 121 nv_wo32(grch->mmio, i++ * 4, 0x00408004); 122 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8); 123 nv_wo32(grch->mmio, i++ * 4, 0x00408008); 124 nv_wo32(grch->mmio, i++ * 4, 0x80000018); 125 126 nv_wo32(grch->mmio, i++ * 4, 0x0040800c); 127 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8); 128 nv_wo32(grch->mmio, i++ * 4, 0x00408010); 129 nv_wo32(grch->mmio, i++ * 4, 0x80000000); 130 131 nv_wo32(grch->mmio, i++ * 4, 0x00418810); 132 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12); 133 nv_wo32(grch->mmio, i++ * 4, 0x00419848); 134 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12); 135 136 nv_wo32(grch->mmio, i++ * 4, 0x00419004); 137 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8); 138 nv_wo32(grch->mmio, i++ * 4, 0x00419008); 139 nv_wo32(grch->mmio, i++ * 4, 0x00000000); 140 141 nv_wo32(grch->mmio, i++ * 4, 0x00418808); 142 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8); 143 nv_wo32(grch->mmio, i++ * 4, 0x0041880c); 144 nv_wo32(grch->mmio, i++ * 4, 0x80000018); 145 146 magic = 0x02180000; 147 nv_wo32(grch->mmio, i++ * 4, 0x00405830); 148 nv_wo32(grch->mmio, i++ * 4, magic); 149 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 150 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) { 151 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800); 152 nv_wo32(grch->mmio, i++ * 4, reg); 153 nv_wo32(grch->mmio, i++ * 4, magic); 154 } 155 } 156 157 grch->mmio_nr = i / 2; 158 return 0; 159} 160 161int 162nvc0_graph_create_context(struct nouveau_channel *chan) 163{ 164 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 165 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; 166 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 167 struct nvc0_graph_priv *priv = pgraph->priv; 168 struct nvc0_graph_chan *grch; 169 struct drm_device *dev = chan->dev; 170 struct nouveau_gpuobj *grctx; 171 int ret, i; 172 173 chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL); 174 if (!chan->pgraph_ctx) 175 return -ENOMEM; 176 grch = chan->pgraph_ctx; 177 178 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256, 179 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC, 180 &grch->grctx); 181 if (ret) 182 goto error; 183 chan->ramin_grctx = grch->grctx; 184 grctx = grch->grctx; 185 186 ret = nvc0_graph_create_context_mmio_list(chan); 187 if (ret) 188 goto error; 189 190 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4); 191 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst)); 192 pinstmem->flush(dev); 193 194 if (!priv->grctx_vals) { 195 ret = nvc0_graph_construct_context(chan); 196 if (ret) 197 goto error; 198 } 199 200 for (i = 0; i < priv->grctx_size; i += 4) 201 nv_wo32(grctx, i, priv->grctx_vals[i / 4]); 202 203 nv_wo32(grctx, 0xf4, 0); 204 nv_wo32(grctx, 0xf8, 0); 205 nv_wo32(grctx, 0x10, grch->mmio_nr); 206 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst)); 207 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst)); 208 nv_wo32(grctx, 0x1c, 1); 209 nv_wo32(grctx, 0x20, 0); 210 nv_wo32(grctx, 0x28, 0); 211 nv_wo32(grctx, 0x2c, 0); 212 pinstmem->flush(dev); 213 return 0; 214 215error: 216 pgraph->destroy_context(chan); 217 return ret; 218} 219 220void 221nvc0_graph_destroy_context(struct nouveau_channel *chan) 222{ 223 struct nvc0_graph_chan *grch; 224 225 grch = chan->pgraph_ctx; 226 chan->pgraph_ctx = NULL; 227 if (!grch) 228 return; 229 230 nouveau_gpuobj_ref(NULL, &grch->mmio); 231 nouveau_gpuobj_ref(NULL, &grch->unk418810); 232 nouveau_gpuobj_ref(NULL, &grch->unk40800c); 233 nouveau_gpuobj_ref(NULL, &grch->unk408004); 234 nouveau_gpuobj_ref(NULL, &grch->grctx); 235 chan->ramin_grctx = NULL; 236} 237 238int 239nvc0_graph_load_context(struct nouveau_channel *chan) 240{ 241 struct drm_device *dev = chan->dev; 242 243 nv_wr32(dev, 0x409840, 0x00000030); 244 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); 245 nv_wr32(dev, 0x409504, 0x00000003); 246 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010)) 247 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n"); 248 249 return 0; 250} 251 252static int 253nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan) 254{ 255 nv_wr32(dev, 0x409840, 0x00000003); 256 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12); 257 nv_wr32(dev, 0x409504, 0x00000009); 258 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) { 259 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n"); 260 return -EBUSY; 261 } 262 263 return 0; 264} 265 266int 267nvc0_graph_unload_context(struct drm_device *dev) 268{ 269 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; 270 return nvc0_graph_unload_context_to(dev, inst); 271} 272 273static void 274nvc0_graph_destroy(struct drm_device *dev) 275{ 276 struct drm_nouveau_private *dev_priv = dev->dev_private; 277 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 278 struct nvc0_graph_priv *priv; 279 280 priv = pgraph->priv; 281 if (!priv) 282 return; 283 284 nouveau_irq_unregister(dev, 12); 285 nouveau_irq_unregister(dev, 25); 286 287 nouveau_gpuobj_ref(NULL, &priv->unk4188b8); 288 nouveau_gpuobj_ref(NULL, &priv->unk4188b4); 289 290 if (priv->grctx_vals) 291 kfree(priv->grctx_vals); 292 kfree(priv); 293} 294 295void 296nvc0_graph_takedown(struct drm_device *dev) 297{ 298 nvc0_graph_destroy(dev); 299} 300 301static int 302nvc0_graph_create(struct drm_device *dev) 303{ 304 struct drm_nouveau_private *dev_priv = dev->dev_private; 305 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 306 struct nvc0_graph_priv *priv; 307 int ret, gpc, i; 308 309 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 310 if (!priv) 311 return -ENOMEM; 312 pgraph->priv = priv; 313 314 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4); 315 if (ret) 316 goto error; 317 318 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8); 319 if (ret) 320 goto error; 321 322 for (i = 0; i < 0x1000; i += 4) { 323 nv_wo32(priv->unk4188b4, i, 0x00000010); 324 nv_wo32(priv->unk4188b8, i, 0x00000010); 325 } 326 327 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f; 328 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16; 329 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 330 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608)); 331 priv->tp_total += priv->tp_nr[gpc]; 332 } 333 334 /*XXX: these need figuring out... */ 335 switch (dev_priv->chipset) { 336 case 0xc0: 337 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */ 338 priv->magic_not_rop_nr = 0x07; 339 /* filled values up to tp_total, the rest 0 */ 340 priv->magicgpc980[0] = 0x22111000; 341 priv->magicgpc980[1] = 0x00000233; 342 priv->magicgpc980[2] = 0x00000000; 343 priv->magicgpc980[3] = 0x00000000; 344 priv->magicgpc918 = 0x000ba2e9; 345 } else 346 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */ 347 priv->magic_not_rop_nr = 0x05; 348 priv->magicgpc980[0] = 0x11110000; 349 priv->magicgpc980[1] = 0x00233222; 350 priv->magicgpc980[2] = 0x00000000; 351 priv->magicgpc980[3] = 0x00000000; 352 priv->magicgpc918 = 0x00092493; 353 } else 354 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */ 355 priv->magic_not_rop_nr = 0x06; 356 priv->magicgpc980[0] = 0x11110000; 357 priv->magicgpc980[1] = 0x03332222; 358 priv->magicgpc980[2] = 0x00000000; 359 priv->magicgpc980[3] = 0x00000000; 360 priv->magicgpc918 = 0x00088889; 361 } 362 break; 363 case 0xc3: /* 450, 4/0/0/0, 2 */ 364 priv->magic_not_rop_nr = 0x03; 365 priv->magicgpc980[0] = 0x00003210; 366 priv->magicgpc980[1] = 0x00000000; 367 priv->magicgpc980[2] = 0x00000000; 368 priv->magicgpc980[3] = 0x00000000; 369 priv->magicgpc918 = 0x00200000; 370 break; 371 case 0xc4: /* 460, 3/4/0/0, 4 */ 372 priv->magic_not_rop_nr = 0x01; 373 priv->magicgpc980[0] = 0x02321100; 374 priv->magicgpc980[1] = 0x00000000; 375 priv->magicgpc980[2] = 0x00000000; 376 priv->magicgpc980[3] = 0x00000000; 377 priv->magicgpc918 = 0x00124925; 378 break; 379 } 380 381 if (!priv->magic_not_rop_nr) { 382 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n", 383 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2], 384 priv->tp_nr[3], priv->rop_nr); 385 /* use 0xc3's values... */ 386 priv->magic_not_rop_nr = 0x03; 387 priv->magicgpc980[0] = 0x00003210; 388 priv->magicgpc980[1] = 0x00000000; 389 priv->magicgpc980[2] = 0x00000000; 390 priv->magicgpc980[3] = 0x00000000; 391 priv->magicgpc918 = 0x00200000; 392 } 393 394 nouveau_irq_register(dev, 12, nvc0_graph_isr); 395 nouveau_irq_register(dev, 25, nvc0_runk140_isr); 396 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ 397 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ 398 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ 399 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */ 400 return 0; 401 402error: 403 nvc0_graph_destroy(dev); 404 return ret; 405} 406 407static void 408nvc0_graph_init_obj418880(struct drm_device *dev) 409{ 410 struct drm_nouveau_private *dev_priv = dev->dev_private; 411 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 412 struct nvc0_graph_priv *priv = pgraph->priv; 413 int i; 414 415 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000); 416 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000); 417 for (i = 0; i < 4; i++) 418 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000); 419 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8); 420 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8); 421} 422 423static void 424nvc0_graph_init_regs(struct drm_device *dev) 425{ 426 nv_wr32(dev, 0x400080, 0x003083c2); 427 nv_wr32(dev, 0x400088, 0x00006fe7); 428 nv_wr32(dev, 0x40008c, 0x00000000); 429 nv_wr32(dev, 0x400090, 0x00000030); 430 nv_wr32(dev, 0x40013c, 0x013901f7); 431 nv_wr32(dev, 0x400140, 0x00000100); 432 nv_wr32(dev, 0x400144, 0x00000000); 433 nv_wr32(dev, 0x400148, 0x00000110); 434 nv_wr32(dev, 0x400138, 0x00000000); 435 nv_wr32(dev, 0x400130, 0x00000000); 436 nv_wr32(dev, 0x400134, 0x00000000); 437 nv_wr32(dev, 0x400124, 0x00000002); 438} 439 440static void 441nvc0_graph_init_gpc_0(struct drm_device *dev) 442{ 443 struct drm_nouveau_private *dev_priv = dev->dev_private; 444 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; 445 int gpc; 446 447 // TP ROP UNKVAL(magic_not_rop_nr) 448 // 450: 4/0/0/0 2 3 449 // 460: 3/4/0/0 4 1 450 // 465: 3/4/4/0 4 7 451 // 470: 3/3/4/4 5 5 452 // 480: 3/4/4/4 6 6 453 454 // magicgpc918 455 // 450: 00200000 00000000001000000000000000000000 456 // 460: 00124925 00000000000100100100100100100101 457 // 465: 000ba2e9 00000000000010111010001011101001 458 // 470: 00092493 00000000000010010010010010010011 459 // 480: 00088889 00000000000010001000100010001001 460 461 /* filled values up to tp_total, remainder 0 */ 462 // 450: 00003210 00000000 00000000 00000000 463 // 460: 02321100 00000000 00000000 00000000 464 // 465: 22111000 00000233 00000000 00000000 465 // 470: 11110000 00233222 00000000 00000000 466 // 480: 11110000 03332222 00000000 00000000 467 468 nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]); 469 nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]); 470 nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]); 471 nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]); 472 473 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 474 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | 475 priv->tp_nr[gpc]); 476 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total); 477 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918); 478 } 479 480 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918); 481 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr); 482} 483 484static void 485nvc0_graph_init_units(struct drm_device *dev) 486{ 487 nv_wr32(dev, 0x409c24, 0x000f0000); 488 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */ 489 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */ 490 nv_wr32(dev, 0x408030, 0xc0000000); 491 nv_wr32(dev, 0x40601c, 0xc0000000); 492 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */ 493 nv_wr32(dev, 0x406018, 0xc0000000); 494 nv_wr32(dev, 0x405840, 0xc0000000); 495 nv_wr32(dev, 0x405844, 0x00ffffff); 496 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008); 497 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000); 498} 499 500static void 501nvc0_graph_init_gpc_1(struct drm_device *dev) 502{ 503 struct drm_nouveau_private *dev_priv = dev->dev_private; 504 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; 505 int gpc, tp; 506 507 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 508 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000); 509 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000); 510 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000); 511 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000); 512 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { 513 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff); 514 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff); 515 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000); 516 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000); 517 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000); 518 nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe); 519 nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f); 520 } 521 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 522 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 523 } 524} 525 526static void 527nvc0_graph_init_rop(struct drm_device *dev) 528{ 529 struct drm_nouveau_private *dev_priv = dev->dev_private; 530 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; 531 int rop; 532 533 for (rop = 0; rop < priv->rop_nr; rop++) { 534 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000); 535 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000); 536 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff); 537 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff); 538 } 539} 540 541static int 542nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base, 543 const char *code_fw, const char *data_fw) 544{ 545 const struct firmware *fw; 546 char name[32]; 547 int ret, i; 548 549 snprintf(name, sizeof(name), "nouveau/%s", data_fw); 550 ret = request_firmware(&fw, name, &dev->pdev->dev); 551 if (ret) { 552 NV_ERROR(dev, "failed to load %s\n", data_fw); 553 return ret; 554 } 555 556 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000); 557 for (i = 0; i < fw->size / 4; i++) 558 nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]); 559 release_firmware(fw); 560 561 snprintf(name, sizeof(name), "nouveau/%s", code_fw); 562 ret = request_firmware(&fw, name, &dev->pdev->dev); 563 if (ret) { 564 NV_ERROR(dev, "failed to load %s\n", code_fw); 565 return ret; 566 } 567 568 nv_wr32(dev, fuc_base + 0x0180, 0x01000000); 569 for (i = 0; i < fw->size / 4; i++) { 570 if ((i & 0x3f) == 0) 571 nv_wr32(dev, fuc_base + 0x0188, i >> 6); 572 nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]); 573 } 574 release_firmware(fw); 575 576 return 0; 577} 578 579static int 580nvc0_graph_init_ctxctl(struct drm_device *dev) 581{ 582 struct drm_nouveau_private *dev_priv = dev->dev_private; 583 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; 584 u32 r000260; 585 int ret; 586 587 /* load fuc microcode */ 588 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); 589 ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d"); 590 if (ret == 0) 591 ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad"); 592 nv_wr32(dev, 0x000260, r000260); 593 594 if (ret) 595 return ret; 596 597 /* start both of them running */ 598 nv_wr32(dev, 0x409840, 0xffffffff); 599 nv_wr32(dev, 0x41a10c, 0x00000000); 600 nv_wr32(dev, 0x40910c, 0x00000000); 601 nv_wr32(dev, 0x41a100, 0x00000002); 602 nv_wr32(dev, 0x409100, 0x00000002); 603 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001)) 604 NV_INFO(dev, "0x409800 wait failed\n"); 605 606 nv_wr32(dev, 0x409840, 0xffffffff); 607 nv_wr32(dev, 0x409500, 0x7fffffff); 608 nv_wr32(dev, 0x409504, 0x00000021); 609 610 nv_wr32(dev, 0x409840, 0xffffffff); 611 nv_wr32(dev, 0x409500, 0x00000000); 612 nv_wr32(dev, 0x409504, 0x00000010); 613 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { 614 NV_ERROR(dev, "fuc09 req 0x10 timeout\n"); 615 return -EBUSY; 616 } 617 priv->grctx_size = nv_rd32(dev, 0x409800); 618 619 nv_wr32(dev, 0x409840, 0xffffffff); 620 nv_wr32(dev, 0x409500, 0x00000000); 621 nv_wr32(dev, 0x409504, 0x00000016); 622 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { 623 NV_ERROR(dev, "fuc09 req 0x16 timeout\n"); 624 return -EBUSY; 625 } 626 627 nv_wr32(dev, 0x409840, 0xffffffff); 628 nv_wr32(dev, 0x409500, 0x00000000); 629 nv_wr32(dev, 0x409504, 0x00000025); 630 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { 631 NV_ERROR(dev, "fuc09 req 0x25 timeout\n"); 632 return -EBUSY; 633 } 634 635 return 0; 636} 637 638int 639nvc0_graph_init(struct drm_device *dev) 640{ 641 struct drm_nouveau_private *dev_priv = dev->dev_private; 642 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 643 int ret; 644 645 dev_priv->engine.graph.accel_blocked = true; 646 647 switch (dev_priv->chipset) { 648 case 0xc0: 649 case 0xc3: 650 case 0xc4: 651 break; 652 default: 653 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); 654 if (nouveau_noaccel != 0) 655 return 0; 656 break; 657 } 658 659 nv_mask(dev, 0x000200, 0x18001000, 0x00000000); 660 nv_mask(dev, 0x000200, 0x18001000, 0x18001000); 661 662 if (!pgraph->priv) { 663 ret = nvc0_graph_create(dev); 664 if (ret) 665 return ret; 666 } 667 668 nvc0_graph_init_obj418880(dev); 669 nvc0_graph_init_regs(dev); 670 //nvc0_graph_init_unitplemented_magics(dev); 671 nvc0_graph_init_gpc_0(dev); 672 //nvc0_graph_init_unitplemented_c242(dev); 673 674 nv_wr32(dev, 0x400500, 0x00010001); 675 nv_wr32(dev, 0x400100, 0xffffffff); 676 nv_wr32(dev, 0x40013c, 0xffffffff); 677 678 nvc0_graph_init_units(dev); 679 nvc0_graph_init_gpc_1(dev); 680 nvc0_graph_init_rop(dev); 681 682 nv_wr32(dev, 0x400108, 0xffffffff); 683 nv_wr32(dev, 0x400138, 0xffffffff); 684 nv_wr32(dev, 0x400118, 0xffffffff); 685 nv_wr32(dev, 0x400130, 0xffffffff); 686 nv_wr32(dev, 0x40011c, 0xffffffff); 687 nv_wr32(dev, 0x400134, 0xffffffff); 688 nv_wr32(dev, 0x400054, 0x34ce3464); 689 690 ret = nvc0_graph_init_ctxctl(dev); 691 if (ret == 0) 692 dev_priv->engine.graph.accel_blocked = false; 693 return 0; 694} 695 696static int 697nvc0_graph_isr_chid(struct drm_device *dev, u64 inst) 698{ 699 struct drm_nouveau_private *dev_priv = dev->dev_private; 700 struct nouveau_channel *chan; 701 unsigned long flags; 702 int i; 703 704 spin_lock_irqsave(&dev_priv->channels.lock, flags); 705 for (i = 0; i < dev_priv->engine.fifo.channels; i++) { 706 chan = dev_priv->channels.ptr[i]; 707 if (!chan || !chan->ramin) 708 continue; 709 710 if (inst == chan->ramin->vinst) 711 break; 712 } 713 spin_unlock_irqrestore(&dev_priv->channels.lock, flags); 714 return i; 715} 716 717static void 718nvc0_graph_isr(struct drm_device *dev) 719{ 720 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; 721 u32 chid = nvc0_graph_isr_chid(dev, inst); 722 u32 stat = nv_rd32(dev, 0x400100); 723 u32 addr = nv_rd32(dev, 0x400704); 724 u32 mthd = (addr & 0x00003ffc); 725 u32 subc = (addr & 0x00070000) >> 16; 726 u32 data = nv_rd32(dev, 0x400708); 727 u32 code = nv_rd32(dev, 0x400110); 728 u32 class = nv_rd32(dev, 0x404200 + (subc * 4)); 729 730 if (stat & 0x00000010) { 731 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] subc %d " 732 "class 0x%04x mthd 0x%04x data 0x%08x\n", 733 chid, inst, subc, class, mthd, data); 734 nv_wr32(dev, 0x400100, 0x00000010); 735 stat &= ~0x00000010; 736 } 737 738 if (stat & 0x00000020) { 739 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d " 740 "class 0x%04x mthd 0x%04x data 0x%08x\n", 741 chid, inst, subc, class, mthd, data); 742 nv_wr32(dev, 0x400100, 0x00000020); 743 stat &= ~0x00000020; 744 } 745 746 if (stat & 0x00100000) { 747 NV_INFO(dev, "PGRAPH: DATA_ERROR ["); 748 nouveau_enum_print(nv50_data_error_names, code); 749 printk("] ch %d [0x%010llx] subc %d class 0x%04x " 750 "mthd 0x%04x data 0x%08x\n", 751 chid, inst, subc, class, mthd, data); 752 nv_wr32(dev, 0x400100, 0x00100000); 753 stat &= ~0x00100000; 754 } 755 756 if (stat & 0x00200000) { 757 u32 trap = nv_rd32(dev, 0x400108); 758 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap); 759 nv_wr32(dev, 0x400108, trap); 760 nv_wr32(dev, 0x400100, 0x00200000); 761 stat &= ~0x00200000; 762 } 763 764 if (stat & 0x00080000) { 765 u32 ustat = nv_rd32(dev, 0x409c18); 766 767 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat); 768 769 nv_wr32(dev, 0x409c20, ustat); 770 nv_wr32(dev, 0x400100, 0x00080000); 771 stat &= ~0x00080000; 772 } 773 774 if (stat) { 775 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat); 776 nv_wr32(dev, 0x400100, stat); 777 } 778 779 nv_wr32(dev, 0x400500, 0x00010001); 780} 781 782static void 783nvc0_runk140_isr(struct drm_device *dev) 784{ 785 u32 units = nv_rd32(dev, 0x00017c) & 0x1f; 786 787 while (units) { 788 u32 unit = ffs(units) - 1; 789 u32 reg = 0x140000 + unit * 0x2000; 790 u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0); 791 u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0); 792 793 NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1); 794 units &= ~(1 << unit); 795 } 796} 797