1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/seq_file.h> 29#include <linux/slab.h> 30#include <drm/drmP.h> 31#include "radeon.h" 32#include "radeon_asic.h" 33#include "rs400d.h" 34 35/* This files gather functions specifics to : rs400,rs480 */ 36static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 37 38void rs400_gart_adjust_size(struct radeon_device *rdev) 39{ 40 /* Check gart size */ 41 switch (rdev->mc.gtt_size/(1024*1024)) { 42 case 32: 43 case 64: 44 case 128: 45 case 256: 46 case 512: 47 case 1024: 48 case 2048: 49 break; 50 default: 51 DRM_ERROR("Unable to use IGP GART size %uM\n", 52 (unsigned)(rdev->mc.gtt_size >> 20)); 53 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 54 DRM_ERROR("Forcing to 32M GART size\n"); 55 rdev->mc.gtt_size = 32 * 1024 * 1024; 56 return; 57 } 58} 59 60void rs400_gart_tlb_flush(struct radeon_device *rdev) 61{ 62 uint32_t tmp; 63 unsigned int timeout = rdev->usec_timeout; 64 65 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 66 do { 67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 69 break; 70 DRM_UDELAY(1); 71 timeout--; 72 } while (timeout > 0); 73 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 74} 75 76int rs400_gart_init(struct radeon_device *rdev) 77{ 78 int r; 79 80 if (rdev->gart.ptr) { 81 WARN(1, "RS400 GART already initialized\n"); 82 return 0; 83 } 84 /* Check gart size */ 85 switch(rdev->mc.gtt_size / (1024 * 1024)) { 86 case 32: 87 case 64: 88 case 128: 89 case 256: 90 case 512: 91 case 1024: 92 case 2048: 93 break; 94 default: 95 return -EINVAL; 96 } 97 /* Initialize common gart structure */ 98 r = radeon_gart_init(rdev); 99 if (r) 100 return r; 101 if (rs400_debugfs_pcie_gart_info_init(rdev)) 102 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 104 return radeon_gart_table_ram_alloc(rdev); 105} 106 107int rs400_gart_enable(struct radeon_device *rdev) 108{ 109 uint32_t size_reg; 110 uint32_t tmp; 111 112 radeon_gart_restore(rdev); 113 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 114 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 115 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 116 /* Check gart size */ 117 switch(rdev->mc.gtt_size / (1024 * 1024)) { 118 case 32: 119 size_reg = RS480_VA_SIZE_32MB; 120 break; 121 case 64: 122 size_reg = RS480_VA_SIZE_64MB; 123 break; 124 case 128: 125 size_reg = RS480_VA_SIZE_128MB; 126 break; 127 case 256: 128 size_reg = RS480_VA_SIZE_256MB; 129 break; 130 case 512: 131 size_reg = RS480_VA_SIZE_512MB; 132 break; 133 case 1024: 134 size_reg = RS480_VA_SIZE_1GB; 135 break; 136 case 2048: 137 size_reg = RS480_VA_SIZE_2GB; 138 break; 139 default: 140 return -EINVAL; 141 } 142 /* It should be fine to program it to max value */ 143 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 144 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 145 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 146 } else { 147 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 148 WREG32(RS480_AGP_BASE_2, 0); 149 } 150 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 151 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 152 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 153 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 154 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 155 WREG32(RADEON_BUS_CNTL, tmp); 156 } else { 157 WREG32(RADEON_MC_AGP_LOCATION, tmp); 158 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 159 WREG32(RADEON_BUS_CNTL, tmp); 160 } 161 /* Table should be in 32bits address space so ignore bits above. */ 162 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 163 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 164 165 WREG32_MC(RS480_GART_BASE, tmp); 166 /* TODO: more tweaking here */ 167 WREG32_MC(RS480_GART_FEATURE_ID, 168 (RS480_TLB_ENABLE | 169 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 170 /* Disable snooping */ 171 WREG32_MC(RS480_AGP_MODE_CNTL, 172 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 173 /* Disable AGP mode */ 174 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 175 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 176 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 177 WREG32_MC(RS480_MC_MISC_CNTL, 178 (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); 179 } else { 180 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 181 } 182 /* Enable gart */ 183 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 184 rs400_gart_tlb_flush(rdev); 185 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 186 (unsigned)(rdev->mc.gtt_size >> 20), 187 (unsigned long long)rdev->gart.table_addr); 188 rdev->gart.ready = true; 189 return 0; 190} 191 192void rs400_gart_disable(struct radeon_device *rdev) 193{ 194 uint32_t tmp; 195 196 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 197 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 198 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 199 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 200} 201 202void rs400_gart_fini(struct radeon_device *rdev) 203{ 204 radeon_gart_fini(rdev); 205 rs400_gart_disable(rdev); 206 radeon_gart_table_ram_free(rdev); 207} 208 209#define RS400_PTE_WRITEABLE (1 << 2) 210#define RS400_PTE_READABLE (1 << 3) 211 212int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 213{ 214 uint32_t entry; 215 u32 *gtt = rdev->gart.ptr; 216 217 if (i < 0 || i > rdev->gart.num_gpu_pages) { 218 return -EINVAL; 219 } 220 221 entry = (lower_32_bits(addr) & PAGE_MASK) | 222 ((upper_32_bits(addr) & 0xff) << 4) | 223 RS400_PTE_WRITEABLE | RS400_PTE_READABLE; 224 entry = cpu_to_le32(entry); 225 gtt[i] = entry; 226 return 0; 227} 228 229int rs400_mc_wait_for_idle(struct radeon_device *rdev) 230{ 231 unsigned i; 232 uint32_t tmp; 233 234 for (i = 0; i < rdev->usec_timeout; i++) { 235 /* read MC_STATUS */ 236 tmp = RREG32(RADEON_MC_STATUS); 237 if (tmp & RADEON_MC_IDLE) { 238 return 0; 239 } 240 DRM_UDELAY(1); 241 } 242 return -1; 243} 244 245void rs400_gpu_init(struct radeon_device *rdev) 246{ 247 /* FIXME: is this correct ? */ 248 r420_pipes_init(rdev); 249 if (rs400_mc_wait_for_idle(rdev)) { 250 printk(KERN_WARNING "rs400: Failed to wait MC idle while " 251 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 252 } 253} 254 255void rs400_mc_init(struct radeon_device *rdev) 256{ 257 u64 base; 258 259 rs400_gart_adjust_size(rdev); 260 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 261 /* DDR for all card after R300 & IGP */ 262 rdev->mc.vram_is_ddr = true; 263 rdev->mc.vram_width = 128; 264 r100_vram_init_sizes(rdev); 265 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 266 radeon_vram_location(rdev, &rdev->mc, base); 267 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 268 radeon_gtt_location(rdev, &rdev->mc); 269 radeon_update_bandwidth_info(rdev); 270} 271 272uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 273{ 274 uint32_t r; 275 276 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 277 r = RREG32(RS480_NB_MC_DATA); 278 WREG32(RS480_NB_MC_INDEX, 0xff); 279 return r; 280} 281 282void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 283{ 284 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 285 WREG32(RS480_NB_MC_DATA, (v)); 286 WREG32(RS480_NB_MC_INDEX, 0xff); 287} 288 289#if defined(CONFIG_DEBUG_FS) 290static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 291{ 292 struct drm_info_node *node = (struct drm_info_node *) m->private; 293 struct drm_device *dev = node->minor->dev; 294 struct radeon_device *rdev = dev->dev_private; 295 uint32_t tmp; 296 297 tmp = RREG32(RADEON_HOST_PATH_CNTL); 298 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 299 tmp = RREG32(RADEON_BUS_CNTL); 300 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 301 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 302 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 303 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 304 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 305 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 306 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 307 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 308 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 309 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 310 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 311 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 312 tmp = RREG32(RS690_HDP_FB_LOCATION); 313 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 314 } else { 315 tmp = RREG32(RADEON_AGP_BASE); 316 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 317 tmp = RREG32(RS480_AGP_BASE_2); 318 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 319 tmp = RREG32(RADEON_MC_AGP_LOCATION); 320 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 321 } 322 tmp = RREG32_MC(RS480_GART_BASE); 323 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 324 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 325 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 326 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 327 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 328 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 329 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 330 tmp = RREG32_MC(0x5F); 331 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 332 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 333 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 334 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 335 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 336 tmp = RREG32_MC(0x3B); 337 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 338 tmp = RREG32_MC(0x3C); 339 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 340 tmp = RREG32_MC(0x30); 341 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 342 tmp = RREG32_MC(0x31); 343 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 344 tmp = RREG32_MC(0x32); 345 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 346 tmp = RREG32_MC(0x33); 347 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 348 tmp = RREG32_MC(0x34); 349 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 350 tmp = RREG32_MC(0x35); 351 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 352 tmp = RREG32_MC(0x36); 353 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 354 tmp = RREG32_MC(0x37); 355 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 356 return 0; 357} 358 359static struct drm_info_list rs400_gart_info_list[] = { 360 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 361}; 362#endif 363 364static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 365{ 366#if defined(CONFIG_DEBUG_FS) 367 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 368#else 369 return 0; 370#endif 371} 372 373void rs400_mc_program(struct radeon_device *rdev) 374{ 375 struct r100_mc_save save; 376 377 /* Stops all mc clients */ 378 r100_mc_stop(rdev, &save); 379 380 /* Wait for mc idle */ 381 if (rs400_mc_wait_for_idle(rdev)) 382 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 383 WREG32(R_000148_MC_FB_LOCATION, 384 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 385 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 386 387 r100_mc_resume(rdev, &save); 388} 389 390static int rs400_startup(struct radeon_device *rdev) 391{ 392 int r; 393 394 r100_set_common_regs(rdev); 395 396 rs400_mc_program(rdev); 397 /* Resume clock */ 398 r300_clock_startup(rdev); 399 /* Initialize GPU configuration (# pipes, ...) */ 400 rs400_gpu_init(rdev); 401 r100_enable_bm(rdev); 402 /* Initialize GART (initialize after TTM so we can allocate 403 * memory through TTM but finalize after TTM) */ 404 r = rs400_gart_enable(rdev); 405 if (r) 406 return r; 407 408 /* allocate wb buffer */ 409 r = radeon_wb_init(rdev); 410 if (r) 411 return r; 412 413 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 414 if (r) { 415 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 416 return r; 417 } 418 419 /* Enable IRQ */ 420 r100_irq_set(rdev); 421 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 422 /* 1M ring buffer */ 423 r = r100_cp_init(rdev, 1024 * 1024); 424 if (r) { 425 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 426 return r; 427 } 428 429 r = radeon_ib_pool_start(rdev); 430 if (r) 431 return r; 432 433 r = r100_ib_test(rdev); 434 if (r) { 435 dev_err(rdev->dev, "failed testing IB (%d).\n", r); 436 rdev->accel_working = false; 437 return r; 438 } 439 440 return 0; 441} 442 443int rs400_resume(struct radeon_device *rdev) 444{ 445 int r; 446 447 /* Make sur GART are not working */ 448 rs400_gart_disable(rdev); 449 /* Resume clock before doing reset */ 450 r300_clock_startup(rdev); 451 /* setup MC before calling post tables */ 452 rs400_mc_program(rdev); 453 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 454 if (radeon_asic_reset(rdev)) { 455 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 456 RREG32(R_000E40_RBBM_STATUS), 457 RREG32(R_0007C0_CP_STAT)); 458 } 459 /* post */ 460 radeon_combios_asic_init(rdev->ddev); 461 /* Resume clock after posting */ 462 r300_clock_startup(rdev); 463 /* Initialize surface registers */ 464 radeon_surface_init(rdev); 465 466 rdev->accel_working = true; 467 r = rs400_startup(rdev); 468 if (r) { 469 rdev->accel_working = false; 470 } 471 return r; 472} 473 474int rs400_suspend(struct radeon_device *rdev) 475{ 476 radeon_ib_pool_suspend(rdev); 477 r100_cp_disable(rdev); 478 radeon_wb_disable(rdev); 479 r100_irq_disable(rdev); 480 rs400_gart_disable(rdev); 481 return 0; 482} 483 484void rs400_fini(struct radeon_device *rdev) 485{ 486 r100_cp_fini(rdev); 487 radeon_wb_fini(rdev); 488 r100_ib_fini(rdev); 489 radeon_gem_fini(rdev); 490 rs400_gart_fini(rdev); 491 radeon_irq_kms_fini(rdev); 492 radeon_fence_driver_fini(rdev); 493 radeon_bo_fini(rdev); 494 radeon_atombios_fini(rdev); 495 kfree(rdev->bios); 496 rdev->bios = NULL; 497} 498 499int rs400_init(struct radeon_device *rdev) 500{ 501 int r; 502 503 /* Disable VGA */ 504 r100_vga_render_disable(rdev); 505 /* Initialize scratch registers */ 506 radeon_scratch_init(rdev); 507 /* Initialize surface registers */ 508 radeon_surface_init(rdev); 509 /* TODO: disable VGA need to use VGA request */ 510 /* restore some register to sane defaults */ 511 r100_restore_sanity(rdev); 512 /* BIOS*/ 513 if (!radeon_get_bios(rdev)) { 514 if (ASIC_IS_AVIVO(rdev)) 515 return -EINVAL; 516 } 517 if (rdev->is_atom_bios) { 518 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 519 return -EINVAL; 520 } else { 521 r = radeon_combios_init(rdev); 522 if (r) 523 return r; 524 } 525 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 526 if (radeon_asic_reset(rdev)) { 527 dev_warn(rdev->dev, 528 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 529 RREG32(R_000E40_RBBM_STATUS), 530 RREG32(R_0007C0_CP_STAT)); 531 } 532 /* check if cards are posted or not */ 533 if (radeon_boot_test_post_card(rdev) == false) 534 return -EINVAL; 535 536 /* Initialize clocks */ 537 radeon_get_clock_info(rdev->ddev); 538 /* initialize memory controller */ 539 rs400_mc_init(rdev); 540 /* Fence driver */ 541 r = radeon_fence_driver_init(rdev); 542 if (r) 543 return r; 544 r = radeon_irq_kms_init(rdev); 545 if (r) 546 return r; 547 /* Memory manager */ 548 r = radeon_bo_init(rdev); 549 if (r) 550 return r; 551 r = rs400_gart_init(rdev); 552 if (r) 553 return r; 554 r300_set_reg_safe(rdev); 555 556 r = radeon_ib_pool_init(rdev); 557 rdev->accel_working = true; 558 if (r) { 559 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 560 rdev->accel_working = false; 561 } 562 563 r = rs400_startup(rdev); 564 if (r) { 565 /* Somethings want wront with the accel init stop accel */ 566 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 567 r100_cp_fini(rdev); 568 radeon_wb_fini(rdev); 569 r100_ib_fini(rdev); 570 rs400_gart_fini(rdev); 571 radeon_irq_kms_fini(rdev); 572 rdev->accel_working = false; 573 } 574 return 0; 575} 576