1/* 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027, 3 * and SCH5127 Super-I/O chips integrated hardware monitoring 4 * features. 5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com> 6 * 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very 10 * similar hardware monitoring capabilities but differ in the way they can be 11 * accessed. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30#include <linux/module.h> 31#include <linux/init.h> 32#include <linux/slab.h> 33#include <linux/jiffies.h> 34#include <linux/i2c.h> 35#include <linux/platform_device.h> 36#include <linux/hwmon.h> 37#include <linux/hwmon-sysfs.h> 38#include <linux/hwmon-vid.h> 39#include <linux/err.h> 40#include <linux/mutex.h> 41#include <linux/acpi.h> 42#include <linux/io.h> 43 44/* ISA device, if found */ 45static struct platform_device *pdev; 46 47/* Module load parameters */ 48static bool force_start; 49module_param(force_start, bool, 0); 50MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs"); 51 52static unsigned short force_id; 53module_param(force_id, ushort, 0); 54MODULE_PARM_DESC(force_id, "Override the detected device ID"); 55 56static bool probe_all_addr; 57module_param(probe_all_addr, bool, 0); 58MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC " 59 "addresses"); 60 61/* Addresses to scan */ 62static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; 63 64enum chips { dme1737, sch5027, sch311x, sch5127 }; 65 66/* --------------------------------------------------------------------- 67 * Registers 68 * 69 * The sensors are defined as follows: 70 * 71 * Voltages Temperatures 72 * -------- ------------ 73 * in0 +5VTR (+5V stdby) temp1 Remote diode 1 74 * in1 Vccp (proc core) temp2 Internal temp 75 * in2 VCC (internal +3.3V) temp3 Remote diode 2 76 * in3 +5V 77 * in4 +12V 78 * in5 VTR (+3.3V stby) 79 * in6 Vbat 80 * in7 Vtrip (sch5127 only) 81 * 82 * --------------------------------------------------------------------- */ 83 84/* Voltages (in) numbered 0-7 (ix) */ 85#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ 86 (ix) < 7 ? 0x94 + (ix) : \ 87 0x1f) 88#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ 89 : 0x91 + (ix) * 2) 90#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ 91 : 0x92 + (ix) * 2) 92 93/* Temperatures (temp) numbered 0-2 (ix) */ 94#define DME1737_REG_TEMP(ix) (0x25 + (ix)) 95#define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) 96#define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) 97#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ 98 : 0x1c + (ix)) 99 100/* Voltage and temperature LSBs 101 * The LSBs (4 bits each) are stored in 5 registers with the following layouts: 102 * IN_TEMP_LSB(0) = [in5, in6] 103 * IN_TEMP_LSB(1) = [temp3, temp1] 104 * IN_TEMP_LSB(2) = [in4, temp2] 105 * IN_TEMP_LSB(3) = [in3, in0] 106 * IN_TEMP_LSB(4) = [in2, in1] 107 * IN_TEMP_LSB(5) = [res, in7] */ 108#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix)) 109static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5}; 110static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4}; 111static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1}; 112static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0}; 113 114/* Fans numbered 0-5 (ix) */ 115#define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \ 116 : 0xa1 + (ix) * 2) 117#define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \ 118 : 0xa5 + (ix) * 2) 119#define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \ 120 : 0xb2 + (ix)) 121#define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */ 122 123/* PWMs numbered 0-2, 4-5 (ix) */ 124#define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \ 125 : 0xa1 + (ix)) 126#define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */ 127#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */ 128#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \ 129 : 0xa3 + (ix)) 130/* The layout of the ramp rate registers is different from the other pwm 131 * registers. The bits for the 3 PWMs are stored in 2 registers: 132 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0] 133 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */ 134#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */ 135 136/* Thermal zones 0-2 */ 137#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix)) 138#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix)) 139/* The layout of the hysteresis registers is different from the other zone 140 * registers. The bits for the 3 zones are stored in 2 registers: 141 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 142 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */ 143#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix)) 144 145/* Alarm registers and bit mapping 146 * The 3 8-bit alarm registers will be concatenated to a single 32-bit 147 * alarm value [0, ALARM3, ALARM2, ALARM1]. */ 148#define DME1737_REG_ALARM1 0x41 149#define DME1737_REG_ALARM2 0x42 150#define DME1737_REG_ALARM3 0x83 151static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18}; 152static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6}; 153static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; 154 155/* Miscellaneous registers */ 156#define DME1737_REG_DEVICE 0x3d 157#define DME1737_REG_COMPANY 0x3e 158#define DME1737_REG_VERSTEP 0x3f 159#define DME1737_REG_CONFIG 0x40 160#define DME1737_REG_CONFIG2 0x7f 161#define DME1737_REG_VID 0x43 162#define DME1737_REG_TACH_PWM 0x81 163 164/* --------------------------------------------------------------------- 165 * Misc defines 166 * --------------------------------------------------------------------- */ 167 168/* Chip identification */ 169#define DME1737_COMPANY_SMSC 0x5c 170#define DME1737_VERSTEP 0x88 171#define DME1737_VERSTEP_MASK 0xf8 172#define SCH311X_DEVICE 0x8c 173#define SCH5027_VERSTEP 0x69 174#define SCH5127_DEVICE 0x8e 175 176/* Device ID values (global configuration register index 0x20) */ 177#define DME1737_ID_1 0x77 178#define DME1737_ID_2 0x78 179#define SCH3112_ID 0x7c 180#define SCH3114_ID 0x7d 181#define SCH3116_ID 0x7f 182#define SCH5027_ID 0x89 183#define SCH5127_ID 0x86 184 185/* Length of ISA address segment */ 186#define DME1737_EXTENT 2 187 188/* chip-dependent features */ 189#define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */ 190#define HAS_VID (1 << 1) /* bit 1 */ 191#define HAS_ZONE3 (1 << 2) /* bit 2 */ 192#define HAS_ZONE_HYST (1 << 3) /* bit 3 */ 193#define HAS_PWM_MIN (1 << 4) /* bit 4 */ 194#define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */ 195#define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */ 196#define HAS_IN7 (1 << 17) /* bit 17 */ 197 198/* --------------------------------------------------------------------- 199 * Data structures and manipulation thereof 200 * --------------------------------------------------------------------- */ 201 202struct dme1737_data { 203 struct i2c_client *client; /* for I2C devices only */ 204 struct device *hwmon_dev; 205 const char *name; 206 unsigned int addr; /* for ISA devices only */ 207 208 struct mutex update_lock; 209 int valid; /* !=0 if following fields are valid */ 210 unsigned long last_update; /* in jiffies */ 211 unsigned long last_vbat; /* in jiffies */ 212 enum chips type; 213 const int *in_nominal; /* pointer to IN_NOMINAL array */ 214 215 u8 vid; 216 u8 pwm_rr_en; 217 u32 has_features; 218 219 /* Register values */ 220 u16 in[8]; 221 u8 in_min[8]; 222 u8 in_max[8]; 223 s16 temp[3]; 224 s8 temp_min[3]; 225 s8 temp_max[3]; 226 s8 temp_offset[3]; 227 u8 config; 228 u8 config2; 229 u8 vrm; 230 u16 fan[6]; 231 u16 fan_min[6]; 232 u8 fan_max[2]; 233 u8 fan_opt[6]; 234 u8 pwm[6]; 235 u8 pwm_min[3]; 236 u8 pwm_config[3]; 237 u8 pwm_acz[3]; 238 u8 pwm_freq[6]; 239 u8 pwm_rr[2]; 240 u8 zone_low[3]; 241 u8 zone_abs[3]; 242 u8 zone_hyst[2]; 243 u32 alarms; 244}; 245 246/* Nominal voltage values */ 247static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, 248 3300}; 249static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, 250 3300}; 251static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, 252 3300}; 253static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300, 254 3300, 1500}; 255#define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ 256 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ 257 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \ 258 IN_NOMINAL_DME1737) 259 260/* Voltage input 261 * Voltage inputs have 16 bits resolution, limit values have 8 bits 262 * resolution. */ 263static inline int IN_FROM_REG(int reg, int nominal, int res) 264{ 265 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); 266} 267 268static inline int IN_TO_REG(int val, int nominal) 269{ 270 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); 271} 272 273/* Temperature input 274 * The register values represent temperatures in 2's complement notation from 275 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit 276 * values have 8 bits resolution. */ 277static inline int TEMP_FROM_REG(int reg, int res) 278{ 279 return (reg * 1000) >> (res - 8); 280} 281 282static inline int TEMP_TO_REG(int val) 283{ 284 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000, 285 -128, 127); 286} 287 288/* Temperature range */ 289static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000, 290 10000, 13333, 16000, 20000, 26666, 32000, 291 40000, 53333, 80000}; 292 293static inline int TEMP_RANGE_FROM_REG(int reg) 294{ 295 return TEMP_RANGE[(reg >> 4) & 0x0f]; 296} 297 298static int TEMP_RANGE_TO_REG(int val, int reg) 299{ 300 int i; 301 302 for (i = 15; i > 0; i--) { 303 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) { 304 break; 305 } 306 } 307 308 return (reg & 0x0f) | (i << 4); 309} 310 311/* Temperature hysteresis 312 * Register layout: 313 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 314 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */ 315static inline int TEMP_HYST_FROM_REG(int reg, int ix) 316{ 317 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; 318} 319 320static inline int TEMP_HYST_TO_REG(int val, int ix, int reg) 321{ 322 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15); 323 324 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4); 325} 326 327/* Fan input RPM */ 328static inline int FAN_FROM_REG(int reg, int tpc) 329{ 330 if (tpc) { 331 return tpc * reg; 332 } else { 333 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; 334 } 335} 336 337static inline int FAN_TO_REG(int val, int tpc) 338{ 339 if (tpc) { 340 return SENSORS_LIMIT(val / tpc, 0, 0xffff); 341 } else { 342 return (val <= 0) ? 0xffff : 343 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe); 344 } 345} 346 347/* Fan TPC (tach pulse count) 348 * Converts a register value to a TPC multiplier or returns 0 if the tachometer 349 * is configured in legacy (non-tpc) mode */ 350static inline int FAN_TPC_FROM_REG(int reg) 351{ 352 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); 353} 354 355/* Fan type 356 * The type of a fan is expressed in number of pulses-per-revolution that it 357 * emits */ 358static inline int FAN_TYPE_FROM_REG(int reg) 359{ 360 int edge = (reg >> 1) & 0x03; 361 362 return (edge > 0) ? 1 << (edge - 1) : 0; 363} 364 365static inline int FAN_TYPE_TO_REG(int val, int reg) 366{ 367 int edge = (val == 4) ? 3 : val; 368 369 return (reg & 0xf9) | (edge << 1); 370} 371 372/* Fan max RPM */ 373static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12, 374 0x11, 0x0f, 0x0e}; 375 376static int FAN_MAX_FROM_REG(int reg) 377{ 378 int i; 379 380 for (i = 10; i > 0; i--) { 381 if (reg == FAN_MAX[i]) { 382 break; 383 } 384 } 385 386 return 1000 + i * 500; 387} 388 389static int FAN_MAX_TO_REG(int val) 390{ 391 int i; 392 393 for (i = 10; i > 0; i--) { 394 if (val > (1000 + (i - 1) * 500)) { 395 break; 396 } 397 } 398 399 return FAN_MAX[i]; 400} 401 402/* PWM enable 403 * Register to enable mapping: 404 * 000: 2 fan on zone 1 auto 405 * 001: 2 fan on zone 2 auto 406 * 010: 2 fan on zone 3 auto 407 * 011: 0 fan full on 408 * 100: -1 fan disabled 409 * 101: 2 fan on hottest of zones 2,3 auto 410 * 110: 2 fan on hottest of zones 1,2,3 auto 411 * 111: 1 fan in manual mode */ 412static inline int PWM_EN_FROM_REG(int reg) 413{ 414 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1}; 415 416 return en[(reg >> 5) & 0x07]; 417} 418 419static inline int PWM_EN_TO_REG(int val, int reg) 420{ 421 int en = (val == 1) ? 7 : 3; 422 423 return (reg & 0x1f) | ((en & 0x07) << 5); 424} 425 426/* PWM auto channels zone 427 * Register to auto channels zone mapping (ACZ is a bitfield with bit x 428 * corresponding to zone x+1): 429 * 000: 001 fan on zone 1 auto 430 * 001: 010 fan on zone 2 auto 431 * 010: 100 fan on zone 3 auto 432 * 011: 000 fan full on 433 * 100: 000 fan disabled 434 * 101: 110 fan on hottest of zones 2,3 auto 435 * 110: 111 fan on hottest of zones 1,2,3 auto 436 * 111: 000 fan in manual mode */ 437static inline int PWM_ACZ_FROM_REG(int reg) 438{ 439 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0}; 440 441 return acz[(reg >> 5) & 0x07]; 442} 443 444static inline int PWM_ACZ_TO_REG(int val, int reg) 445{ 446 int acz = (val == 4) ? 2 : val - 1; 447 448 return (reg & 0x1f) | ((acz & 0x07) << 5); 449} 450 451/* PWM frequency */ 452static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88, 453 15000, 20000, 30000, 25000, 0, 0, 0, 0}; 454 455static inline int PWM_FREQ_FROM_REG(int reg) 456{ 457 return PWM_FREQ[reg & 0x0f]; 458} 459 460static int PWM_FREQ_TO_REG(int val, int reg) 461{ 462 int i; 463 464 /* the first two cases are special - stupid chip design! */ 465 if (val > 27500) { 466 i = 10; 467 } else if (val > 22500) { 468 i = 11; 469 } else { 470 for (i = 9; i > 0; i--) { 471 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) { 472 break; 473 } 474 } 475 } 476 477 return (reg & 0xf0) | i; 478} 479 480/* PWM ramp rate 481 * Register layout: 482 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0] 483 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */ 484static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5}; 485 486static inline int PWM_RR_FROM_REG(int reg, int ix) 487{ 488 int rr = (ix == 1) ? reg >> 4 : reg; 489 490 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0; 491} 492 493static int PWM_RR_TO_REG(int val, int ix, int reg) 494{ 495 int i; 496 497 for (i = 0; i < 7; i++) { 498 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) { 499 break; 500 } 501 } 502 503 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; 504} 505 506/* PWM ramp rate enable */ 507static inline int PWM_RR_EN_FROM_REG(int reg, int ix) 508{ 509 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0; 510} 511 512static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg) 513{ 514 int en = (ix == 1) ? 0x80 : 0x08; 515 516 return val ? reg | en : reg & ~en; 517} 518 519/* PWM min/off 520 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for 521 * the register layout). */ 522static inline int PWM_OFF_FROM_REG(int reg, int ix) 523{ 524 return (reg >> (ix + 5)) & 0x01; 525} 526 527static inline int PWM_OFF_TO_REG(int val, int ix, int reg) 528{ 529 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); 530} 531 532/* --------------------------------------------------------------------- 533 * Device I/O access 534 * 535 * ISA access is performed through an index/data register pair and needs to 536 * be protected by a mutex during runtime (not required for initialization). 537 * We use data->update_lock for this and need to ensure that we acquire it 538 * before calling dme1737_read or dme1737_write. 539 * --------------------------------------------------------------------- */ 540 541static u8 dme1737_read(const struct dme1737_data *data, u8 reg) 542{ 543 struct i2c_client *client = data->client; 544 s32 val; 545 546 if (client) { /* I2C device */ 547 val = i2c_smbus_read_byte_data(client, reg); 548 549 if (val < 0) { 550 dev_warn(&client->dev, "Read from register " 551 "0x%02x failed! Please report to the driver " 552 "maintainer.\n", reg); 553 } 554 } else { /* ISA device */ 555 outb(reg, data->addr); 556 val = inb(data->addr + 1); 557 } 558 559 return val; 560} 561 562static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val) 563{ 564 struct i2c_client *client = data->client; 565 s32 res = 0; 566 567 if (client) { /* I2C device */ 568 res = i2c_smbus_write_byte_data(client, reg, val); 569 570 if (res < 0) { 571 dev_warn(&client->dev, "Write to register " 572 "0x%02x failed! Please report to the driver " 573 "maintainer.\n", reg); 574 } 575 } else { /* ISA device */ 576 outb(reg, data->addr); 577 outb(val, data->addr + 1); 578 } 579 580 return res; 581} 582 583static struct dme1737_data *dme1737_update_device(struct device *dev) 584{ 585 struct dme1737_data *data = dev_get_drvdata(dev); 586 int ix; 587 u8 lsb[6]; 588 589 mutex_lock(&data->update_lock); 590 591 /* Enable a Vbat monitoring cycle every 10 mins */ 592 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) { 593 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data, 594 DME1737_REG_CONFIG) | 0x10); 595 data->last_vbat = jiffies; 596 } 597 598 /* Sample register contents every 1 sec */ 599 if (time_after(jiffies, data->last_update + HZ) || !data->valid) { 600 if (data->has_features & HAS_VID) { 601 data->vid = dme1737_read(data, DME1737_REG_VID) & 602 0x3f; 603 } 604 605 /* In (voltage) registers */ 606 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 607 /* Voltage inputs are stored as 16 bit values even 608 * though they have only 12 bits resolution. This is 609 * to make it consistent with the temp inputs. */ 610 if (ix == 7 && !(data->has_features & HAS_IN7)) { 611 continue; 612 } 613 data->in[ix] = dme1737_read(data, 614 DME1737_REG_IN(ix)) << 8; 615 data->in_min[ix] = dme1737_read(data, 616 DME1737_REG_IN_MIN(ix)); 617 data->in_max[ix] = dme1737_read(data, 618 DME1737_REG_IN_MAX(ix)); 619 } 620 621 /* Temp registers */ 622 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 623 /* Temp inputs are stored as 16 bit values even 624 * though they have only 12 bits resolution. This is 625 * to take advantage of implicit conversions between 626 * register values (2's complement) and temp values 627 * (signed decimal). */ 628 data->temp[ix] = dme1737_read(data, 629 DME1737_REG_TEMP(ix)) << 8; 630 data->temp_min[ix] = dme1737_read(data, 631 DME1737_REG_TEMP_MIN(ix)); 632 data->temp_max[ix] = dme1737_read(data, 633 DME1737_REG_TEMP_MAX(ix)); 634 if (data->has_features & HAS_TEMP_OFFSET) { 635 data->temp_offset[ix] = dme1737_read(data, 636 DME1737_REG_TEMP_OFFSET(ix)); 637 } 638 } 639 640 /* In and temp LSB registers 641 * The LSBs are latched when the MSBs are read, so the order in 642 * which the registers are read (MSB first, then LSB) is 643 * important! */ 644 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { 645 if (ix == 5 && !(data->has_features & HAS_IN7)) { 646 continue; 647 } 648 lsb[ix] = dme1737_read(data, 649 DME1737_REG_IN_TEMP_LSB(ix)); 650 } 651 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 652 if (ix == 7 && !(data->has_features & HAS_IN7)) { 653 continue; 654 } 655 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] << 656 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0; 657 } 658 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 659 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] << 660 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0; 661 } 662 663 /* Fan registers */ 664 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { 665 /* Skip reading registers if optional fans are not 666 * present */ 667 if (!(data->has_features & HAS_FAN(ix))) { 668 continue; 669 } 670 data->fan[ix] = dme1737_read(data, 671 DME1737_REG_FAN(ix)); 672 data->fan[ix] |= dme1737_read(data, 673 DME1737_REG_FAN(ix) + 1) << 8; 674 data->fan_min[ix] = dme1737_read(data, 675 DME1737_REG_FAN_MIN(ix)); 676 data->fan_min[ix] |= dme1737_read(data, 677 DME1737_REG_FAN_MIN(ix) + 1) << 8; 678 data->fan_opt[ix] = dme1737_read(data, 679 DME1737_REG_FAN_OPT(ix)); 680 /* fan_max exists only for fan[5-6] */ 681 if (ix > 3) { 682 data->fan_max[ix - 4] = dme1737_read(data, 683 DME1737_REG_FAN_MAX(ix)); 684 } 685 } 686 687 /* PWM registers */ 688 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { 689 /* Skip reading registers if optional PWMs are not 690 * present */ 691 if (!(data->has_features & HAS_PWM(ix))) { 692 continue; 693 } 694 data->pwm[ix] = dme1737_read(data, 695 DME1737_REG_PWM(ix)); 696 data->pwm_freq[ix] = dme1737_read(data, 697 DME1737_REG_PWM_FREQ(ix)); 698 /* pwm_config and pwm_min exist only for pwm[1-3] */ 699 if (ix < 3) { 700 data->pwm_config[ix] = dme1737_read(data, 701 DME1737_REG_PWM_CONFIG(ix)); 702 data->pwm_min[ix] = dme1737_read(data, 703 DME1737_REG_PWM_MIN(ix)); 704 } 705 } 706 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) { 707 data->pwm_rr[ix] = dme1737_read(data, 708 DME1737_REG_PWM_RR(ix)); 709 } 710 711 /* Thermal zone registers */ 712 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) { 713 /* Skip reading registers if zone3 is not present */ 714 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) { 715 continue; 716 } 717 /* sch5127 zone2 registers are special */ 718 if ((ix == 1) && (data->type == sch5127)) { 719 data->zone_low[1] = dme1737_read(data, 720 DME1737_REG_ZONE_LOW(2)); 721 data->zone_abs[1] = dme1737_read(data, 722 DME1737_REG_ZONE_ABS(2)); 723 } else { 724 data->zone_low[ix] = dme1737_read(data, 725 DME1737_REG_ZONE_LOW(ix)); 726 data->zone_abs[ix] = dme1737_read(data, 727 DME1737_REG_ZONE_ABS(ix)); 728 } 729 } 730 if (data->has_features & HAS_ZONE_HYST) { 731 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { 732 data->zone_hyst[ix] = dme1737_read(data, 733 DME1737_REG_ZONE_HYST(ix)); 734 } 735 } 736 737 /* Alarm registers */ 738 data->alarms = dme1737_read(data, 739 DME1737_REG_ALARM1); 740 /* Bit 7 tells us if the other alarm registers are non-zero and 741 * therefore also need to be read */ 742 if (data->alarms & 0x80) { 743 data->alarms |= dme1737_read(data, 744 DME1737_REG_ALARM2) << 8; 745 data->alarms |= dme1737_read(data, 746 DME1737_REG_ALARM3) << 16; 747 } 748 749 /* The ISA chips require explicit clearing of alarm bits. 750 * Don't worry, an alarm will come back if the condition 751 * that causes it still exists */ 752 if (!data->client) { 753 if (data->alarms & 0xff0000) { 754 dme1737_write(data, DME1737_REG_ALARM3, 755 0xff); 756 } 757 if (data->alarms & 0xff00) { 758 dme1737_write(data, DME1737_REG_ALARM2, 759 0xff); 760 } 761 if (data->alarms & 0xff) { 762 dme1737_write(data, DME1737_REG_ALARM1, 763 0xff); 764 } 765 } 766 767 data->last_update = jiffies; 768 data->valid = 1; 769 } 770 771 mutex_unlock(&data->update_lock); 772 773 return data; 774} 775 776/* --------------------------------------------------------------------- 777 * Voltage sysfs attributes 778 * ix = [0-7] 779 * --------------------------------------------------------------------- */ 780 781#define SYS_IN_INPUT 0 782#define SYS_IN_MIN 1 783#define SYS_IN_MAX 2 784#define SYS_IN_ALARM 3 785 786static ssize_t show_in(struct device *dev, struct device_attribute *attr, 787 char *buf) 788{ 789 struct dme1737_data *data = dme1737_update_device(dev); 790 struct sensor_device_attribute_2 791 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 792 int ix = sensor_attr_2->index; 793 int fn = sensor_attr_2->nr; 794 int res; 795 796 switch (fn) { 797 case SYS_IN_INPUT: 798 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); 799 break; 800 case SYS_IN_MIN: 801 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); 802 break; 803 case SYS_IN_MAX: 804 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); 805 break; 806 case SYS_IN_ALARM: 807 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; 808 break; 809 default: 810 res = 0; 811 dev_dbg(dev, "Unknown function %d.\n", fn); 812 } 813 814 return sprintf(buf, "%d\n", res); 815} 816 817static ssize_t set_in(struct device *dev, struct device_attribute *attr, 818 const char *buf, size_t count) 819{ 820 struct dme1737_data *data = dev_get_drvdata(dev); 821 struct sensor_device_attribute_2 822 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 823 int ix = sensor_attr_2->index; 824 int fn = sensor_attr_2->nr; 825 long val = simple_strtol(buf, NULL, 10); 826 827 mutex_lock(&data->update_lock); 828 switch (fn) { 829 case SYS_IN_MIN: 830 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); 831 dme1737_write(data, DME1737_REG_IN_MIN(ix), 832 data->in_min[ix]); 833 break; 834 case SYS_IN_MAX: 835 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); 836 dme1737_write(data, DME1737_REG_IN_MAX(ix), 837 data->in_max[ix]); 838 break; 839 default: 840 dev_dbg(dev, "Unknown function %d.\n", fn); 841 } 842 mutex_unlock(&data->update_lock); 843 844 return count; 845} 846 847/* --------------------------------------------------------------------- 848 * Temperature sysfs attributes 849 * ix = [0-2] 850 * --------------------------------------------------------------------- */ 851 852#define SYS_TEMP_INPUT 0 853#define SYS_TEMP_MIN 1 854#define SYS_TEMP_MAX 2 855#define SYS_TEMP_OFFSET 3 856#define SYS_TEMP_ALARM 4 857#define SYS_TEMP_FAULT 5 858 859static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 860 char *buf) 861{ 862 struct dme1737_data *data = dme1737_update_device(dev); 863 struct sensor_device_attribute_2 864 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 865 int ix = sensor_attr_2->index; 866 int fn = sensor_attr_2->nr; 867 int res; 868 869 switch (fn) { 870 case SYS_TEMP_INPUT: 871 res = TEMP_FROM_REG(data->temp[ix], 16); 872 break; 873 case SYS_TEMP_MIN: 874 res = TEMP_FROM_REG(data->temp_min[ix], 8); 875 break; 876 case SYS_TEMP_MAX: 877 res = TEMP_FROM_REG(data->temp_max[ix], 8); 878 break; 879 case SYS_TEMP_OFFSET: 880 res = TEMP_FROM_REG(data->temp_offset[ix], 8); 881 break; 882 case SYS_TEMP_ALARM: 883 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01; 884 break; 885 case SYS_TEMP_FAULT: 886 res = (((u16)data->temp[ix] & 0xff00) == 0x8000); 887 break; 888 default: 889 res = 0; 890 dev_dbg(dev, "Unknown function %d.\n", fn); 891 } 892 893 return sprintf(buf, "%d\n", res); 894} 895 896static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 897 const char *buf, size_t count) 898{ 899 struct dme1737_data *data = dev_get_drvdata(dev); 900 struct sensor_device_attribute_2 901 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 902 int ix = sensor_attr_2->index; 903 int fn = sensor_attr_2->nr; 904 long val = simple_strtol(buf, NULL, 10); 905 906 mutex_lock(&data->update_lock); 907 switch (fn) { 908 case SYS_TEMP_MIN: 909 data->temp_min[ix] = TEMP_TO_REG(val); 910 dme1737_write(data, DME1737_REG_TEMP_MIN(ix), 911 data->temp_min[ix]); 912 break; 913 case SYS_TEMP_MAX: 914 data->temp_max[ix] = TEMP_TO_REG(val); 915 dme1737_write(data, DME1737_REG_TEMP_MAX(ix), 916 data->temp_max[ix]); 917 break; 918 case SYS_TEMP_OFFSET: 919 data->temp_offset[ix] = TEMP_TO_REG(val); 920 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix), 921 data->temp_offset[ix]); 922 break; 923 default: 924 dev_dbg(dev, "Unknown function %d.\n", fn); 925 } 926 mutex_unlock(&data->update_lock); 927 928 return count; 929} 930 931/* --------------------------------------------------------------------- 932 * Zone sysfs attributes 933 * ix = [0-2] 934 * --------------------------------------------------------------------- */ 935 936#define SYS_ZONE_AUTO_CHANNELS_TEMP 0 937#define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1 938#define SYS_ZONE_AUTO_POINT1_TEMP 2 939#define SYS_ZONE_AUTO_POINT2_TEMP 3 940#define SYS_ZONE_AUTO_POINT3_TEMP 4 941 942static ssize_t show_zone(struct device *dev, struct device_attribute *attr, 943 char *buf) 944{ 945 struct dme1737_data *data = dme1737_update_device(dev); 946 struct sensor_device_attribute_2 947 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 948 int ix = sensor_attr_2->index; 949 int fn = sensor_attr_2->nr; 950 int res; 951 952 switch (fn) { 953 case SYS_ZONE_AUTO_CHANNELS_TEMP: 954 /* check config2 for non-standard temp-to-zone mapping */ 955 if ((ix == 1) && (data->config2 & 0x02)) { 956 res = 4; 957 } else { 958 res = 1 << ix; 959 } 960 break; 961 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 962 res = TEMP_FROM_REG(data->zone_low[ix], 8) - 963 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix); 964 break; 965 case SYS_ZONE_AUTO_POINT1_TEMP: 966 res = TEMP_FROM_REG(data->zone_low[ix], 8); 967 break; 968 case SYS_ZONE_AUTO_POINT2_TEMP: 969 /* pwm_freq holds the temp range bits in the upper nibble */ 970 res = TEMP_FROM_REG(data->zone_low[ix], 8) + 971 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]); 972 break; 973 case SYS_ZONE_AUTO_POINT3_TEMP: 974 res = TEMP_FROM_REG(data->zone_abs[ix], 8); 975 break; 976 default: 977 res = 0; 978 dev_dbg(dev, "Unknown function %d.\n", fn); 979 } 980 981 return sprintf(buf, "%d\n", res); 982} 983 984static ssize_t set_zone(struct device *dev, struct device_attribute *attr, 985 const char *buf, size_t count) 986{ 987 struct dme1737_data *data = dev_get_drvdata(dev); 988 struct sensor_device_attribute_2 989 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 990 int ix = sensor_attr_2->index; 991 int fn = sensor_attr_2->nr; 992 long val = simple_strtol(buf, NULL, 10); 993 994 mutex_lock(&data->update_lock); 995 switch (fn) { 996 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 997 /* Refresh the cache */ 998 data->zone_low[ix] = dme1737_read(data, 999 DME1737_REG_ZONE_LOW(ix)); 1000 /* Modify the temp hyst value */ 1001 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG( 1002 TEMP_FROM_REG(data->zone_low[ix], 8) - 1003 val, ix, dme1737_read(data, 1004 DME1737_REG_ZONE_HYST(ix == 2))); 1005 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2), 1006 data->zone_hyst[ix == 2]); 1007 break; 1008 case SYS_ZONE_AUTO_POINT1_TEMP: 1009 data->zone_low[ix] = TEMP_TO_REG(val); 1010 dme1737_write(data, DME1737_REG_ZONE_LOW(ix), 1011 data->zone_low[ix]); 1012 break; 1013 case SYS_ZONE_AUTO_POINT2_TEMP: 1014 /* Refresh the cache */ 1015 data->zone_low[ix] = dme1737_read(data, 1016 DME1737_REG_ZONE_LOW(ix)); 1017 /* Modify the temp range value (which is stored in the upper 1018 * nibble of the pwm_freq register) */ 1019 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - 1020 TEMP_FROM_REG(data->zone_low[ix], 8), 1021 dme1737_read(data, 1022 DME1737_REG_PWM_FREQ(ix))); 1023 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1024 data->pwm_freq[ix]); 1025 break; 1026 case SYS_ZONE_AUTO_POINT3_TEMP: 1027 data->zone_abs[ix] = TEMP_TO_REG(val); 1028 dme1737_write(data, DME1737_REG_ZONE_ABS(ix), 1029 data->zone_abs[ix]); 1030 break; 1031 default: 1032 dev_dbg(dev, "Unknown function %d.\n", fn); 1033 } 1034 mutex_unlock(&data->update_lock); 1035 1036 return count; 1037} 1038 1039/* --------------------------------------------------------------------- 1040 * Fan sysfs attributes 1041 * ix = [0-5] 1042 * --------------------------------------------------------------------- */ 1043 1044#define SYS_FAN_INPUT 0 1045#define SYS_FAN_MIN 1 1046#define SYS_FAN_MAX 2 1047#define SYS_FAN_ALARM 3 1048#define SYS_FAN_TYPE 4 1049 1050static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1051 char *buf) 1052{ 1053 struct dme1737_data *data = dme1737_update_device(dev); 1054 struct sensor_device_attribute_2 1055 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1056 int ix = sensor_attr_2->index; 1057 int fn = sensor_attr_2->nr; 1058 int res; 1059 1060 switch (fn) { 1061 case SYS_FAN_INPUT: 1062 res = FAN_FROM_REG(data->fan[ix], 1063 ix < 4 ? 0 : 1064 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1065 break; 1066 case SYS_FAN_MIN: 1067 res = FAN_FROM_REG(data->fan_min[ix], 1068 ix < 4 ? 0 : 1069 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1070 break; 1071 case SYS_FAN_MAX: 1072 /* only valid for fan[5-6] */ 1073 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]); 1074 break; 1075 case SYS_FAN_ALARM: 1076 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01; 1077 break; 1078 case SYS_FAN_TYPE: 1079 /* only valid for fan[1-4] */ 1080 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]); 1081 break; 1082 default: 1083 res = 0; 1084 dev_dbg(dev, "Unknown function %d.\n", fn); 1085 } 1086 1087 return sprintf(buf, "%d\n", res); 1088} 1089 1090static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1091 const char *buf, size_t count) 1092{ 1093 struct dme1737_data *data = dev_get_drvdata(dev); 1094 struct sensor_device_attribute_2 1095 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1096 int ix = sensor_attr_2->index; 1097 int fn = sensor_attr_2->nr; 1098 long val = simple_strtol(buf, NULL, 10); 1099 1100 mutex_lock(&data->update_lock); 1101 switch (fn) { 1102 case SYS_FAN_MIN: 1103 if (ix < 4) { 1104 data->fan_min[ix] = FAN_TO_REG(val, 0); 1105 } else { 1106 /* Refresh the cache */ 1107 data->fan_opt[ix] = dme1737_read(data, 1108 DME1737_REG_FAN_OPT(ix)); 1109 /* Modify the fan min value */ 1110 data->fan_min[ix] = FAN_TO_REG(val, 1111 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1112 } 1113 dme1737_write(data, DME1737_REG_FAN_MIN(ix), 1114 data->fan_min[ix] & 0xff); 1115 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1, 1116 data->fan_min[ix] >> 8); 1117 break; 1118 case SYS_FAN_MAX: 1119 /* Only valid for fan[5-6] */ 1120 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val); 1121 dme1737_write(data, DME1737_REG_FAN_MAX(ix), 1122 data->fan_max[ix - 4]); 1123 break; 1124 case SYS_FAN_TYPE: 1125 /* Only valid for fan[1-4] */ 1126 if (!(val == 1 || val == 2 || val == 4)) { 1127 count = -EINVAL; 1128 dev_warn(dev, "Fan type value %ld not " 1129 "supported. Choose one of 1, 2, or 4.\n", 1130 val); 1131 goto exit; 1132 } 1133 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data, 1134 DME1737_REG_FAN_OPT(ix))); 1135 dme1737_write(data, DME1737_REG_FAN_OPT(ix), 1136 data->fan_opt[ix]); 1137 break; 1138 default: 1139 dev_dbg(dev, "Unknown function %d.\n", fn); 1140 } 1141exit: 1142 mutex_unlock(&data->update_lock); 1143 1144 return count; 1145} 1146 1147/* --------------------------------------------------------------------- 1148 * PWM sysfs attributes 1149 * ix = [0-4] 1150 * --------------------------------------------------------------------- */ 1151 1152#define SYS_PWM 0 1153#define SYS_PWM_FREQ 1 1154#define SYS_PWM_ENABLE 2 1155#define SYS_PWM_RAMP_RATE 3 1156#define SYS_PWM_AUTO_CHANNELS_ZONE 4 1157#define SYS_PWM_AUTO_PWM_MIN 5 1158#define SYS_PWM_AUTO_POINT1_PWM 6 1159#define SYS_PWM_AUTO_POINT2_PWM 7 1160 1161static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1162 char *buf) 1163{ 1164 struct dme1737_data *data = dme1737_update_device(dev); 1165 struct sensor_device_attribute_2 1166 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1167 int ix = sensor_attr_2->index; 1168 int fn = sensor_attr_2->nr; 1169 int res; 1170 1171 switch (fn) { 1172 case SYS_PWM: 1173 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) { 1174 res = 255; 1175 } else { 1176 res = data->pwm[ix]; 1177 } 1178 break; 1179 case SYS_PWM_FREQ: 1180 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]); 1181 break; 1182 case SYS_PWM_ENABLE: 1183 if (ix >= 3) { 1184 res = 1; /* pwm[5-6] hard-wired to manual mode */ 1185 } else { 1186 res = PWM_EN_FROM_REG(data->pwm_config[ix]); 1187 } 1188 break; 1189 case SYS_PWM_RAMP_RATE: 1190 /* Only valid for pwm[1-3] */ 1191 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix); 1192 break; 1193 case SYS_PWM_AUTO_CHANNELS_ZONE: 1194 /* Only valid for pwm[1-3] */ 1195 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1196 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]); 1197 } else { 1198 res = data->pwm_acz[ix]; 1199 } 1200 break; 1201 case SYS_PWM_AUTO_PWM_MIN: 1202 /* Only valid for pwm[1-3] */ 1203 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) { 1204 res = data->pwm_min[ix]; 1205 } else { 1206 res = 0; 1207 } 1208 break; 1209 case SYS_PWM_AUTO_POINT1_PWM: 1210 /* Only valid for pwm[1-3] */ 1211 res = data->pwm_min[ix]; 1212 break; 1213 case SYS_PWM_AUTO_POINT2_PWM: 1214 /* Only valid for pwm[1-3] */ 1215 res = 255; /* hard-wired */ 1216 break; 1217 default: 1218 res = 0; 1219 dev_dbg(dev, "Unknown function %d.\n", fn); 1220 } 1221 1222 return sprintf(buf, "%d\n", res); 1223} 1224 1225static struct attribute *dme1737_pwm_chmod_attr[]; 1226static void dme1737_chmod_file(struct device*, struct attribute*, umode_t); 1227 1228static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1229 const char *buf, size_t count) 1230{ 1231 struct dme1737_data *data = dev_get_drvdata(dev); 1232 struct sensor_device_attribute_2 1233 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1234 int ix = sensor_attr_2->index; 1235 int fn = sensor_attr_2->nr; 1236 long val = simple_strtol(buf, NULL, 10); 1237 1238 mutex_lock(&data->update_lock); 1239 switch (fn) { 1240 case SYS_PWM: 1241 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255); 1242 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]); 1243 break; 1244 case SYS_PWM_FREQ: 1245 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data, 1246 DME1737_REG_PWM_FREQ(ix))); 1247 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1248 data->pwm_freq[ix]); 1249 break; 1250 case SYS_PWM_ENABLE: 1251 /* Only valid for pwm[1-3] */ 1252 if (val < 0 || val > 2) { 1253 count = -EINVAL; 1254 dev_warn(dev, "PWM enable %ld not " 1255 "supported. Choose one of 0, 1, or 2.\n", 1256 val); 1257 goto exit; 1258 } 1259 /* Refresh the cache */ 1260 data->pwm_config[ix] = dme1737_read(data, 1261 DME1737_REG_PWM_CONFIG(ix)); 1262 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) { 1263 /* Bail out if no change */ 1264 goto exit; 1265 } 1266 /* Do some housekeeping if we are currently in auto mode */ 1267 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1268 /* Save the current zone channel assignment */ 1269 data->pwm_acz[ix] = PWM_ACZ_FROM_REG( 1270 data->pwm_config[ix]); 1271 /* Save the current ramp rate state and disable it */ 1272 data->pwm_rr[ix > 0] = dme1737_read(data, 1273 DME1737_REG_PWM_RR(ix > 0)); 1274 data->pwm_rr_en &= ~(1 << ix); 1275 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) { 1276 data->pwm_rr_en |= (1 << ix); 1277 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix, 1278 data->pwm_rr[ix > 0]); 1279 dme1737_write(data, 1280 DME1737_REG_PWM_RR(ix > 0), 1281 data->pwm_rr[ix > 0]); 1282 } 1283 } 1284 /* Set the new PWM mode */ 1285 switch (val) { 1286 case 0: 1287 /* Change permissions of pwm[ix] to read-only */ 1288 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1289 S_IRUGO); 1290 /* Turn fan fully on */ 1291 data->pwm_config[ix] = PWM_EN_TO_REG(0, 1292 data->pwm_config[ix]); 1293 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1294 data->pwm_config[ix]); 1295 break; 1296 case 1: 1297 /* Turn on manual mode */ 1298 data->pwm_config[ix] = PWM_EN_TO_REG(1, 1299 data->pwm_config[ix]); 1300 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1301 data->pwm_config[ix]); 1302 /* Change permissions of pwm[ix] to read-writeable */ 1303 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1304 S_IRUGO | S_IWUSR); 1305 break; 1306 case 2: 1307 /* Change permissions of pwm[ix] to read-only */ 1308 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1309 S_IRUGO); 1310 /* Turn on auto mode using the saved zone channel 1311 * assignment */ 1312 data->pwm_config[ix] = PWM_ACZ_TO_REG( 1313 data->pwm_acz[ix], 1314 data->pwm_config[ix]); 1315 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1316 data->pwm_config[ix]); 1317 /* Enable PWM ramp rate if previously enabled */ 1318 if (data->pwm_rr_en & (1 << ix)) { 1319 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix, 1320 dme1737_read(data, 1321 DME1737_REG_PWM_RR(ix > 0))); 1322 dme1737_write(data, 1323 DME1737_REG_PWM_RR(ix > 0), 1324 data->pwm_rr[ix > 0]); 1325 } 1326 break; 1327 } 1328 break; 1329 case SYS_PWM_RAMP_RATE: 1330 /* Only valid for pwm[1-3] */ 1331 /* Refresh the cache */ 1332 data->pwm_config[ix] = dme1737_read(data, 1333 DME1737_REG_PWM_CONFIG(ix)); 1334 data->pwm_rr[ix > 0] = dme1737_read(data, 1335 DME1737_REG_PWM_RR(ix > 0)); 1336 /* Set the ramp rate value */ 1337 if (val > 0) { 1338 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, 1339 data->pwm_rr[ix > 0]); 1340 } 1341 /* Enable/disable the feature only if the associated PWM 1342 * output is in automatic mode. */ 1343 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1344 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, 1345 data->pwm_rr[ix > 0]); 1346 } 1347 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0), 1348 data->pwm_rr[ix > 0]); 1349 break; 1350 case SYS_PWM_AUTO_CHANNELS_ZONE: 1351 /* Only valid for pwm[1-3] */ 1352 if (!(val == 1 || val == 2 || val == 4 || 1353 val == 6 || val == 7)) { 1354 count = -EINVAL; 1355 dev_warn(dev, "PWM auto channels zone %ld " 1356 "not supported. Choose one of 1, 2, 4, 6, " 1357 "or 7.\n", val); 1358 goto exit; 1359 } 1360 /* Refresh the cache */ 1361 data->pwm_config[ix] = dme1737_read(data, 1362 DME1737_REG_PWM_CONFIG(ix)); 1363 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1364 /* PWM is already in auto mode so update the temp 1365 * channel assignment */ 1366 data->pwm_config[ix] = PWM_ACZ_TO_REG(val, 1367 data->pwm_config[ix]); 1368 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1369 data->pwm_config[ix]); 1370 } else { 1371 /* PWM is not in auto mode so we save the temp 1372 * channel assignment for later use */ 1373 data->pwm_acz[ix] = val; 1374 } 1375 break; 1376 case SYS_PWM_AUTO_PWM_MIN: 1377 /* Only valid for pwm[1-3] */ 1378 /* Refresh the cache */ 1379 data->pwm_min[ix] = dme1737_read(data, 1380 DME1737_REG_PWM_MIN(ix)); 1381 /* There are only 2 values supported for the auto_pwm_min 1382 * value: 0 or auto_point1_pwm. So if the temperature drops 1383 * below the auto_point1_temp_hyst value, the fan either turns 1384 * off or runs at auto_point1_pwm duty-cycle. */ 1385 if (val > ((data->pwm_min[ix] + 1) / 2)) { 1386 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix, 1387 dme1737_read(data, 1388 DME1737_REG_PWM_RR(0))); 1389 } else { 1390 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix, 1391 dme1737_read(data, 1392 DME1737_REG_PWM_RR(0))); 1393 } 1394 dme1737_write(data, DME1737_REG_PWM_RR(0), 1395 data->pwm_rr[0]); 1396 break; 1397 case SYS_PWM_AUTO_POINT1_PWM: 1398 /* Only valid for pwm[1-3] */ 1399 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255); 1400 dme1737_write(data, DME1737_REG_PWM_MIN(ix), 1401 data->pwm_min[ix]); 1402 break; 1403 default: 1404 dev_dbg(dev, "Unknown function %d.\n", fn); 1405 } 1406exit: 1407 mutex_unlock(&data->update_lock); 1408 1409 return count; 1410} 1411 1412/* --------------------------------------------------------------------- 1413 * Miscellaneous sysfs attributes 1414 * --------------------------------------------------------------------- */ 1415 1416static ssize_t show_vrm(struct device *dev, struct device_attribute *attr, 1417 char *buf) 1418{ 1419 struct i2c_client *client = to_i2c_client(dev); 1420 struct dme1737_data *data = i2c_get_clientdata(client); 1421 1422 return sprintf(buf, "%d\n", data->vrm); 1423} 1424 1425static ssize_t set_vrm(struct device *dev, struct device_attribute *attr, 1426 const char *buf, size_t count) 1427{ 1428 struct dme1737_data *data = dev_get_drvdata(dev); 1429 long val = simple_strtol(buf, NULL, 10); 1430 1431 data->vrm = val; 1432 return count; 1433} 1434 1435static ssize_t show_vid(struct device *dev, struct device_attribute *attr, 1436 char *buf) 1437{ 1438 struct dme1737_data *data = dme1737_update_device(dev); 1439 1440 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); 1441} 1442 1443static ssize_t show_name(struct device *dev, struct device_attribute *attr, 1444 char *buf) 1445{ 1446 struct dme1737_data *data = dev_get_drvdata(dev); 1447 1448 return sprintf(buf, "%s\n", data->name); 1449} 1450 1451/* --------------------------------------------------------------------- 1452 * Sysfs device attribute defines and structs 1453 * --------------------------------------------------------------------- */ 1454 1455/* Voltages 0-7 */ 1456 1457#define SENSOR_DEVICE_ATTR_IN(ix) \ 1458static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \ 1459 show_in, NULL, SYS_IN_INPUT, ix); \ 1460static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \ 1461 show_in, set_in, SYS_IN_MIN, ix); \ 1462static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \ 1463 show_in, set_in, SYS_IN_MAX, ix); \ 1464static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \ 1465 show_in, NULL, SYS_IN_ALARM, ix) 1466 1467SENSOR_DEVICE_ATTR_IN(0); 1468SENSOR_DEVICE_ATTR_IN(1); 1469SENSOR_DEVICE_ATTR_IN(2); 1470SENSOR_DEVICE_ATTR_IN(3); 1471SENSOR_DEVICE_ATTR_IN(4); 1472SENSOR_DEVICE_ATTR_IN(5); 1473SENSOR_DEVICE_ATTR_IN(6); 1474SENSOR_DEVICE_ATTR_IN(7); 1475 1476/* Temperatures 1-3 */ 1477 1478#define SENSOR_DEVICE_ATTR_TEMP(ix) \ 1479static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \ 1480 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \ 1481static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \ 1482 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \ 1483static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \ 1484 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \ 1485static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \ 1486 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \ 1487static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \ 1488 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \ 1489static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \ 1490 show_temp, NULL, SYS_TEMP_FAULT, ix-1) 1491 1492SENSOR_DEVICE_ATTR_TEMP(1); 1493SENSOR_DEVICE_ATTR_TEMP(2); 1494SENSOR_DEVICE_ATTR_TEMP(3); 1495 1496/* Zones 1-3 */ 1497 1498#define SENSOR_DEVICE_ATTR_ZONE(ix) \ 1499static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \ 1500 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \ 1501static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \ 1502 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \ 1503static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \ 1504 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \ 1505static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \ 1506 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \ 1507static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \ 1508 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1) 1509 1510SENSOR_DEVICE_ATTR_ZONE(1); 1511SENSOR_DEVICE_ATTR_ZONE(2); 1512SENSOR_DEVICE_ATTR_ZONE(3); 1513 1514/* Fans 1-4 */ 1515 1516#define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \ 1517static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1518 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1519static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1520 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1521static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1522 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1523static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \ 1524 show_fan, set_fan, SYS_FAN_TYPE, ix-1) 1525 1526SENSOR_DEVICE_ATTR_FAN_1TO4(1); 1527SENSOR_DEVICE_ATTR_FAN_1TO4(2); 1528SENSOR_DEVICE_ATTR_FAN_1TO4(3); 1529SENSOR_DEVICE_ATTR_FAN_1TO4(4); 1530 1531/* Fans 5-6 */ 1532 1533#define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \ 1534static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1535 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1536static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1537 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1538static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1539 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1540static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \ 1541 show_fan, set_fan, SYS_FAN_MAX, ix-1) 1542 1543SENSOR_DEVICE_ATTR_FAN_5TO6(5); 1544SENSOR_DEVICE_ATTR_FAN_5TO6(6); 1545 1546/* PWMs 1-3 */ 1547 1548#define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \ 1549static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1550 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1551static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1552 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1553static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1554 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \ 1555static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \ 1556 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \ 1557static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \ 1558 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \ 1559static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \ 1560 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \ 1561static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \ 1562 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \ 1563static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \ 1564 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1) 1565 1566SENSOR_DEVICE_ATTR_PWM_1TO3(1); 1567SENSOR_DEVICE_ATTR_PWM_1TO3(2); 1568SENSOR_DEVICE_ATTR_PWM_1TO3(3); 1569 1570/* PWMs 5-6 */ 1571 1572#define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \ 1573static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1574 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1575static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1576 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1577static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1578 show_pwm, NULL, SYS_PWM_ENABLE, ix-1) 1579 1580SENSOR_DEVICE_ATTR_PWM_5TO6(5); 1581SENSOR_DEVICE_ATTR_PWM_5TO6(6); 1582 1583/* Misc */ 1584 1585static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm); 1586static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); 1587static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */ 1588 1589/* This struct holds all the attributes that are always present and need to be 1590 * created unconditionally. The attributes that need modification of their 1591 * permissions are created read-only and write permissions are added or removed 1592 * on the fly when required */ 1593static struct attribute *dme1737_attr[] = { 1594 /* Voltages */ 1595 &sensor_dev_attr_in0_input.dev_attr.attr, 1596 &sensor_dev_attr_in0_min.dev_attr.attr, 1597 &sensor_dev_attr_in0_max.dev_attr.attr, 1598 &sensor_dev_attr_in0_alarm.dev_attr.attr, 1599 &sensor_dev_attr_in1_input.dev_attr.attr, 1600 &sensor_dev_attr_in1_min.dev_attr.attr, 1601 &sensor_dev_attr_in1_max.dev_attr.attr, 1602 &sensor_dev_attr_in1_alarm.dev_attr.attr, 1603 &sensor_dev_attr_in2_input.dev_attr.attr, 1604 &sensor_dev_attr_in2_min.dev_attr.attr, 1605 &sensor_dev_attr_in2_max.dev_attr.attr, 1606 &sensor_dev_attr_in2_alarm.dev_attr.attr, 1607 &sensor_dev_attr_in3_input.dev_attr.attr, 1608 &sensor_dev_attr_in3_min.dev_attr.attr, 1609 &sensor_dev_attr_in3_max.dev_attr.attr, 1610 &sensor_dev_attr_in3_alarm.dev_attr.attr, 1611 &sensor_dev_attr_in4_input.dev_attr.attr, 1612 &sensor_dev_attr_in4_min.dev_attr.attr, 1613 &sensor_dev_attr_in4_max.dev_attr.attr, 1614 &sensor_dev_attr_in4_alarm.dev_attr.attr, 1615 &sensor_dev_attr_in5_input.dev_attr.attr, 1616 &sensor_dev_attr_in5_min.dev_attr.attr, 1617 &sensor_dev_attr_in5_max.dev_attr.attr, 1618 &sensor_dev_attr_in5_alarm.dev_attr.attr, 1619 &sensor_dev_attr_in6_input.dev_attr.attr, 1620 &sensor_dev_attr_in6_min.dev_attr.attr, 1621 &sensor_dev_attr_in6_max.dev_attr.attr, 1622 &sensor_dev_attr_in6_alarm.dev_attr.attr, 1623 /* Temperatures */ 1624 &sensor_dev_attr_temp1_input.dev_attr.attr, 1625 &sensor_dev_attr_temp1_min.dev_attr.attr, 1626 &sensor_dev_attr_temp1_max.dev_attr.attr, 1627 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 1628 &sensor_dev_attr_temp1_fault.dev_attr.attr, 1629 &sensor_dev_attr_temp2_input.dev_attr.attr, 1630 &sensor_dev_attr_temp2_min.dev_attr.attr, 1631 &sensor_dev_attr_temp2_max.dev_attr.attr, 1632 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 1633 &sensor_dev_attr_temp2_fault.dev_attr.attr, 1634 &sensor_dev_attr_temp3_input.dev_attr.attr, 1635 &sensor_dev_attr_temp3_min.dev_attr.attr, 1636 &sensor_dev_attr_temp3_max.dev_attr.attr, 1637 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 1638 &sensor_dev_attr_temp3_fault.dev_attr.attr, 1639 /* Zones */ 1640 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1641 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1642 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1643 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, 1644 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1645 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1646 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1647 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, 1648 NULL 1649}; 1650 1651static const struct attribute_group dme1737_group = { 1652 .attrs = dme1737_attr, 1653}; 1654 1655/* The following struct holds temp offset attributes, which are not available 1656 * in all chips. The following chips support them: 1657 * DME1737, SCH311x */ 1658static struct attribute *dme1737_temp_offset_attr[] = { 1659 &sensor_dev_attr_temp1_offset.dev_attr.attr, 1660 &sensor_dev_attr_temp2_offset.dev_attr.attr, 1661 &sensor_dev_attr_temp3_offset.dev_attr.attr, 1662 NULL 1663}; 1664 1665static const struct attribute_group dme1737_temp_offset_group = { 1666 .attrs = dme1737_temp_offset_attr, 1667}; 1668 1669/* The following struct holds VID related attributes, which are not available 1670 * in all chips. The following chips support them: 1671 * DME1737 */ 1672static struct attribute *dme1737_vid_attr[] = { 1673 &dev_attr_vrm.attr, 1674 &dev_attr_cpu0_vid.attr, 1675 NULL 1676}; 1677 1678static const struct attribute_group dme1737_vid_group = { 1679 .attrs = dme1737_vid_attr, 1680}; 1681 1682/* The following struct holds temp zone 3 related attributes, which are not 1683 * available in all chips. The following chips support them: 1684 * DME1737, SCH311x, SCH5027 */ 1685static struct attribute *dme1737_zone3_attr[] = { 1686 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1687 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1688 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1689 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, 1690 NULL 1691}; 1692 1693static const struct attribute_group dme1737_zone3_group = { 1694 .attrs = dme1737_zone3_attr, 1695}; 1696 1697 1698/* The following struct holds temp zone hysteresis related attributes, which 1699 * are not available in all chips. The following chips support them: 1700 * DME1737, SCH311x */ 1701static struct attribute *dme1737_zone_hyst_attr[] = { 1702 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, 1703 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, 1704 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, 1705 NULL 1706}; 1707 1708static const struct attribute_group dme1737_zone_hyst_group = { 1709 .attrs = dme1737_zone_hyst_attr, 1710}; 1711 1712/* The following struct holds voltage in7 related attributes, which 1713 * are not available in all chips. The following chips support them: 1714 * SCH5127 */ 1715static struct attribute *dme1737_in7_attr[] = { 1716 &sensor_dev_attr_in7_input.dev_attr.attr, 1717 &sensor_dev_attr_in7_min.dev_attr.attr, 1718 &sensor_dev_attr_in7_max.dev_attr.attr, 1719 &sensor_dev_attr_in7_alarm.dev_attr.attr, 1720 NULL 1721}; 1722 1723static const struct attribute_group dme1737_in7_group = { 1724 .attrs = dme1737_in7_attr, 1725}; 1726 1727/* The following structs hold the PWM attributes, some of which are optional. 1728 * Their creation depends on the chip configuration which is determined during 1729 * module load. */ 1730static struct attribute *dme1737_pwm1_attr[] = { 1731 &sensor_dev_attr_pwm1.dev_attr.attr, 1732 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1733 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1734 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1735 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1736 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1737 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 1738 NULL 1739}; 1740static struct attribute *dme1737_pwm2_attr[] = { 1741 &sensor_dev_attr_pwm2.dev_attr.attr, 1742 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1743 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1744 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1745 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1746 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1747 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 1748 NULL 1749}; 1750static struct attribute *dme1737_pwm3_attr[] = { 1751 &sensor_dev_attr_pwm3.dev_attr.attr, 1752 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1753 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1754 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1755 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1756 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1757 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 1758 NULL 1759}; 1760static struct attribute *dme1737_pwm5_attr[] = { 1761 &sensor_dev_attr_pwm5.dev_attr.attr, 1762 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1763 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 1764 NULL 1765}; 1766static struct attribute *dme1737_pwm6_attr[] = { 1767 &sensor_dev_attr_pwm6.dev_attr.attr, 1768 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1769 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 1770 NULL 1771}; 1772 1773static const struct attribute_group dme1737_pwm_group[] = { 1774 { .attrs = dme1737_pwm1_attr }, 1775 { .attrs = dme1737_pwm2_attr }, 1776 { .attrs = dme1737_pwm3_attr }, 1777 { .attrs = NULL }, 1778 { .attrs = dme1737_pwm5_attr }, 1779 { .attrs = dme1737_pwm6_attr }, 1780}; 1781 1782/* The following struct holds auto PWM min attributes, which are not available 1783 * in all chips. Their creation depends on the chip type which is determined 1784 * during module load. */ 1785static struct attribute *dme1737_auto_pwm_min_attr[] = { 1786 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, 1787 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, 1788 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, 1789}; 1790 1791/* The following structs hold the fan attributes, some of which are optional. 1792 * Their creation depends on the chip configuration which is determined during 1793 * module load. */ 1794static struct attribute *dme1737_fan1_attr[] = { 1795 &sensor_dev_attr_fan1_input.dev_attr.attr, 1796 &sensor_dev_attr_fan1_min.dev_attr.attr, 1797 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 1798 &sensor_dev_attr_fan1_type.dev_attr.attr, 1799 NULL 1800}; 1801static struct attribute *dme1737_fan2_attr[] = { 1802 &sensor_dev_attr_fan2_input.dev_attr.attr, 1803 &sensor_dev_attr_fan2_min.dev_attr.attr, 1804 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 1805 &sensor_dev_attr_fan2_type.dev_attr.attr, 1806 NULL 1807}; 1808static struct attribute *dme1737_fan3_attr[] = { 1809 &sensor_dev_attr_fan3_input.dev_attr.attr, 1810 &sensor_dev_attr_fan3_min.dev_attr.attr, 1811 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 1812 &sensor_dev_attr_fan3_type.dev_attr.attr, 1813 NULL 1814}; 1815static struct attribute *dme1737_fan4_attr[] = { 1816 &sensor_dev_attr_fan4_input.dev_attr.attr, 1817 &sensor_dev_attr_fan4_min.dev_attr.attr, 1818 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 1819 &sensor_dev_attr_fan4_type.dev_attr.attr, 1820 NULL 1821}; 1822static struct attribute *dme1737_fan5_attr[] = { 1823 &sensor_dev_attr_fan5_input.dev_attr.attr, 1824 &sensor_dev_attr_fan5_min.dev_attr.attr, 1825 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 1826 &sensor_dev_attr_fan5_max.dev_attr.attr, 1827 NULL 1828}; 1829static struct attribute *dme1737_fan6_attr[] = { 1830 &sensor_dev_attr_fan6_input.dev_attr.attr, 1831 &sensor_dev_attr_fan6_min.dev_attr.attr, 1832 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 1833 &sensor_dev_attr_fan6_max.dev_attr.attr, 1834 NULL 1835}; 1836 1837static const struct attribute_group dme1737_fan_group[] = { 1838 { .attrs = dme1737_fan1_attr }, 1839 { .attrs = dme1737_fan2_attr }, 1840 { .attrs = dme1737_fan3_attr }, 1841 { .attrs = dme1737_fan4_attr }, 1842 { .attrs = dme1737_fan5_attr }, 1843 { .attrs = dme1737_fan6_attr }, 1844}; 1845 1846/* The permissions of the following zone attributes are changed to read- 1847 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1848static struct attribute *dme1737_zone_chmod_attr[] = { 1849 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1850 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1851 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1852 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1853 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1854 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1855 NULL 1856}; 1857 1858static const struct attribute_group dme1737_zone_chmod_group = { 1859 .attrs = dme1737_zone_chmod_attr, 1860}; 1861 1862 1863/* The permissions of the following zone 3 attributes are changed to read- 1864 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1865static struct attribute *dme1737_zone3_chmod_attr[] = { 1866 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1867 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1868 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1869 NULL 1870}; 1871 1872static const struct attribute_group dme1737_zone3_chmod_group = { 1873 .attrs = dme1737_zone3_chmod_attr, 1874}; 1875 1876/* The permissions of the following PWM attributes are changed to read- 1877 * writeable if the chip is *not* locked and the respective PWM is available. 1878 * Otherwise they stay read-only. */ 1879static struct attribute *dme1737_pwm1_chmod_attr[] = { 1880 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1881 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1882 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1883 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1884 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1885 NULL 1886}; 1887static struct attribute *dme1737_pwm2_chmod_attr[] = { 1888 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1889 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1890 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1891 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1892 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1893 NULL 1894}; 1895static struct attribute *dme1737_pwm3_chmod_attr[] = { 1896 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1897 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1898 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1899 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1900 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1901 NULL 1902}; 1903static struct attribute *dme1737_pwm5_chmod_attr[] = { 1904 &sensor_dev_attr_pwm5.dev_attr.attr, 1905 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1906 NULL 1907}; 1908static struct attribute *dme1737_pwm6_chmod_attr[] = { 1909 &sensor_dev_attr_pwm6.dev_attr.attr, 1910 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1911 NULL 1912}; 1913 1914static const struct attribute_group dme1737_pwm_chmod_group[] = { 1915 { .attrs = dme1737_pwm1_chmod_attr }, 1916 { .attrs = dme1737_pwm2_chmod_attr }, 1917 { .attrs = dme1737_pwm3_chmod_attr }, 1918 { .attrs = NULL }, 1919 { .attrs = dme1737_pwm5_chmod_attr }, 1920 { .attrs = dme1737_pwm6_chmod_attr }, 1921}; 1922 1923/* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the 1924 * chip is not locked. Otherwise they are read-only. */ 1925static struct attribute *dme1737_pwm_chmod_attr[] = { 1926 &sensor_dev_attr_pwm1.dev_attr.attr, 1927 &sensor_dev_attr_pwm2.dev_attr.attr, 1928 &sensor_dev_attr_pwm3.dev_attr.attr, 1929}; 1930 1931/* --------------------------------------------------------------------- 1932 * Super-IO functions 1933 * --------------------------------------------------------------------- */ 1934 1935static inline void dme1737_sio_enter(int sio_cip) 1936{ 1937 outb(0x55, sio_cip); 1938} 1939 1940static inline void dme1737_sio_exit(int sio_cip) 1941{ 1942 outb(0xaa, sio_cip); 1943} 1944 1945static inline int dme1737_sio_inb(int sio_cip, int reg) 1946{ 1947 outb(reg, sio_cip); 1948 return inb(sio_cip + 1); 1949} 1950 1951static inline void dme1737_sio_outb(int sio_cip, int reg, int val) 1952{ 1953 outb(reg, sio_cip); 1954 outb(val, sio_cip + 1); 1955} 1956 1957/* --------------------------------------------------------------------- 1958 * Device initialization 1959 * --------------------------------------------------------------------- */ 1960 1961static int dme1737_i2c_get_features(int, struct dme1737_data*); 1962 1963static void dme1737_chmod_file(struct device *dev, 1964 struct attribute *attr, umode_t mode) 1965{ 1966 if (sysfs_chmod_file(&dev->kobj, attr, mode)) { 1967 dev_warn(dev, "Failed to change permissions of %s.\n", 1968 attr->name); 1969 } 1970} 1971 1972static void dme1737_chmod_group(struct device *dev, 1973 const struct attribute_group *group, 1974 umode_t mode) 1975{ 1976 struct attribute **attr; 1977 1978 for (attr = group->attrs; *attr; attr++) { 1979 dme1737_chmod_file(dev, *attr, mode); 1980 } 1981} 1982 1983static void dme1737_remove_files(struct device *dev) 1984{ 1985 struct dme1737_data *data = dev_get_drvdata(dev); 1986 int ix; 1987 1988 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 1989 if (data->has_features & HAS_FAN(ix)) { 1990 sysfs_remove_group(&dev->kobj, 1991 &dme1737_fan_group[ix]); 1992 } 1993 } 1994 1995 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 1996 if (data->has_features & HAS_PWM(ix)) { 1997 sysfs_remove_group(&dev->kobj, 1998 &dme1737_pwm_group[ix]); 1999 if ((data->has_features & HAS_PWM_MIN) && ix < 3) { 2000 sysfs_remove_file(&dev->kobj, 2001 dme1737_auto_pwm_min_attr[ix]); 2002 } 2003 } 2004 } 2005 2006 if (data->has_features & HAS_TEMP_OFFSET) { 2007 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group); 2008 } 2009 if (data->has_features & HAS_VID) { 2010 sysfs_remove_group(&dev->kobj, &dme1737_vid_group); 2011 } 2012 if (data->has_features & HAS_ZONE3) { 2013 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group); 2014 } 2015 if (data->has_features & HAS_ZONE_HYST) { 2016 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group); 2017 } 2018 if (data->has_features & HAS_IN7) { 2019 sysfs_remove_group(&dev->kobj, &dme1737_in7_group); 2020 } 2021 sysfs_remove_group(&dev->kobj, &dme1737_group); 2022 2023 if (!data->client) { 2024 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr); 2025 } 2026} 2027 2028static int dme1737_create_files(struct device *dev) 2029{ 2030 struct dme1737_data *data = dev_get_drvdata(dev); 2031 int err, ix; 2032 2033 /* Create a name attribute for ISA devices */ 2034 if (!data->client) { 2035 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr); 2036 if (err) { 2037 goto exit; 2038 } 2039 } 2040 2041 /* Create standard sysfs attributes */ 2042 err = sysfs_create_group(&dev->kobj, &dme1737_group); 2043 if (err) { 2044 goto exit_remove; 2045 } 2046 2047 /* Create chip-dependent sysfs attributes */ 2048 if (data->has_features & HAS_TEMP_OFFSET) { 2049 err = sysfs_create_group(&dev->kobj, 2050 &dme1737_temp_offset_group); 2051 if (err) { 2052 goto exit_remove; 2053 } 2054 } 2055 if (data->has_features & HAS_VID) { 2056 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group); 2057 if (err) { 2058 goto exit_remove; 2059 } 2060 } 2061 if (data->has_features & HAS_ZONE3) { 2062 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group); 2063 if (err) { 2064 goto exit_remove; 2065 } 2066 } 2067 if (data->has_features & HAS_ZONE_HYST) { 2068 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group); 2069 if (err) { 2070 goto exit_remove; 2071 } 2072 } 2073 if (data->has_features & HAS_IN7) { 2074 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group); 2075 if (err) { 2076 goto exit_remove; 2077 } 2078 } 2079 2080 /* Create fan sysfs attributes */ 2081 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 2082 if (data->has_features & HAS_FAN(ix)) { 2083 err = sysfs_create_group(&dev->kobj, 2084 &dme1737_fan_group[ix]); 2085 if (err) { 2086 goto exit_remove; 2087 } 2088 } 2089 } 2090 2091 /* Create PWM sysfs attributes */ 2092 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 2093 if (data->has_features & HAS_PWM(ix)) { 2094 err = sysfs_create_group(&dev->kobj, 2095 &dme1737_pwm_group[ix]); 2096 if (err) { 2097 goto exit_remove; 2098 } 2099 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) { 2100 err = sysfs_create_file(&dev->kobj, 2101 dme1737_auto_pwm_min_attr[ix]); 2102 if (err) { 2103 goto exit_remove; 2104 } 2105 } 2106 } 2107 } 2108 2109 /* Inform if the device is locked. Otherwise change the permissions of 2110 * selected attributes from read-only to read-writeable. */ 2111 if (data->config & 0x02) { 2112 dev_info(dev, "Device is locked. Some attributes " 2113 "will be read-only.\n"); 2114 } else { 2115 /* Change permissions of zone sysfs attributes */ 2116 dme1737_chmod_group(dev, &dme1737_zone_chmod_group, 2117 S_IRUGO | S_IWUSR); 2118 2119 /* Change permissions of chip-dependent sysfs attributes */ 2120 if (data->has_features & HAS_TEMP_OFFSET) { 2121 dme1737_chmod_group(dev, &dme1737_temp_offset_group, 2122 S_IRUGO | S_IWUSR); 2123 } 2124 if (data->has_features & HAS_ZONE3) { 2125 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group, 2126 S_IRUGO | S_IWUSR); 2127 } 2128 if (data->has_features & HAS_ZONE_HYST) { 2129 dme1737_chmod_group(dev, &dme1737_zone_hyst_group, 2130 S_IRUGO | S_IWUSR); 2131 } 2132 2133 /* Change permissions of PWM sysfs attributes */ 2134 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { 2135 if (data->has_features & HAS_PWM(ix)) { 2136 dme1737_chmod_group(dev, 2137 &dme1737_pwm_chmod_group[ix], 2138 S_IRUGO | S_IWUSR); 2139 if ((data->has_features & HAS_PWM_MIN) && 2140 ix < 3) { 2141 dme1737_chmod_file(dev, 2142 dme1737_auto_pwm_min_attr[ix], 2143 S_IRUGO | S_IWUSR); 2144 } 2145 } 2146 } 2147 2148 /* Change permissions of pwm[1-3] if in manual mode */ 2149 for (ix = 0; ix < 3; ix++) { 2150 if ((data->has_features & HAS_PWM(ix)) && 2151 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { 2152 dme1737_chmod_file(dev, 2153 dme1737_pwm_chmod_attr[ix], 2154 S_IRUGO | S_IWUSR); 2155 } 2156 } 2157 } 2158 2159 return 0; 2160 2161exit_remove: 2162 dme1737_remove_files(dev); 2163exit: 2164 return err; 2165} 2166 2167static int dme1737_init_device(struct device *dev) 2168{ 2169 struct dme1737_data *data = dev_get_drvdata(dev); 2170 struct i2c_client *client = data->client; 2171 int ix; 2172 u8 reg; 2173 2174 /* Point to the right nominal voltages array */ 2175 data->in_nominal = IN_NOMINAL(data->type); 2176 2177 data->config = dme1737_read(data, DME1737_REG_CONFIG); 2178 /* Inform if part is not monitoring/started */ 2179 if (!(data->config & 0x01)) { 2180 if (!force_start) { 2181 dev_err(dev, "Device is not monitoring. " 2182 "Use the force_start load parameter to " 2183 "override.\n"); 2184 return -EFAULT; 2185 } 2186 2187 /* Force monitoring */ 2188 data->config |= 0x01; 2189 dme1737_write(data, DME1737_REG_CONFIG, data->config); 2190 } 2191 /* Inform if part is not ready */ 2192 if (!(data->config & 0x04)) { 2193 dev_err(dev, "Device is not ready.\n"); 2194 return -EFAULT; 2195 } 2196 2197 /* Determine which optional fan and pwm features are enabled (only 2198 * valid for I2C devices) */ 2199 if (client) { /* I2C chip */ 2200 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2); 2201 /* Check if optional fan3 input is enabled */ 2202 if (data->config2 & 0x04) { 2203 data->has_features |= HAS_FAN(2); 2204 } 2205 2206 /* Fan4 and pwm3 are only available if the client's I2C address 2207 * is the default 0x2e. Otherwise the I/Os associated with 2208 * these functions are used for addr enable/select. */ 2209 if (client->addr == 0x2e) { 2210 data->has_features |= HAS_FAN(3) | HAS_PWM(2); 2211 } 2212 2213 /* Determine which of the optional fan[5-6] and pwm[5-6] 2214 * features are enabled. For this, we need to query the runtime 2215 * registers through the Super-IO LPC interface. Try both 2216 * config ports 0x2e and 0x4e. */ 2217 if (dme1737_i2c_get_features(0x2e, data) && 2218 dme1737_i2c_get_features(0x4e, data)) { 2219 dev_warn(dev, "Failed to query Super-IO for optional " 2220 "features.\n"); 2221 } 2222 } 2223 2224 /* Fan[1-2] and pwm[1-2] are present in all chips */ 2225 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1); 2226 2227 /* Chip-dependent features */ 2228 switch (data->type) { 2229 case dme1737: 2230 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 | 2231 HAS_ZONE_HYST | HAS_PWM_MIN; 2232 break; 2233 case sch311x: 2234 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 | 2235 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2); 2236 break; 2237 case sch5027: 2238 data->has_features |= HAS_ZONE3; 2239 break; 2240 case sch5127: 2241 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7; 2242 break; 2243 default: 2244 break; 2245 } 2246 2247 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, " 2248 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n", 2249 (data->has_features & HAS_PWM(2)) ? "yes" : "no", 2250 (data->has_features & HAS_PWM(4)) ? "yes" : "no", 2251 (data->has_features & HAS_PWM(5)) ? "yes" : "no", 2252 (data->has_features & HAS_FAN(2)) ? "yes" : "no", 2253 (data->has_features & HAS_FAN(3)) ? "yes" : "no", 2254 (data->has_features & HAS_FAN(4)) ? "yes" : "no", 2255 (data->has_features & HAS_FAN(5)) ? "yes" : "no"); 2256 2257 reg = dme1737_read(data, DME1737_REG_TACH_PWM); 2258 /* Inform if fan-to-pwm mapping differs from the default */ 2259 if (client && reg != 0xa4) { /* I2C chip */ 2260 dev_warn(dev, "Non-standard fan to pwm mapping: " 2261 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, " 2262 "fan4->pwm%d. Please report to the driver " 2263 "maintainer.\n", 2264 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2265 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1); 2266 } else if (!client && reg != 0x24) { /* ISA chip */ 2267 dev_warn(dev, "Non-standard fan to pwm mapping: " 2268 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. " 2269 "Please report to the driver maintainer.\n", 2270 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2271 ((reg >> 4) & 0x03) + 1); 2272 } 2273 2274 /* Switch pwm[1-3] to manual mode if they are currently disabled and 2275 * set the duty-cycles to 0% (which is identical to the PWMs being 2276 * disabled). */ 2277 if (!(data->config & 0x02)) { 2278 for (ix = 0; ix < 3; ix++) { 2279 data->pwm_config[ix] = dme1737_read(data, 2280 DME1737_REG_PWM_CONFIG(ix)); 2281 if ((data->has_features & HAS_PWM(ix)) && 2282 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) { 2283 dev_info(dev, "Switching pwm%d to " 2284 "manual mode.\n", ix + 1); 2285 data->pwm_config[ix] = PWM_EN_TO_REG(1, 2286 data->pwm_config[ix]); 2287 dme1737_write(data, DME1737_REG_PWM(ix), 0); 2288 dme1737_write(data, 2289 DME1737_REG_PWM_CONFIG(ix), 2290 data->pwm_config[ix]); 2291 } 2292 } 2293 } 2294 2295 /* Initialize the default PWM auto channels zone (acz) assignments */ 2296 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */ 2297 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */ 2298 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ 2299 2300 /* Set VRM */ 2301 if (data->has_features & HAS_VID) { 2302 data->vrm = vid_which_vrm(); 2303 } 2304 2305 return 0; 2306} 2307 2308/* --------------------------------------------------------------------- 2309 * I2C device detection and registration 2310 * --------------------------------------------------------------------- */ 2311 2312static struct i2c_driver dme1737_i2c_driver; 2313 2314static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) 2315{ 2316 int err = 0, reg; 2317 u16 addr; 2318 2319 dme1737_sio_enter(sio_cip); 2320 2321 /* Check device ID 2322 * We currently know about two kinds of DME1737 and SCH5027. */ 2323 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2324 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 || 2325 reg == SCH5027_ID)) { 2326 err = -ENODEV; 2327 goto exit; 2328 } 2329 2330 /* Select logical device A (runtime registers) */ 2331 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2332 2333 /* Get the base address of the runtime registers */ 2334 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2335 dme1737_sio_inb(sio_cip, 0x61); 2336 if (!addr) { 2337 err = -ENODEV; 2338 goto exit; 2339 } 2340 2341 /* Read the runtime registers to determine which optional features 2342 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set 2343 * to '10' if the respective feature is enabled. */ 2344 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */ 2345 data->has_features |= HAS_FAN(5); 2346 } 2347 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */ 2348 data->has_features |= HAS_PWM(5); 2349 } 2350 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */ 2351 data->has_features |= HAS_FAN(4); 2352 } 2353 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */ 2354 data->has_features |= HAS_PWM(4); 2355 } 2356 2357exit: 2358 dme1737_sio_exit(sio_cip); 2359 2360 return err; 2361} 2362 2363/* Return 0 if detection is successful, -ENODEV otherwise */ 2364static int dme1737_i2c_detect(struct i2c_client *client, 2365 struct i2c_board_info *info) 2366{ 2367 struct i2c_adapter *adapter = client->adapter; 2368 struct device *dev = &adapter->dev; 2369 u8 company, verstep = 0; 2370 const char *name; 2371 2372 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 2373 return -ENODEV; 2374 } 2375 2376 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY); 2377 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP); 2378 2379 if (company == DME1737_COMPANY_SMSC && 2380 verstep == SCH5027_VERSTEP) { 2381 name = "sch5027"; 2382 } else if (company == DME1737_COMPANY_SMSC && 2383 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { 2384 name = "dme1737"; 2385 } else { 2386 return -ENODEV; 2387 } 2388 2389 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", 2390 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737", 2391 client->addr, verstep); 2392 strlcpy(info->type, name, I2C_NAME_SIZE); 2393 2394 return 0; 2395} 2396 2397static int dme1737_i2c_probe(struct i2c_client *client, 2398 const struct i2c_device_id *id) 2399{ 2400 struct dme1737_data *data; 2401 struct device *dev = &client->dev; 2402 int err; 2403 2404 data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL); 2405 if (!data) { 2406 err = -ENOMEM; 2407 goto exit; 2408 } 2409 2410 i2c_set_clientdata(client, data); 2411 data->type = id->driver_data; 2412 data->client = client; 2413 data->name = client->name; 2414 mutex_init(&data->update_lock); 2415 2416 /* Initialize the DME1737 chip */ 2417 err = dme1737_init_device(dev); 2418 if (err) { 2419 dev_err(dev, "Failed to initialize device.\n"); 2420 goto exit_kfree; 2421 } 2422 2423 /* Create sysfs files */ 2424 err = dme1737_create_files(dev); 2425 if (err) { 2426 dev_err(dev, "Failed to create sysfs files.\n"); 2427 goto exit_kfree; 2428 } 2429 2430 /* Register device */ 2431 data->hwmon_dev = hwmon_device_register(dev); 2432 if (IS_ERR(data->hwmon_dev)) { 2433 dev_err(dev, "Failed to register device.\n"); 2434 err = PTR_ERR(data->hwmon_dev); 2435 goto exit_remove; 2436 } 2437 2438 return 0; 2439 2440exit_remove: 2441 dme1737_remove_files(dev); 2442exit_kfree: 2443 kfree(data); 2444exit: 2445 return err; 2446} 2447 2448static int dme1737_i2c_remove(struct i2c_client *client) 2449{ 2450 struct dme1737_data *data = i2c_get_clientdata(client); 2451 2452 hwmon_device_unregister(data->hwmon_dev); 2453 dme1737_remove_files(&client->dev); 2454 2455 kfree(data); 2456 return 0; 2457} 2458 2459static const struct i2c_device_id dme1737_id[] = { 2460 { "dme1737", dme1737 }, 2461 { "sch5027", sch5027 }, 2462 { } 2463}; 2464MODULE_DEVICE_TABLE(i2c, dme1737_id); 2465 2466static struct i2c_driver dme1737_i2c_driver = { 2467 .class = I2C_CLASS_HWMON, 2468 .driver = { 2469 .name = "dme1737", 2470 }, 2471 .probe = dme1737_i2c_probe, 2472 .remove = dme1737_i2c_remove, 2473 .id_table = dme1737_id, 2474 .detect = dme1737_i2c_detect, 2475 .address_list = normal_i2c, 2476}; 2477 2478/* --------------------------------------------------------------------- 2479 * ISA device detection and registration 2480 * --------------------------------------------------------------------- */ 2481 2482static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr) 2483{ 2484 int err = 0, reg; 2485 unsigned short base_addr; 2486 2487 dme1737_sio_enter(sio_cip); 2488 2489 /* Check device ID 2490 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 */ 2491 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2492 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID || 2493 reg == SCH5127_ID)) { 2494 err = -ENODEV; 2495 goto exit; 2496 } 2497 2498 /* Select logical device A (runtime registers) */ 2499 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2500 2501 /* Get the base address of the runtime registers */ 2502 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2503 dme1737_sio_inb(sio_cip, 0x61); 2504 if (!base_addr) { 2505 pr_err("Base address not set\n"); 2506 err = -ENODEV; 2507 goto exit; 2508 } 2509 2510 /* Access to the hwmon registers is through an index/data register 2511 * pair located at offset 0x70/0x71. */ 2512 *addr = base_addr + 0x70; 2513 2514exit: 2515 dme1737_sio_exit(sio_cip); 2516 return err; 2517} 2518 2519static int __init dme1737_isa_device_add(unsigned short addr) 2520{ 2521 struct resource res = { 2522 .start = addr, 2523 .end = addr + DME1737_EXTENT - 1, 2524 .name = "dme1737", 2525 .flags = IORESOURCE_IO, 2526 }; 2527 int err; 2528 2529 err = acpi_check_resource_conflict(&res); 2530 if (err) 2531 goto exit; 2532 2533 pdev = platform_device_alloc("dme1737", addr); 2534 if (!pdev) { 2535 pr_err("Failed to allocate device\n"); 2536 err = -ENOMEM; 2537 goto exit; 2538 } 2539 2540 err = platform_device_add_resources(pdev, &res, 1); 2541 if (err) { 2542 pr_err("Failed to add device resource (err = %d)\n", err); 2543 goto exit_device_put; 2544 } 2545 2546 err = platform_device_add(pdev); 2547 if (err) { 2548 pr_err("Failed to add device (err = %d)\n", err); 2549 goto exit_device_put; 2550 } 2551 2552 return 0; 2553 2554exit_device_put: 2555 platform_device_put(pdev); 2556 pdev = NULL; 2557exit: 2558 return err; 2559} 2560 2561static int __devinit dme1737_isa_probe(struct platform_device *pdev) 2562{ 2563 u8 company, device; 2564 struct resource *res; 2565 struct dme1737_data *data; 2566 struct device *dev = &pdev->dev; 2567 int err; 2568 2569 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 2570 if (!request_region(res->start, DME1737_EXTENT, "dme1737")) { 2571 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n", 2572 (unsigned short)res->start, 2573 (unsigned short)res->start + DME1737_EXTENT - 1); 2574 err = -EBUSY; 2575 goto exit; 2576 } 2577 2578 data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL); 2579 if (!data) { 2580 err = -ENOMEM; 2581 goto exit_release_region; 2582 } 2583 2584 data->addr = res->start; 2585 platform_set_drvdata(pdev, data); 2586 2587 /* Skip chip detection if module is loaded with force_id parameter */ 2588 switch (force_id) { 2589 case SCH3112_ID: 2590 case SCH3114_ID: 2591 case SCH3116_ID: 2592 data->type = sch311x; 2593 break; 2594 case SCH5127_ID: 2595 data->type = sch5127; 2596 break; 2597 default: 2598 company = dme1737_read(data, DME1737_REG_COMPANY); 2599 device = dme1737_read(data, DME1737_REG_DEVICE); 2600 2601 if ((company == DME1737_COMPANY_SMSC) && 2602 (device == SCH311X_DEVICE)) { 2603 data->type = sch311x; 2604 } else if ((company == DME1737_COMPANY_SMSC) && 2605 (device == SCH5127_DEVICE)) { 2606 data->type = sch5127; 2607 } else { 2608 err = -ENODEV; 2609 goto exit_kfree; 2610 } 2611 } 2612 2613 if (data->type == sch5127) { 2614 data->name = "sch5127"; 2615 } else { 2616 data->name = "sch311x"; 2617 } 2618 2619 /* Initialize the mutex */ 2620 mutex_init(&data->update_lock); 2621 2622 dev_info(dev, "Found a %s chip at 0x%04x\n", 2623 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr); 2624 2625 /* Initialize the chip */ 2626 err = dme1737_init_device(dev); 2627 if (err) { 2628 dev_err(dev, "Failed to initialize device.\n"); 2629 goto exit_kfree; 2630 } 2631 2632 /* Create sysfs files */ 2633 err = dme1737_create_files(dev); 2634 if (err) { 2635 dev_err(dev, "Failed to create sysfs files.\n"); 2636 goto exit_kfree; 2637 } 2638 2639 /* Register device */ 2640 data->hwmon_dev = hwmon_device_register(dev); 2641 if (IS_ERR(data->hwmon_dev)) { 2642 dev_err(dev, "Failed to register device.\n"); 2643 err = PTR_ERR(data->hwmon_dev); 2644 goto exit_remove_files; 2645 } 2646 2647 return 0; 2648 2649exit_remove_files: 2650 dme1737_remove_files(dev); 2651exit_kfree: 2652 platform_set_drvdata(pdev, NULL); 2653 kfree(data); 2654exit_release_region: 2655 release_region(res->start, DME1737_EXTENT); 2656exit: 2657 return err; 2658} 2659 2660static int __devexit dme1737_isa_remove(struct platform_device *pdev) 2661{ 2662 struct dme1737_data *data = platform_get_drvdata(pdev); 2663 2664 hwmon_device_unregister(data->hwmon_dev); 2665 dme1737_remove_files(&pdev->dev); 2666 release_region(data->addr, DME1737_EXTENT); 2667 platform_set_drvdata(pdev, NULL); 2668 kfree(data); 2669 2670 return 0; 2671} 2672 2673static struct platform_driver dme1737_isa_driver = { 2674 .driver = { 2675 .owner = THIS_MODULE, 2676 .name = "dme1737", 2677 }, 2678 .probe = dme1737_isa_probe, 2679 .remove = __devexit_p(dme1737_isa_remove), 2680}; 2681 2682/* --------------------------------------------------------------------- 2683 * Module initialization and cleanup 2684 * --------------------------------------------------------------------- */ 2685 2686static int __init dme1737_init(void) 2687{ 2688 int err; 2689 unsigned short addr; 2690 2691 err = i2c_add_driver(&dme1737_i2c_driver); 2692 if (err) { 2693 goto exit; 2694 } 2695 2696 if (dme1737_isa_detect(0x2e, &addr) && 2697 dme1737_isa_detect(0x4e, &addr) && 2698 (!probe_all_addr || 2699 (dme1737_isa_detect(0x162e, &addr) && 2700 dme1737_isa_detect(0x164e, &addr)))) { 2701 /* Return 0 if we didn't find an ISA device */ 2702 return 0; 2703 } 2704 2705 err = platform_driver_register(&dme1737_isa_driver); 2706 if (err) { 2707 goto exit_del_i2c_driver; 2708 } 2709 2710 /* Sets global pdev as a side effect */ 2711 err = dme1737_isa_device_add(addr); 2712 if (err) { 2713 goto exit_del_isa_driver; 2714 } 2715 2716 return 0; 2717 2718exit_del_isa_driver: 2719 platform_driver_unregister(&dme1737_isa_driver); 2720exit_del_i2c_driver: 2721 i2c_del_driver(&dme1737_i2c_driver); 2722exit: 2723 return err; 2724} 2725 2726static void __exit dme1737_exit(void) 2727{ 2728 if (pdev) { 2729 platform_device_unregister(pdev); 2730 platform_driver_unregister(&dme1737_isa_driver); 2731 } 2732 2733 i2c_del_driver(&dme1737_i2c_driver); 2734} 2735 2736MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>"); 2737MODULE_DESCRIPTION("DME1737 sensors"); 2738MODULE_LICENSE("GPL"); 2739 2740module_init(dme1737_init); 2741module_exit(dme1737_exit); 2742