pdc202xx_old.c revision d614aec4752f8c61b2e7cb77806b6bd59aa50836
1/* 2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. 4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 5 * 6 * Portions Copyright (C) 1999 Promise Technology, Inc. 7 * Author: Frank Tiernan (frankt@promise.com) 8 * Released under terms of General Public License 9 */ 10 11#include <linux/types.h> 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/delay.h> 15#include <linux/blkdev.h> 16#include <linux/pci.h> 17#include <linux/init.h> 18#include <linux/ide.h> 19 20#include <asm/io.h> 21 22#define DRV_NAME "pdc202xx_old" 23 24#define PDC202XX_DEBUG_DRIVE_INFO 0 25 26static void pdc_old_disable_66MHz_clock(ide_hwif_t *); 27 28static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) 29{ 30 ide_hwif_t *hwif = drive->hwif; 31 struct pci_dev *dev = to_pci_dev(hwif->dev); 32 u8 drive_pci = 0x60 + (drive->dn << 2); 33 34 u8 AP = 0, BP = 0, CP = 0; 35 u8 TA = 0, TB = 0, TC = 0; 36 37#if PDC202XX_DEBUG_DRIVE_INFO 38 u32 drive_conf = 0; 39 pci_read_config_dword(dev, drive_pci, &drive_conf); 40#endif 41 42 /* 43 * TODO: do this once per channel 44 */ 45 if (dev->device != PCI_DEVICE_ID_PROMISE_20246) 46 pdc_old_disable_66MHz_clock(hwif); 47 48 pci_read_config_byte(dev, drive_pci, &AP); 49 pci_read_config_byte(dev, drive_pci + 1, &BP); 50 pci_read_config_byte(dev, drive_pci + 2, &CP); 51 52 switch(speed) { 53 case XFER_UDMA_5: 54 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; 55 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; 56 case XFER_UDMA_3: 57 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; 58 case XFER_UDMA_0: 59 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; 60 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; 61 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; 62 case XFER_PIO_4: TA = 0x01; TB = 0x04; break; 63 case XFER_PIO_3: TA = 0x02; TB = 0x06; break; 64 case XFER_PIO_2: TA = 0x03; TB = 0x08; break; 65 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; 66 case XFER_PIO_0: 67 default: TA = 0x09; TB = 0x13; break; 68 } 69 70 if (speed < XFER_SW_DMA_0) { 71 /* 72 * preserve SYNC_INT / ERDDY_EN bits while clearing 73 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A 74 */ 75 AP &= ~0x3f; 76 if (ata_id_iordy_disable(drive->id)) 77 AP |= 0x20; /* set IORDY_EN bit */ 78 if (drive->media == ide_disk) 79 AP |= 0x10; /* set Prefetch_EN bit */ 80 /* clear PB[4:0] bits of register B */ 81 BP &= ~0x1f; 82 pci_write_config_byte(dev, drive_pci, AP | TA); 83 pci_write_config_byte(dev, drive_pci + 1, BP | TB); 84 } else { 85 /* clear MB[2:0] bits of register B */ 86 BP &= ~0xe0; 87 /* clear MC[3:0] bits of register C */ 88 CP &= ~0x0f; 89 pci_write_config_byte(dev, drive_pci + 1, BP | TB); 90 pci_write_config_byte(dev, drive_pci + 2, CP | TC); 91 } 92 93#if PDC202XX_DEBUG_DRIVE_INFO 94 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ", 95 drive->name, ide_xfer_verbose(speed), 96 drive->dn, drive_conf); 97 pci_read_config_dword(dev, drive_pci, &drive_conf); 98 printk("0x%08x\n", drive_conf); 99#endif 100} 101 102static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 103{ 104 pdc202xx_set_mode(drive, XFER_PIO_0 + pio); 105} 106 107static u8 pdc2026x_cable_detect(ide_hwif_t *hwif) 108{ 109 struct pci_dev *dev = to_pci_dev(hwif->dev); 110 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10); 111 112 pci_read_config_word(dev, 0x50, &CIS); 113 114 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 115} 116 117/* 118 * Set the control register to use the 66MHz system 119 * clock for UDMA 3/4/5 mode operation when necessary. 120 * 121 * FIXME: this register is shared by both channels, some locking is needed 122 * 123 * It may also be possible to leave the 66MHz clock on 124 * and readjust the timing parameters. 125 */ 126static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) 127{ 128 unsigned long clock_reg = hwif->extra_base + 0x01; 129 u8 clock = inb(clock_reg); 130 131 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); 132} 133 134static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) 135{ 136 unsigned long clock_reg = hwif->extra_base + 0x01; 137 u8 clock = inb(clock_reg); 138 139 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 140} 141 142static void pdc202xx_dma_start(ide_drive_t *drive) 143{ 144 if (drive->current_speed > XFER_UDMA_2) 145 pdc_old_enable_66MHz_clock(drive->hwif); 146 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { 147 ide_hwif_t *hwif = drive->hwif; 148 struct request *rq = hwif->rq; 149 unsigned long high_16 = hwif->extra_base - 16; 150 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 151 u32 word_count = 0; 152 u8 clock = inb(high_16 + 0x11); 153 154 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); 155 word_count = (blk_rq_sectors(rq) << 8); 156 word_count = (rq_data_dir(rq) == READ) ? 157 word_count | 0x05000000 : 158 word_count | 0x06000000; 159 outl(word_count, atapi_reg); 160 } 161 ide_dma_start(drive); 162} 163 164static int pdc202xx_dma_end(ide_drive_t *drive) 165{ 166 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { 167 ide_hwif_t *hwif = drive->hwif; 168 unsigned long high_16 = hwif->extra_base - 16; 169 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 170 u8 clock = 0; 171 172 outl(0, atapi_reg); /* zero out extra */ 173 clock = inb(high_16 + 0x11); 174 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); 175 } 176 if (drive->current_speed > XFER_UDMA_2) 177 pdc_old_disable_66MHz_clock(drive->hwif); 178 return ide_dma_end(drive); 179} 180 181static int init_chipset_pdc202xx(struct pci_dev *dev) 182{ 183 unsigned long dmabase = pci_resource_start(dev, 4); 184 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; 185 186 if (dmabase == 0) 187 goto out; 188 189 udma_speed_flag = inb(dmabase | 0x1f); 190 primary_mode = inb(dmabase | 0x1a); 191 secondary_mode = inb(dmabase | 0x1b); 192 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ 193 "Primary %s Mode " \ 194 "Secondary %s Mode.\n", pci_name(dev), 195 (udma_speed_flag & 1) ? "EN" : "DIS", 196 (primary_mode & 1) ? "MASTER" : "PCI", 197 (secondary_mode & 1) ? "MASTER" : "PCI" ); 198 199 if (!(udma_speed_flag & 1)) { 200 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", 201 pci_name(dev), udma_speed_flag, 202 (udma_speed_flag|1)); 203 outb(udma_speed_flag | 1, dmabase | 0x1f); 204 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); 205 } 206out: 207 return 0; 208} 209 210static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, 211 const char *name) 212{ 213 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { 214 u8 irq = 0, irq2 = 0; 215 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 216 /* 0xbc */ 217 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); 218 if (irq != irq2) { 219 pci_write_config_byte(dev, 220 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ 221 printk(KERN_INFO "%s %s: PCI config space interrupt " 222 "mirror fixed\n", name, pci_name(dev)); 223 } 224 } 225} 226 227#define IDE_HFLAGS_PDC202XX \ 228 (IDE_HFLAG_ERROR_STOPS_FIFO | \ 229 IDE_HFLAG_OFF_BOARD) 230 231static const struct ide_port_ops pdc20246_port_ops = { 232 .set_pio_mode = pdc202xx_set_pio_mode, 233 .set_dma_mode = pdc202xx_set_mode, 234}; 235 236static const struct ide_port_ops pdc2026x_port_ops = { 237 .set_pio_mode = pdc202xx_set_pio_mode, 238 .set_dma_mode = pdc202xx_set_mode, 239 .cable_detect = pdc2026x_cable_detect, 240}; 241 242static const struct ide_dma_ops pdc2026x_dma_ops = { 243 .dma_host_set = ide_dma_host_set, 244 .dma_setup = ide_dma_setup, 245 .dma_start = pdc202xx_dma_start, 246 .dma_end = pdc202xx_dma_end, 247 .dma_test_irq = ide_dma_test_irq, 248 .dma_lost_irq = ide_dma_lost_irq, 249 .dma_timer_expiry = ide_dma_sff_timer_expiry, 250 .dma_sff_read_status = ide_dma_sff_read_status, 251}; 252 253#define DECLARE_PDC2026X_DEV(udma, sectors) \ 254 { \ 255 .name = DRV_NAME, \ 256 .init_chipset = init_chipset_pdc202xx, \ 257 .port_ops = &pdc2026x_port_ops, \ 258 .dma_ops = &pdc2026x_dma_ops, \ 259 .host_flags = IDE_HFLAGS_PDC202XX, \ 260 .pio_mask = ATA_PIO4, \ 261 .mwdma_mask = ATA_MWDMA2, \ 262 .udma_mask = udma, \ 263 .max_sectors = sectors, \ 264 } 265 266static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = { 267 { /* 0: PDC20246 */ 268 .name = DRV_NAME, 269 .init_chipset = init_chipset_pdc202xx, 270 .port_ops = &pdc20246_port_ops, 271 .dma_ops = &sff_dma_ops, 272 .host_flags = IDE_HFLAGS_PDC202XX, 273 .pio_mask = ATA_PIO4, 274 .mwdma_mask = ATA_MWDMA2, 275 .udma_mask = ATA_UDMA2, 276 }, 277 278 /* 1: PDC2026{2,3} */ 279 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0), 280 /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */ 281 DECLARE_PDC2026X_DEV(ATA_UDMA5, 256), 282}; 283 284/** 285 * pdc202xx_init_one - called when a PDC202xx is found 286 * @dev: the pdc202xx device 287 * @id: the matching pci id 288 * 289 * Called when the PCI registration layer (or the IDE initialization) 290 * finds a device matching our IDE device tables. 291 */ 292 293static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 294{ 295 const struct ide_port_info *d; 296 u8 idx = id->driver_data; 297 298 d = &pdc202xx_chipsets[idx]; 299 300 if (idx < 2) 301 pdc202ata4_fixup_irq(dev, d->name); 302 303 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) { 304 struct pci_dev *bridge = dev->bus->self; 305 306 if (bridge && 307 bridge->vendor == PCI_VENDOR_ID_INTEL && 308 (bridge->device == PCI_DEVICE_ID_INTEL_I960 || 309 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { 310 printk(KERN_INFO DRV_NAME " %s: skipping Promise " 311 "PDC20265 attached to I2O RAID controller\n", 312 pci_name(dev)); 313 return -ENODEV; 314 } 315 } 316 317 return ide_pci_init_one(dev, d, NULL); 318} 319 320static const struct pci_device_id pdc202xx_pci_tbl[] = { 321 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, 322 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, 323 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, 324 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, 325 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, 326 { 0, }, 327}; 328MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); 329 330static struct pci_driver pdc202xx_pci_driver = { 331 .name = "Promise_Old_IDE", 332 .id_table = pdc202xx_pci_tbl, 333 .probe = pdc202xx_init_one, 334 .remove = ide_pci_remove, 335 .suspend = ide_pci_suspend, 336 .resume = ide_pci_resume, 337}; 338 339static int __init pdc202xx_ide_init(void) 340{ 341 return ide_pci_register_driver(&pdc202xx_pci_driver); 342} 343 344static void __exit pdc202xx_ide_exit(void) 345{ 346 pci_unregister_driver(&pdc202xx_pci_driver); 347} 348 349module_init(pdc202xx_ide_init); 350module_exit(pdc202xx_ide_exit); 351 352MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); 353MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); 354MODULE_LICENSE("GPL"); 355