s5h1411.c revision 6d8976164dd7d10d25fe940b8546265f60ad52cd 
1/*
2    Samsung S5H1411 VSB/QAM demodulator driver
3
4    Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
5
6    This program is free software; you can redistribute it and/or modify
7    it under the terms of the GNU General Public License as published by
8    the Free Software Foundation; either version 2 of the License, or
9    (at your option) any later version.
10
11    This program is distributed in the hope that it will be useful,
12    but WITHOUT ANY WARRANTY; without even the implied warranty of
13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14    GNU General Public License for more details.
15
16    You should have received a copy of the GNU General Public License
17    along with this program; if not, write to the Free Software
18    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20*/
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include "dvb_frontend.h"
29#include "s5h1411.h"
30
31struct s5h1411_state {
32
33	struct i2c_adapter *i2c;
34
35	/* configuration settings */
36	const struct s5h1411_config *config;
37
38	struct dvb_frontend frontend;
39
40	fe_modulation_t current_modulation;
41
42	u32 current_frequency;
43	int if_freq;
44
45	u8 inversion;
46};
47
48static int debug;
49
50#define dprintk(arg...) do {	\
51	if (debug)		\
52		printk(arg);	\
53	} while (0)
54
55/* Register values to initialise the demod, defaults to VSB */
56static struct init_tab {
57	u8	addr;
58	u8	reg;
59	u16	data;
60} init_tab[] = {
61	{ S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
62	{ S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
63	{ S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
64	{ S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
65	{ S5H1411_I2C_TOP_ADDR, 0x1f, 0x342a, },
66	{ S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
67	{ S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
68	{ S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
69	{ S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
70	{ S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
71	{ S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
72	{ S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
73	{ S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
74	{ S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
75	{ S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
76	{ S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
77	{ S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
78	{ S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
79	{ S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
80	{ S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
81	{ S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
82	{ S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
83	{ S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
84	{ S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
85	{ S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
86	{ S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
87	{ S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
88	{ S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
89	{ S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
90	{ S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
91	{ S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
92	{ S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
93	{ S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
94	{ S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
95	{ S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
96	{ S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
97	{ S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
98	{ S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
99	{ S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
100	{ S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
101	{ S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
102	{ S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
103	{ S5H1411_I2C_TOP_ADDR, 0xb5, 0xafbb, },
104	{ S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
105	{ S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
106	{ S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
107	{ S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
108	{ S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
109	{ S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
110	{ S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
111	{ S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
112	{ S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
113	{ S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
114	{ S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
115	{ S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
116	{ S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
117	{ S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
118	{ S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
119	{ S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
120	{ S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
121	{ S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
122	{ S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
123	{ S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
124	{ S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
125	{ S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
126	{ S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
127	{ S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
128	{ S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
129	{ S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
130	{ S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
131	{ S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
132	{ S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
133	{ S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
134	{ S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
135	{ S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
136	{ S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
137	{ S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
138	{ S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
139	{ S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
140	{ S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
141	{ S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
142};
143
144/* VSB SNR lookup table */
145static struct vsb_snr_tab {
146	u16	val;
147	u16	data;
148} vsb_snr_tab[] = {
149	{  0x39f, 300, },
150	{  0x39b, 295, },
151	{  0x397, 290, },
152	{  0x394, 285, },
153	{  0x38f, 280, },
154	{  0x38b, 275, },
155	{  0x387, 270, },
156	{  0x382, 265, },
157	{  0x37d, 260, },
158	{  0x377, 255, },
159	{  0x370, 250, },
160	{  0x36a, 245, },
161	{  0x364, 240, },
162	{  0x35b, 235, },
163	{  0x353, 230, },
164	{  0x349, 225, },
165	{  0x340, 320, },
166	{  0x337, 215, },
167	{  0x327, 210, },
168	{  0x31b, 205, },
169	{  0x310, 200, },
170	{  0x302, 195, },
171	{  0x2f3, 190, },
172	{  0x2e4, 185, },
173	{  0x2d7, 180, },
174	{  0x2cd, 175, },
175	{  0x2bb, 170, },
176	{  0x2a9, 165, },
177	{  0x29e, 160, },
178	{  0x284, 155, },
179	{  0x27a, 150, },
180	{  0x260, 145, },
181	{  0x23a, 140, },
182	{  0x224, 135, },
183	{  0x213, 130, },
184	{  0x204, 125, },
185	{  0x1fe, 120, },
186	{      0,   0, },
187};
188
189/* QAM64 SNR lookup table */
190static struct qam64_snr_tab {
191	u16	val;
192	u16	data;
193} qam64_snr_tab[] = {
194	{  0x0001,   0, },
195	{  0x0af0, 300, },
196	{  0x0d80, 290, },
197	{  0x10a0, 280, },
198	{  0x14b5, 270, },
199	{  0x1590, 268, },
200	{  0x1680, 266, },
201	{  0x17b0, 264, },
202	{  0x18c0, 262, },
203	{  0x19b0, 260, },
204	{  0x1ad0, 258, },
205	{  0x1d00, 256, },
206	{  0x1da0, 254, },
207	{  0x1ef0, 252, },
208	{  0x2050, 250, },
209	{  0x20f0, 249, },
210	{  0x21d0, 248, },
211	{  0x22b0, 247, },
212	{  0x23a0, 246, },
213	{  0x2470, 245, },
214	{  0x24f0, 244, },
215	{  0x25a0, 243, },
216	{  0x26c0, 242, },
217	{  0x27b0, 241, },
218	{  0x28d0, 240, },
219	{  0x29b0, 239, },
220	{  0x2ad0, 238, },
221	{  0x2ba0, 237, },
222	{  0x2c80, 236, },
223	{  0x2d20, 235, },
224	{  0x2e00, 234, },
225	{  0x2f10, 233, },
226	{  0x3050, 232, },
227	{  0x3190, 231, },
228	{  0x3300, 230, },
229	{  0x3340, 229, },
230	{  0x3200, 228, },
231	{  0x3550, 227, },
232	{  0x3610, 226, },
233	{  0x3600, 225, },
234	{  0x3700, 224, },
235	{  0x3800, 223, },
236	{  0x3920, 222, },
237	{  0x3a20, 221, },
238	{  0x3b30, 220, },
239	{  0x3d00, 219, },
240	{  0x3e00, 218, },
241	{  0x4000, 217, },
242	{  0x4100, 216, },
243	{  0x4300, 215, },
244	{  0x4400, 214, },
245	{  0x4600, 213, },
246	{  0x4700, 212, },
247	{  0x4800, 211, },
248	{  0x4a00, 210, },
249	{  0x4b00, 209, },
250	{  0x4d00, 208, },
251	{  0x4f00, 207, },
252	{  0x5050, 206, },
253	{  0x5200, 205, },
254	{  0x53c0, 204, },
255	{  0x5450, 203, },
256	{  0x5650, 202, },
257	{  0x5820, 201, },
258	{  0x6000, 200, },
259	{  0xffff,   0, },
260};
261
262/* QAM256 SNR lookup table */
263static struct qam256_snr_tab {
264	u16	val;
265	u16	data;
266} qam256_snr_tab[] = {
267	{  0x0001,   0, },
268	{  0x0970, 400, },
269	{  0x0a90, 390, },
270	{  0x0b90, 380, },
271	{  0x0d90, 370, },
272	{  0x0ff0, 360, },
273	{  0x1240, 350, },
274	{  0x1345, 348, },
275	{  0x13c0, 346, },
276	{  0x14c0, 344, },
277	{  0x1500, 342, },
278	{  0x1610, 340, },
279	{  0x1700, 338, },
280	{  0x1800, 336, },
281	{  0x18b0, 334, },
282	{  0x1900, 332, },
283	{  0x1ab0, 330, },
284	{  0x1bc0, 328, },
285	{  0x1cb0, 326, },
286	{  0x1db0, 324, },
287	{  0x1eb0, 322, },
288	{  0x2030, 320, },
289	{  0x2200, 318, },
290	{  0x2280, 316, },
291	{  0x2410, 314, },
292	{  0x25b0, 312, },
293	{  0x27a0, 310, },
294	{  0x2840, 308, },
295	{  0x29d0, 306, },
296	{  0x2b10, 304, },
297	{  0x2d30, 302, },
298	{  0x2f20, 300, },
299	{  0x30c0, 298, },
300	{  0x3260, 297, },
301	{  0x32c0, 296, },
302	{  0x3300, 295, },
303	{  0x33b0, 294, },
304	{  0x34b0, 293, },
305	{  0x35a0, 292, },
306	{  0x3650, 291, },
307	{  0x3800, 290, },
308	{  0x3900, 289, },
309	{  0x3a50, 288, },
310	{  0x3b30, 287, },
311	{  0x3cb0, 286, },
312	{  0x3e20, 285, },
313	{  0x3fa0, 284, },
314	{  0x40a0, 283, },
315	{  0x41c0, 282, },
316	{  0x42f0, 281, },
317	{  0x44a0, 280, },
318	{  0x4600, 279, },
319	{  0x47b0, 278, },
320	{  0x4900, 277, },
321	{  0x4a00, 276, },
322	{  0x4ba0, 275, },
323	{  0x4d00, 274, },
324	{  0x4f00, 273, },
325	{  0x5000, 272, },
326	{  0x51f0, 272, },
327	{  0x53a0, 270, },
328	{  0x5520, 269, },
329	{  0x5700, 268, },
330	{  0x5800, 267, },
331	{  0x5a00, 266, },
332	{  0x5c00, 265, },
333	{  0x5d00, 264, },
334	{  0x5f00, 263, },
335	{  0x6000, 262, },
336	{  0x6200, 261, },
337	{  0x6400, 260, },
338	{  0xffff,   0, },
339};
340
341/* 8 bit registers, 16 bit values */
342static int s5h1411_writereg(struct s5h1411_state *state,
343	u8 addr, u8 reg, u16 data)
344{
345	int ret;
346	u8 buf [] = { reg, data >> 8,  data & 0xff };
347
348	struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
349
350	ret = i2c_transfer(state->i2c, &msg, 1);
351
352	if (ret != 1)
353		printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
354		       "ret == %i)\n", __func__, addr, reg, data, ret);
355
356	return (ret != 1) ? -1 : 0;
357}
358
359static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
360{
361	int ret;
362	u8 b0 [] = { reg };
363	u8 b1 [] = { 0, 0 };
364
365	struct i2c_msg msg [] = {
366		{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },
367		{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } };
368
369	ret = i2c_transfer(state->i2c, msg, 2);
370
371	if (ret != 2)
372		printk(KERN_ERR "%s: readreg error (ret == %i)\n",
373			__func__, ret);
374	return (b1[0] << 8) | b1[1];
375}
376
377static int s5h1411_softreset(struct dvb_frontend *fe)
378{
379	struct s5h1411_state *state = fe->demodulator_priv;
380
381	dprintk("%s()\n", __func__);
382
383	s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
384	s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
385	return 0;
386}
387
388static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
389{
390	struct s5h1411_state *state = fe->demodulator_priv;
391
392	dprintk("%s(%d KHz)\n", __func__, KHz);
393
394	switch (KHz) {
395	case 3250:
396		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d9);
397		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
398		s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
399		break;
400	case 3500:
401		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
402		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
403		s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
404		break;
405	case 4000:
406		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
407		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
408		s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
409		break;
410	default:
411		dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
412			__func__, KHz);
413		/* no break, need to continue */
414	case 5380:
415	case 44000:
416		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
417		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
418		s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
419		break;
420	}
421
422	state->if_freq = KHz;
423
424	return 0;
425}
426
427static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
428{
429	struct s5h1411_state *state = fe->demodulator_priv;
430	u16 val;
431
432	dprintk("%s(%d)\n", __func__, mode);
433
434	val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
435	switch (mode) {
436	case S5H1411_MPEGTIMING_CONTINOUS_INVERTING_CLOCK:
437		val |= 0x0000;
438		break;
439	case S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK:
440		dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
441		val |= 0x1000;
442		break;
443	case S5H1411_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK:
444		val |= 0x2000;
445		break;
446	case S5H1411_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK:
447		val |= 0x3000;
448		break;
449	default:
450		return -EINVAL;
451	}
452
453	/* Configure MPEG Signal Timing charactistics */
454	return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
455}
456
457static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
458{
459	struct s5h1411_state *state = fe->demodulator_priv;
460	u16 val;
461
462	dprintk("%s(%d)\n", __func__, inversion);
463	val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
464
465	if (inversion == 1)
466		val |= 0x1000; /* Inverted */
467	else
468		val |= 0x0000;
469
470	state->inversion = inversion;
471	return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
472}
473
474static int s5h1411_enable_modulation(struct dvb_frontend *fe,
475				     fe_modulation_t m)
476{
477	struct s5h1411_state *state = fe->demodulator_priv;
478
479	dprintk("%s(0x%08x)\n", __func__, m);
480
481	switch (m) {
482	case VSB_8:
483		dprintk("%s() VSB_8\n", __func__);
484		s5h1411_set_if_freq(fe, state->config->vsb_if);
485		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
486		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
487		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
488		break;
489	case QAM_64:
490	case QAM_256:
491	case QAM_AUTO:
492		dprintk("%s() QAM_AUTO (64/256)\n", __func__);
493		s5h1411_set_if_freq(fe, state->config->qam_if);
494		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
495		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
496		s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
497		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
498		break;
499	default:
500		dprintk("%s() Invalid modulation\n", __func__);
501		return -EINVAL;
502	}
503
504	state->current_modulation = m;
505	s5h1411_softreset(fe);
506
507	return 0;
508}
509
510static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
511{
512	struct s5h1411_state *state = fe->demodulator_priv;
513
514	dprintk("%s(%d)\n", __func__, enable);
515
516	if (enable)
517		return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
518	else
519		return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
520}
521
522static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
523{
524	struct s5h1411_state *state = fe->demodulator_priv;
525	u16 val;
526
527	dprintk("%s(%d)\n", __func__, enable);
528
529	val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
530
531	if (enable)
532		return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
533				val | 0x02);
534	else
535		return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
536}
537
538static int s5h1411_sleep(struct dvb_frontend *fe, int enable)
539{
540	struct s5h1411_state *state = fe->demodulator_priv;
541
542	dprintk("%s(%d)\n", __func__, enable);
543
544	if (enable)
545		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
546	else {
547		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
548		s5h1411_softreset(fe);
549	}
550
551	return 0;
552}
553
554static int s5h1411_register_reset(struct dvb_frontend *fe)
555{
556	struct s5h1411_state *state = fe->demodulator_priv;
557
558	dprintk("%s()\n", __func__);
559
560	return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
561}
562
563/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
564static int s5h1411_set_frontend(struct dvb_frontend *fe,
565	struct dvb_frontend_parameters *p)
566{
567	struct s5h1411_state *state = fe->demodulator_priv;
568
569	dprintk("%s(frequency=%d)\n", __func__, p->frequency);
570
571	s5h1411_softreset(fe);
572
573	state->current_frequency = p->frequency;
574
575	s5h1411_enable_modulation(fe, p->u.vsb.modulation);
576
577	/* Allow the demod to settle */
578	msleep(100);
579
580	if (fe->ops.tuner_ops.set_params) {
581		if (fe->ops.i2c_gate_ctrl)
582			fe->ops.i2c_gate_ctrl(fe, 1);
583
584		fe->ops.tuner_ops.set_params(fe, p);
585
586		if (fe->ops.i2c_gate_ctrl)
587			fe->ops.i2c_gate_ctrl(fe, 0);
588	}
589
590	return 0;
591}
592
593/* Reset the demod hardware and reset all of the configuration registers
594   to a default state. */
595static int s5h1411_init(struct dvb_frontend *fe)
596{
597	struct s5h1411_state *state = fe->demodulator_priv;
598	int i;
599
600	dprintk("%s()\n", __func__);
601
602	s5h1411_sleep(fe, 0);
603	s5h1411_register_reset(fe);
604
605	for (i = 0; i < ARRAY_SIZE(init_tab); i++)
606		s5h1411_writereg(state, init_tab[i].addr,
607			init_tab[i].reg,
608			init_tab[i].data);
609
610	/* The datasheet says that after initialisation, VSB is default */
611	state->current_modulation = VSB_8;
612
613	if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
614		/* Serial */
615		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, 0x1101);
616	else
617		/* Parallel */
618		s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, 0x1001);
619
620	s5h1411_set_spectralinversion(fe, state->config->inversion);
621	s5h1411_set_if_freq(fe, state->config->vsb_if);
622	s5h1411_set_gpio(fe, state->config->gpio);
623	s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
624	s5h1411_softreset(fe);
625
626	/* Note: Leaving the I2C gate closed. */
627	s5h1411_i2c_gate_ctrl(fe, 0);
628
629	return 0;
630}
631
632static int s5h1411_read_status(struct dvb_frontend *fe, fe_status_t *status)
633{
634	struct s5h1411_state *state = fe->demodulator_priv;
635	u16 reg;
636	u32 tuner_status = 0;
637
638	*status = 0;
639
640	/* Get the demodulator status */
641	reg = (s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2) >> 15)
642		& 0x0001;
643	if (reg)
644		*status |= FE_HAS_LOCK | FE_HAS_CARRIER | FE_HAS_SIGNAL;
645
646	switch (state->current_modulation) {
647	case QAM_64:
648	case QAM_256:
649		reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
650		if (reg & 0x100)
651			*status |= FE_HAS_VITERBI;
652		if (reg & 0x10)
653			*status |= FE_HAS_SYNC;
654		break;
655	case VSB_8:
656		reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x5e);
657		if (reg & 0x0001)
658			*status |= FE_HAS_SYNC;
659		reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
660		if (reg & 0x1000)
661			*status |= FE_HAS_VITERBI;
662		break;
663	default:
664		return -EINVAL;
665	}
666
667	switch (state->config->status_mode) {
668	case S5H1411_DEMODLOCKING:
669		if (*status & FE_HAS_VITERBI)
670			*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
671		break;
672	case S5H1411_TUNERLOCKING:
673		/* Get the tuner status */
674		if (fe->ops.tuner_ops.get_status) {
675			if (fe->ops.i2c_gate_ctrl)
676				fe->ops.i2c_gate_ctrl(fe, 1);
677
678			fe->ops.tuner_ops.get_status(fe, &tuner_status);
679
680			if (fe->ops.i2c_gate_ctrl)
681				fe->ops.i2c_gate_ctrl(fe, 0);
682		}
683		if (tuner_status)
684			*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
685		break;
686	}
687
688	dprintk("%s() status 0x%08x\n", __func__, *status);
689
690	return 0;
691}
692
693static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
694{
695	int i, ret = -EINVAL;
696	dprintk("%s()\n", __func__);
697
698	for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
699		if (v < qam256_snr_tab[i].val) {
700			*snr = qam256_snr_tab[i].data;
701			ret = 0;
702			break;
703		}
704	}
705	return ret;
706}
707
708static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
709{
710	int i, ret = -EINVAL;
711	dprintk("%s()\n", __func__);
712
713	for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
714		if (v < qam64_snr_tab[i].val) {
715			*snr = qam64_snr_tab[i].data;
716			ret = 0;
717			break;
718		}
719	}
720	return ret;
721}
722
723static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
724{
725	int i, ret = -EINVAL;
726	dprintk("%s()\n", __func__);
727
728	for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
729		if (v > vsb_snr_tab[i].val) {
730			*snr = vsb_snr_tab[i].data;
731			ret = 0;
732			break;
733		}
734	}
735	dprintk("%s() snr=%d\n", __func__, *snr);
736	return ret;
737}
738
739static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
740{
741	struct s5h1411_state *state = fe->demodulator_priv;
742	u16 reg;
743	dprintk("%s()\n", __func__);
744
745	switch (state->current_modulation) {
746	case QAM_64:
747		reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
748		return s5h1411_qam64_lookup_snr(fe, snr, reg);
749	case QAM_256:
750		reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
751		return s5h1411_qam256_lookup_snr(fe, snr, reg);
752	case VSB_8:
753		reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
754			0xf2) & 0x3ff;
755		return s5h1411_vsb_lookup_snr(fe, snr, reg);
756	default:
757		break;
758	}
759
760	return -EINVAL;
761}
762
763static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
764	u16 *signal_strength)
765{
766	return s5h1411_read_snr(fe, signal_strength);
767}
768
769static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
770{
771	struct s5h1411_state *state = fe->demodulator_priv;
772
773	*ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
774
775	return 0;
776}
777
778static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
779{
780	return s5h1411_read_ucblocks(fe, ber);
781}
782
783static int s5h1411_get_frontend(struct dvb_frontend *fe,
784				struct dvb_frontend_parameters *p)
785{
786	struct s5h1411_state *state = fe->demodulator_priv;
787
788	p->frequency = state->current_frequency;
789	p->u.vsb.modulation = state->current_modulation;
790
791	return 0;
792}
793
794static int s5h1411_get_tune_settings(struct dvb_frontend *fe,
795				     struct dvb_frontend_tune_settings *tune)
796{
797	tune->min_delay_ms = 1000;
798	return 0;
799}
800
801static void s5h1411_release(struct dvb_frontend *fe)
802{
803	struct s5h1411_state *state = fe->demodulator_priv;
804	kfree(state);
805}
806
807static struct dvb_frontend_ops s5h1411_ops;
808
809struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
810				    struct i2c_adapter *i2c)
811{
812	struct s5h1411_state *state = NULL;
813	u16 reg;
814
815	/* allocate memory for the internal state */
816	state = kmalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
817	if (state == NULL)
818		goto error;
819
820	/* setup the state */
821	state->config = config;
822	state->i2c = i2c;
823	state->current_modulation = VSB_8;
824	state->inversion = state->config->inversion;
825
826	/* check if the demod exists */
827	reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
828	if (reg != 0x0066)
829		goto error;
830
831	/* create dvb_frontend */
832	memcpy(&state->frontend.ops, &s5h1411_ops,
833	       sizeof(struct dvb_frontend_ops));
834
835	state->frontend.demodulator_priv = state;
836
837	if (s5h1411_init(&state->frontend) != 0) {
838		printk(KERN_ERR "%s: Failed to initialize correctly\n",
839			__func__);
840		goto error;
841	}
842
843	/* Note: Leaving the I2C gate open here. */
844	s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
845
846	return &state->frontend;
847
848error:
849	kfree(state);
850	return NULL;
851}
852EXPORT_SYMBOL(s5h1411_attach);
853
854static struct dvb_frontend_ops s5h1411_ops = {
855
856	.info = {
857		.name			= "Samsung S5H1411 QAM/8VSB Frontend",
858		.type			= FE_ATSC,
859		.frequency_min		= 54000000,
860		.frequency_max		= 858000000,
861		.frequency_stepsize	= 62500,
862		.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
863	},
864
865	.init                 = s5h1411_init,
866	.i2c_gate_ctrl        = s5h1411_i2c_gate_ctrl,
867	.set_frontend         = s5h1411_set_frontend,
868	.get_frontend         = s5h1411_get_frontend,
869	.get_tune_settings    = s5h1411_get_tune_settings,
870	.read_status          = s5h1411_read_status,
871	.read_ber             = s5h1411_read_ber,
872	.read_signal_strength = s5h1411_read_signal_strength,
873	.read_snr             = s5h1411_read_snr,
874	.read_ucblocks        = s5h1411_read_ucblocks,
875	.release              = s5h1411_release,
876};
877
878module_param(debug, int, 0644);
879MODULE_PARM_DESC(debug, "Enable verbose debug messages");
880
881MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
882MODULE_AUTHOR("Steven Toth");
883MODULE_LICENSE("GPL");
884
885/*
886 * Local variables:
887 * c-basic-offset: 8
888 */
889