tda1004x.c revision c2026b3af0c8ad33ef253a950c271f2d0da111b6
1 /* 2 Driver for Philips tda1004xh OFDM Demodulator 3 4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 21 */ 22/* 23 * This driver needs external firmware. Please use the commands 24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045", 25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to 26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware. 27 */ 28#define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw" 29#define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw" 30 31#include <linux/init.h> 32#include <linux/module.h> 33#include <linux/moduleparam.h> 34#include <linux/device.h> 35#include "dvb_frontend.h" 36#include "tda1004x.h" 37 38enum tda1004x_demod { 39 TDA1004X_DEMOD_TDA10045, 40 TDA1004X_DEMOD_TDA10046, 41}; 42 43struct tda1004x_state { 44 struct i2c_adapter* i2c; 45 struct dvb_frontend_ops ops; 46 const struct tda1004x_config* config; 47 struct dvb_frontend frontend; 48 49 /* private demod data */ 50 u8 initialised; 51 enum tda1004x_demod demod_type; 52}; 53 54static int debug; 55#define dprintk(args...) \ 56 do { \ 57 if (debug) printk(KERN_DEBUG "tda1004x: " args); \ 58 } while (0) 59 60#define TDA1004X_CHIPID 0x00 61#define TDA1004X_AUTO 0x01 62#define TDA1004X_IN_CONF1 0x02 63#define TDA1004X_IN_CONF2 0x03 64#define TDA1004X_OUT_CONF1 0x04 65#define TDA1004X_OUT_CONF2 0x05 66#define TDA1004X_STATUS_CD 0x06 67#define TDA1004X_CONFC4 0x07 68#define TDA1004X_DSSPARE2 0x0C 69#define TDA10045H_CODE_IN 0x0D 70#define TDA10045H_FWPAGE 0x0E 71#define TDA1004X_SCAN_CPT 0x10 72#define TDA1004X_DSP_CMD 0x11 73#define TDA1004X_DSP_ARG 0x12 74#define TDA1004X_DSP_DATA1 0x13 75#define TDA1004X_DSP_DATA2 0x14 76#define TDA1004X_CONFADC1 0x15 77#define TDA1004X_CONFC1 0x16 78#define TDA10045H_S_AGC 0x1a 79#define TDA10046H_AGC_TUN_LEVEL 0x1a 80#define TDA1004X_SNR 0x1c 81#define TDA1004X_CONF_TS1 0x1e 82#define TDA1004X_CONF_TS2 0x1f 83#define TDA1004X_CBER_RESET 0x20 84#define TDA1004X_CBER_MSB 0x21 85#define TDA1004X_CBER_LSB 0x22 86#define TDA1004X_CVBER_LUT 0x23 87#define TDA1004X_VBER_MSB 0x24 88#define TDA1004X_VBER_MID 0x25 89#define TDA1004X_VBER_LSB 0x26 90#define TDA1004X_UNCOR 0x27 91 92#define TDA10045H_CONFPLL_P 0x2D 93#define TDA10045H_CONFPLL_M_MSB 0x2E 94#define TDA10045H_CONFPLL_M_LSB 0x2F 95#define TDA10045H_CONFPLL_N 0x30 96 97#define TDA10046H_CONFPLL1 0x2D 98#define TDA10046H_CONFPLL2 0x2F 99#define TDA10046H_CONFPLL3 0x30 100#define TDA10046H_TIME_WREF1 0x31 101#define TDA10046H_TIME_WREF2 0x32 102#define TDA10046H_TIME_WREF3 0x33 103#define TDA10046H_TIME_WREF4 0x34 104#define TDA10046H_TIME_WREF5 0x35 105 106#define TDA10045H_UNSURW_MSB 0x31 107#define TDA10045H_UNSURW_LSB 0x32 108#define TDA10045H_WREF_MSB 0x33 109#define TDA10045H_WREF_MID 0x34 110#define TDA10045H_WREF_LSB 0x35 111#define TDA10045H_MUXOUT 0x36 112#define TDA1004X_CONFADC2 0x37 113 114#define TDA10045H_IOFFSET 0x38 115 116#define TDA10046H_CONF_TRISTATE1 0x3B 117#define TDA10046H_CONF_TRISTATE2 0x3C 118#define TDA10046H_CONF_POLARITY 0x3D 119#define TDA10046H_FREQ_OFFSET 0x3E 120#define TDA10046H_GPIO_OUT_SEL 0x41 121#define TDA10046H_GPIO_SELECT 0x42 122#define TDA10046H_AGC_CONF 0x43 123#define TDA10046H_AGC_THR 0x44 124#define TDA10046H_AGC_RENORM 0x45 125#define TDA10046H_AGC_GAINS 0x46 126#define TDA10046H_AGC_TUN_MIN 0x47 127#define TDA10046H_AGC_TUN_MAX 0x48 128#define TDA10046H_AGC_IF_MIN 0x49 129#define TDA10046H_AGC_IF_MAX 0x4A 130 131#define TDA10046H_FREQ_PHY2_MSB 0x4D 132#define TDA10046H_FREQ_PHY2_LSB 0x4E 133 134#define TDA10046H_CVBER_CTRL 0x4F 135#define TDA10046H_AGC_IF_LEVEL 0x52 136#define TDA10046H_CODE_CPT 0x57 137#define TDA10046H_CODE_IN 0x58 138 139 140static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) 141{ 142 int ret; 143 u8 buf[] = { reg, data }; 144 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 }; 145 146 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data); 147 148 msg.addr = state->config->demod_address; 149 ret = i2c_transfer(state->i2c, &msg, 1); 150 151 if (ret != 1) 152 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n", 153 __FUNCTION__, reg, data, ret); 154 155 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__, 156 reg, data, ret); 157 return (ret != 1) ? -1 : 0; 158} 159 160static int tda1004x_read_byte(struct tda1004x_state *state, int reg) 161{ 162 int ret; 163 u8 b0[] = { reg }; 164 u8 b1[] = { 0 }; 165 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 }, 166 { .flags = I2C_M_RD, .buf = b1, .len = 1 }}; 167 168 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg); 169 170 msg[0].addr = state->config->demod_address; 171 msg[1].addr = state->config->demod_address; 172 ret = i2c_transfer(state->i2c, msg, 2); 173 174 if (ret != 2) { 175 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg, 176 ret); 177 return -1; 178 } 179 180 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__, 181 reg, b1[0], ret); 182 return b1[0]; 183} 184 185static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) 186{ 187 int val; 188 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg, 189 mask, data); 190 191 // read a byte and check 192 val = tda1004x_read_byte(state, reg); 193 if (val < 0) 194 return val; 195 196 // mask if off 197 val = val & ~mask; 198 val |= data & 0xff; 199 200 // write it out again 201 return tda1004x_write_byteI(state, reg, val); 202} 203 204static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) 205{ 206 int i; 207 int result; 208 209 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len); 210 211 result = 0; 212 for (i = 0; i < len; i++) { 213 result = tda1004x_write_byteI(state, reg + i, buf[i]); 214 if (result != 0) 215 break; 216 } 217 218 return result; 219} 220 221static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) 222{ 223 int result; 224 dprintk("%s\n", __FUNCTION__); 225 226 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); 227 msleep(1); 228 return result; 229} 230 231static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) 232{ 233 dprintk("%s\n", __FUNCTION__); 234 235 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); 236} 237 238static int tda10045h_set_bandwidth(struct tda1004x_state *state, 239 fe_bandwidth_t bandwidth) 240{ 241 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; 242 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; 243 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; 244 245 switch (bandwidth) { 246 case BANDWIDTH_6_MHZ: 247 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); 248 break; 249 250 case BANDWIDTH_7_MHZ: 251 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); 252 break; 253 254 case BANDWIDTH_8_MHZ: 255 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); 256 break; 257 258 default: 259 return -EINVAL; 260 } 261 262 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); 263 264 return 0; 265} 266 267static int tda10046h_set_bandwidth(struct tda1004x_state *state, 268 fe_bandwidth_t bandwidth) 269{ 270 static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e }; 271 static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 }; 272 static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd }; 273 274 switch (bandwidth) { 275 case BANDWIDTH_6_MHZ: 276 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz)); 277 if (state->config->if_freq == TDA10046_FREQ_045) { 278 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x09); 279 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x4f); 280 } 281 break; 282 283 case BANDWIDTH_7_MHZ: 284 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz)); 285 if (state->config->if_freq == TDA10046_FREQ_045) { 286 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); 287 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x79); 288 } 289 break; 290 291 case BANDWIDTH_8_MHZ: 292 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz)); 293 if (state->config->if_freq == TDA10046_FREQ_045) { 294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); 295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); 296 } 297 break; 298 299 default: 300 return -EINVAL; 301 } 302 303 return 0; 304} 305 306static int tda1004x_do_upload(struct tda1004x_state *state, 307 unsigned char *mem, unsigned int len, 308 u8 dspCodeCounterReg, u8 dspCodeInReg) 309{ 310 u8 buf[65]; 311 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 }; 312 int tx_size; 313 int pos = 0; 314 315 /* clear code counter */ 316 tda1004x_write_byteI(state, dspCodeCounterReg, 0); 317 fw_msg.addr = state->config->demod_address; 318 319 buf[0] = dspCodeInReg; 320 while (pos != len) { 321 // work out how much to send this time 322 tx_size = len - pos; 323 if (tx_size > 0x10) 324 tx_size = 0x10; 325 326 // send the chunk 327 memcpy(buf + 1, mem + pos, tx_size); 328 fw_msg.len = tx_size + 1; 329 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) { 330 printk(KERN_ERR "tda1004x: Error during firmware upload\n"); 331 return -EIO; 332 } 333 pos += tx_size; 334 335 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos); 336 } 337 // give the DSP a chance to settle 03/10/05 Hac 338 msleep(100); 339 340 return 0; 341} 342 343static int tda1004x_check_upload_ok(struct tda1004x_state *state) 344{ 345 u8 data1, data2; 346 unsigned long timeout; 347 348 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { 349 timeout = jiffies + 2 * HZ; 350 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { 351 if (time_after(jiffies, timeout)) { 352 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n"); 353 break; 354 } 355 msleep(1); 356 } 357 } else 358 msleep(100); 359 360 // check upload was OK 361 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP 362 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); 363 364 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); 365 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); 366 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) { 367 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2); 368 return -EIO; 369 } 370 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2); 371 return 0; 372} 373 374static int tda10045_fwupload(struct dvb_frontend* fe) 375{ 376 struct tda1004x_state* state = fe->demodulator_priv; 377 int ret; 378 const struct firmware *fw; 379 380 /* don't re-upload unless necessary */ 381 if (tda1004x_check_upload_ok(state) == 0) 382 return 0; 383 384 /* request the firmware, this will block until someone uploads it */ 385 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE); 386 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); 387 if (ret) { 388 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); 389 return ret; 390 } 391 392 /* reset chip */ 393 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); 394 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); 395 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); 396 msleep(10); 397 398 /* set parameters */ 399 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ); 400 401 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); 402 release_firmware(fw); 403 if (ret) 404 return ret; 405 printk(KERN_INFO "tda1004x: firmware upload complete\n"); 406 407 /* wait for DSP to initialise */ 408 /* DSPREADY doesn't seem to work on the TDA10045H */ 409 msleep(100); 410 411 return tda1004x_check_upload_ok(state); 412} 413 414static void tda10046_init_plls(struct dvb_frontend* fe) 415{ 416 struct tda1004x_state* state = fe->demodulator_priv; 417 418 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); 419 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10 420 if (state->config->xtal_freq == TDA10046_XTAL_4M ) { 421 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__); 422 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 423 } else { 424 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__); 425 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 426 } 427 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); 428 switch (state->config->if_freq) { 429 case TDA10046_FREQ_3617: 430 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); 431 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); 432 break; 433 case TDA10046_FREQ_3613: 434 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); 435 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13); 436 break; 437 case TDA10046_FREQ_045: 438 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); 439 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); 440 break; 441 case TDA10046_FREQ_052: 442 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); 443 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06); 444 break; 445 } 446 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz 447} 448 449static int tda10046_fwupload(struct dvb_frontend* fe) 450{ 451 struct tda1004x_state* state = fe->demodulator_priv; 452 int ret; 453 const struct firmware *fw; 454 455 /* reset + wake up chip */ 456 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0); 457 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); 458 /* let the clocks recover from sleep */ 459 msleep(5); 460 461 /* don't re-upload unless necessary */ 462 if (tda1004x_check_upload_ok(state) == 0) 463 return 0; 464 465 /* set parameters */ 466 tda10046_init_plls(fe); 467 468 if (state->config->request_firmware != NULL) { 469 /* request the firmware, this will block until someone uploads it */ 470 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n"); 471 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); 472 if (ret) { 473 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); 474 return ret; 475 } 476 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST 477 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); 478 release_firmware(fw); 479 if (ret) 480 return ret; 481 } else { 482 /* boot from firmware eeprom */ 483 /* Hac Note: we might need to do some GPIO Magic here */ 484 printk(KERN_INFO "tda1004x: booting from eeprom\n"); 485 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4); 486 msleep(300); 487 } 488 return tda1004x_check_upload_ok(state); 489} 490 491static int tda1004x_encode_fec(int fec) 492{ 493 // convert known FEC values 494 switch (fec) { 495 case FEC_1_2: 496 return 0; 497 case FEC_2_3: 498 return 1; 499 case FEC_3_4: 500 return 2; 501 case FEC_5_6: 502 return 3; 503 case FEC_7_8: 504 return 4; 505 } 506 507 // unsupported 508 return -EINVAL; 509} 510 511static int tda1004x_decode_fec(int tdafec) 512{ 513 // convert known FEC values 514 switch (tdafec) { 515 case 0: 516 return FEC_1_2; 517 case 1: 518 return FEC_2_3; 519 case 2: 520 return FEC_3_4; 521 case 3: 522 return FEC_5_6; 523 case 4: 524 return FEC_7_8; 525 } 526 527 // unsupported 528 return -1; 529} 530 531int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data) 532{ 533 struct tda1004x_state* state = fe->demodulator_priv; 534 535 return tda1004x_write_byteI(state, reg, data); 536} 537 538static int tda10045_init(struct dvb_frontend* fe) 539{ 540 struct tda1004x_state* state = fe->demodulator_priv; 541 542 dprintk("%s\n", __FUNCTION__); 543 544 if (state->initialised) 545 return 0; 546 547 if (tda10045_fwupload(fe)) { 548 printk("tda1004x: firmware upload failed\n"); 549 return -EIO; 550 } 551 552 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC 553 554 // Init the PLL 555 if (state->config->pll_init) { 556 tda1004x_enable_tuner_i2c(state); 557 state->config->pll_init(fe); 558 tda1004x_disable_tuner_i2c(state); 559 } 560 561 // tda setup 562 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer 563 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream 564 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal 565 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer 566 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset 567 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset 568 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface 569 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface 570 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits 571 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity 572 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); 573 574 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); 575 576 state->initialised = 1; 577 return 0; 578} 579 580static int tda10046_init(struct dvb_frontend* fe) 581{ 582 struct tda1004x_state* state = fe->demodulator_priv; 583 dprintk("%s\n", __FUNCTION__); 584 585 if (state->initialised) 586 return 0; 587 588 if (tda10046_fwupload(fe)) { 589 printk("tda1004x: firmware upload failed\n"); 590 return -EIO; 591 } 592 593 // Init the tuner PLL 594 if (state->config->pll_init) { 595 tda1004x_enable_tuner_i2c(state); 596 state->config->pll_init(fe); 597 tda1004x_disable_tuner_i2c(state); 598 } 599 600 // tda setup 601 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer 602 tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream 603 tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer 604 605 tda10046_init_plls(fe); 606 switch (state->config->agc_config) { 607 case TDA10046_AGC_DEFAULT: 608 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup 609 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities 610 break; 611 case TDA10046_AGC_IFO_AUTO_NEG: 612 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup 613 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities 614 break; 615 case TDA10046_AGC_IFO_AUTO_POS: 616 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup 617 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities 618 break; 619 case TDA10046_AGC_TDA827X: 620 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup 621 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold 622 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x0E); // Gain Renormalize 623 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities 624 break; 625 } 626 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on 627 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } 628 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values 629 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } 630 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } 631 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1 632 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits 633 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config 634 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config 635 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); 636 637 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup 638 tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config 639 tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select 640 641 state->initialised = 1; 642 return 0; 643} 644 645static int tda1004x_set_fe(struct dvb_frontend* fe, 646 struct dvb_frontend_parameters *fe_params) 647{ 648 struct tda1004x_state* state = fe->demodulator_priv; 649 int tmp; 650 int inversion; 651 652 dprintk("%s\n", __FUNCTION__); 653 654 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { 655 // setup auto offset 656 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); 657 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); 658 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); 659 660 // disable agc_conf[2] 661 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); 662 } 663 664 // set frequency 665 tda1004x_enable_tuner_i2c(state); 666 state->config->pll_set(fe, fe_params); 667 tda1004x_disable_tuner_i2c(state); 668 669 // Hardcoded to use auto as much as possible on the TDA10045 as it 670 // is very unreliable if AUTO mode is _not_ used. 671 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { 672 fe_params->u.ofdm.code_rate_HP = FEC_AUTO; 673 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; 674 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; 675 } 676 677 // Set standard params.. or put them to auto 678 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) || 679 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) || 680 (fe_params->u.ofdm.constellation == QAM_AUTO) || 681 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) { 682 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto 683 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits 684 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits 685 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits 686 } else { 687 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto 688 689 // set HP FEC 690 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP); 691 if (tmp < 0) 692 return tmp; 693 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); 694 695 // set LP FEC 696 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP); 697 if (tmp < 0) 698 return tmp; 699 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); 700 701 // set constellation 702 switch (fe_params->u.ofdm.constellation) { 703 case QPSK: 704 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); 705 break; 706 707 case QAM_16: 708 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); 709 break; 710 711 case QAM_64: 712 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); 713 break; 714 715 default: 716 return -EINVAL; 717 } 718 719 // set hierarchy 720 switch (fe_params->u.ofdm.hierarchy_information) { 721 case HIERARCHY_NONE: 722 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); 723 break; 724 725 case HIERARCHY_1: 726 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); 727 break; 728 729 case HIERARCHY_2: 730 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); 731 break; 732 733 case HIERARCHY_4: 734 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); 735 break; 736 737 default: 738 return -EINVAL; 739 } 740 } 741 742 // set bandwidth 743 switch (state->demod_type) { 744 case TDA1004X_DEMOD_TDA10045: 745 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); 746 break; 747 748 case TDA1004X_DEMOD_TDA10046: 749 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); 750 break; 751 } 752 753 // set inversion 754 inversion = fe_params->inversion; 755 if (state->config->invert) 756 inversion = inversion ? INVERSION_OFF : INVERSION_ON; 757 switch (inversion) { 758 case INVERSION_OFF: 759 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); 760 break; 761 762 case INVERSION_ON: 763 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); 764 break; 765 766 default: 767 return -EINVAL; 768 } 769 770 // set guard interval 771 switch (fe_params->u.ofdm.guard_interval) { 772 case GUARD_INTERVAL_1_32: 773 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 774 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); 775 break; 776 777 case GUARD_INTERVAL_1_16: 778 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); 780 break; 781 782 case GUARD_INTERVAL_1_8: 783 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 784 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); 785 break; 786 787 case GUARD_INTERVAL_1_4: 788 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 789 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); 790 break; 791 792 case GUARD_INTERVAL_AUTO: 793 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); 794 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); 795 break; 796 797 default: 798 return -EINVAL; 799 } 800 801 // set transmission mode 802 switch (fe_params->u.ofdm.transmission_mode) { 803 case TRANSMISSION_MODE_2K: 804 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); 805 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); 806 break; 807 808 case TRANSMISSION_MODE_8K: 809 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); 810 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); 811 break; 812 813 case TRANSMISSION_MODE_AUTO: 814 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); 815 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); 816 break; 817 818 default: 819 return -EINVAL; 820 } 821 822 // start the lock 823 switch (state->demod_type) { 824 case TDA1004X_DEMOD_TDA10045: 825 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); 826 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); 827 break; 828 829 case TDA1004X_DEMOD_TDA10046: 830 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); 831 break; 832 } 833 834 msleep(10); 835 836 return 0; 837} 838 839static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) 840{ 841 struct tda1004x_state* state = fe->demodulator_priv; 842 dprintk("%s\n", __FUNCTION__); 843 844 // inversion status 845 fe_params->inversion = INVERSION_OFF; 846 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) 847 fe_params->inversion = INVERSION_ON; 848 if (state->config->invert) 849 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON; 850 851 // bandwidth 852 switch (state->demod_type) { 853 case TDA1004X_DEMOD_TDA10045: 854 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { 855 case 0x14: 856 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 857 break; 858 case 0xdb: 859 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 860 break; 861 case 0x4f: 862 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 863 break; 864 } 865 break; 866 867 case TDA1004X_DEMOD_TDA10046: 868 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { 869 case 0x60: 870 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 871 break; 872 case 0x6e: 873 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 874 break; 875 case 0x80: 876 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 877 break; 878 } 879 break; 880 } 881 882 // FEC 883 fe_params->u.ofdm.code_rate_HP = 884 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); 885 fe_params->u.ofdm.code_rate_LP = 886 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); 887 888 // constellation 889 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { 890 case 0: 891 fe_params->u.ofdm.constellation = QPSK; 892 break; 893 case 1: 894 fe_params->u.ofdm.constellation = QAM_16; 895 break; 896 case 2: 897 fe_params->u.ofdm.constellation = QAM_64; 898 break; 899 } 900 901 // transmission mode 902 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 903 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) 904 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 905 906 // guard interval 907 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { 908 case 0: 909 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 910 break; 911 case 1: 912 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 913 break; 914 case 2: 915 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 916 break; 917 case 3: 918 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 919 break; 920 } 921 922 // hierarchy 923 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { 924 case 0: 925 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE; 926 break; 927 case 1: 928 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1; 929 break; 930 case 2: 931 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2; 932 break; 933 case 3: 934 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4; 935 break; 936 } 937 938 return 0; 939} 940 941static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status) 942{ 943 struct tda1004x_state* state = fe->demodulator_priv; 944 int status; 945 int cber; 946 int vber; 947 948 dprintk("%s\n", __FUNCTION__); 949 950 // read status 951 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); 952 if (status == -1) 953 return -EIO; 954 955 // decode 956 *fe_status = 0; 957 if (status & 4) 958 *fe_status |= FE_HAS_SIGNAL; 959 if (status & 2) 960 *fe_status |= FE_HAS_CARRIER; 961 if (status & 8) 962 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; 963 964 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi 965 // is getting anything valid 966 if (!(*fe_status & FE_HAS_VITERBI)) { 967 // read the CBER 968 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); 969 if (cber == -1) 970 return -EIO; 971 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); 972 if (status == -1) 973 return -EIO; 974 cber |= (status << 8); 975 tda1004x_read_byte(state, TDA1004X_CBER_RESET); 976 977 if (cber != 65535) 978 *fe_status |= FE_HAS_VITERBI; 979 } 980 981 // if we DO have some valid VITERBI output, but don't already have SYNC 982 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid. 983 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) { 984 // read the VBER 985 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); 986 if (vber == -1) 987 return -EIO; 988 status = tda1004x_read_byte(state, TDA1004X_VBER_MID); 989 if (status == -1) 990 return -EIO; 991 vber |= (status << 8); 992 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); 993 if (status == -1) 994 return -EIO; 995 vber |= ((status << 16) & 0x0f); 996 tda1004x_read_byte(state, TDA1004X_CVBER_LUT); 997 998 // if RS has passed some valid TS packets, then we must be 999 // getting some SYNC bytes 1000 if (vber < 16632) 1001 *fe_status |= FE_HAS_SYNC; 1002 } 1003 1004 // success 1005 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status); 1006 return 0; 1007} 1008 1009static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal) 1010{ 1011 struct tda1004x_state* state = fe->demodulator_priv; 1012 int tmp; 1013 int reg = 0; 1014 1015 dprintk("%s\n", __FUNCTION__); 1016 1017 // determine the register to use 1018 switch (state->demod_type) { 1019 case TDA1004X_DEMOD_TDA10045: 1020 reg = TDA10045H_S_AGC; 1021 break; 1022 1023 case TDA1004X_DEMOD_TDA10046: 1024 reg = TDA10046H_AGC_IF_LEVEL; 1025 break; 1026 } 1027 1028 // read it 1029 tmp = tda1004x_read_byte(state, reg); 1030 if (tmp < 0) 1031 return -EIO; 1032 1033 *signal = (tmp << 8) | tmp; 1034 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal); 1035 return 0; 1036} 1037 1038static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr) 1039{ 1040 struct tda1004x_state* state = fe->demodulator_priv; 1041 int tmp; 1042 1043 dprintk("%s\n", __FUNCTION__); 1044 1045 // read it 1046 tmp = tda1004x_read_byte(state, TDA1004X_SNR); 1047 if (tmp < 0) 1048 return -EIO; 1049 tmp = 255 - tmp; 1050 1051 *snr = ((tmp << 8) | tmp); 1052 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr); 1053 return 0; 1054} 1055 1056static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 1057{ 1058 struct tda1004x_state* state = fe->demodulator_priv; 1059 int tmp; 1060 int tmp2; 1061 int counter; 1062 1063 dprintk("%s\n", __FUNCTION__); 1064 1065 // read the UCBLOCKS and reset 1066 counter = 0; 1067 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); 1068 if (tmp < 0) 1069 return -EIO; 1070 tmp &= 0x7f; 1071 while (counter++ < 5) { 1072 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); 1073 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); 1074 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); 1075 1076 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); 1077 if (tmp2 < 0) 1078 return -EIO; 1079 tmp2 &= 0x7f; 1080 if ((tmp2 < tmp) || (tmp2 == 0)) 1081 break; 1082 } 1083 1084 if (tmp != 0x7f) 1085 *ucblocks = tmp; 1086 else 1087 *ucblocks = 0xffffffff; 1088 1089 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks); 1090 return 0; 1091} 1092 1093static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber) 1094{ 1095 struct tda1004x_state* state = fe->demodulator_priv; 1096 int tmp; 1097 1098 dprintk("%s\n", __FUNCTION__); 1099 1100 // read it in 1101 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); 1102 if (tmp < 0) 1103 return -EIO; 1104 *ber = tmp << 1; 1105 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); 1106 if (tmp < 0) 1107 return -EIO; 1108 *ber |= (tmp << 9); 1109 tda1004x_read_byte(state, TDA1004X_CBER_RESET); 1110 1111 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber); 1112 return 0; 1113} 1114 1115static int tda1004x_sleep(struct dvb_frontend* fe) 1116{ 1117 struct tda1004x_state* state = fe->demodulator_priv; 1118 1119 switch (state->demod_type) { 1120 case TDA1004X_DEMOD_TDA10045: 1121 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); 1122 break; 1123 1124 case TDA1004X_DEMOD_TDA10046: 1125 if (state->config->pll_sleep != NULL) { 1126 tda1004x_enable_tuner_i2c(state); 1127 state->config->pll_sleep(fe); 1128 tda1004x_disable_tuner_i2c(state); 1129 } 1130 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); 1131 break; 1132 } 1133 state->initialised = 0; 1134 1135 return 0; 1136} 1137 1138static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 1139{ 1140 fesettings->min_delay_ms = 800; 1141 /* Drift compensation makes no sense for DVB-T */ 1142 fesettings->step_size = 0; 1143 fesettings->max_drift = 0; 1144 return 0; 1145} 1146 1147static void tda1004x_release(struct dvb_frontend* fe) 1148{ 1149 struct tda1004x_state *state = fe->demodulator_priv; 1150 kfree(state); 1151} 1152 1153static struct dvb_frontend_ops tda10045_ops = { 1154 .info = { 1155 .name = "Philips TDA10045H DVB-T", 1156 .type = FE_OFDM, 1157 .frequency_min = 51000000, 1158 .frequency_max = 858000000, 1159 .frequency_stepsize = 166667, 1160 .caps = 1161 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1162 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1163 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1164 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO 1165 }, 1166 1167 .release = tda1004x_release, 1168 1169 .init = tda10045_init, 1170 .sleep = tda1004x_sleep, 1171 1172 .set_frontend = tda1004x_set_fe, 1173 .get_frontend = tda1004x_get_fe, 1174 .get_tune_settings = tda1004x_get_tune_settings, 1175 1176 .read_status = tda1004x_read_status, 1177 .read_ber = tda1004x_read_ber, 1178 .read_signal_strength = tda1004x_read_signal_strength, 1179 .read_snr = tda1004x_read_snr, 1180 .read_ucblocks = tda1004x_read_ucblocks, 1181}; 1182 1183struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, 1184 struct i2c_adapter* i2c) 1185{ 1186 struct tda1004x_state *state; 1187 1188 /* allocate memory for the internal state */ 1189 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); 1190 if (!state) 1191 return NULL; 1192 1193 /* setup the state */ 1194 state->config = config; 1195 state->i2c = i2c; 1196 memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); 1197 state->initialised = 0; 1198 state->demod_type = TDA1004X_DEMOD_TDA10045; 1199 1200 /* check if the demod is there */ 1201 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) { 1202 kfree(state); 1203 return NULL; 1204 } 1205 1206 /* create dvb_frontend */ 1207 state->frontend.ops = &state->ops; 1208 state->frontend.demodulator_priv = state; 1209 return &state->frontend; 1210} 1211 1212static struct dvb_frontend_ops tda10046_ops = { 1213 .info = { 1214 .name = "Philips TDA10046H DVB-T", 1215 .type = FE_OFDM, 1216 .frequency_min = 51000000, 1217 .frequency_max = 858000000, 1218 .frequency_stepsize = 166667, 1219 .caps = 1220 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1221 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1222 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1223 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO 1224 }, 1225 1226 .release = tda1004x_release, 1227 1228 .init = tda10046_init, 1229 .sleep = tda1004x_sleep, 1230 1231 .set_frontend = tda1004x_set_fe, 1232 .get_frontend = tda1004x_get_fe, 1233 .get_tune_settings = tda1004x_get_tune_settings, 1234 1235 .read_status = tda1004x_read_status, 1236 .read_ber = tda1004x_read_ber, 1237 .read_signal_strength = tda1004x_read_signal_strength, 1238 .read_snr = tda1004x_read_snr, 1239 .read_ucblocks = tda1004x_read_ucblocks, 1240}; 1241 1242struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, 1243 struct i2c_adapter* i2c) 1244{ 1245 struct tda1004x_state *state; 1246 1247 /* allocate memory for the internal state */ 1248 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); 1249 if (!state) 1250 return NULL; 1251 1252 /* setup the state */ 1253 state->config = config; 1254 state->i2c = i2c; 1255 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); 1256 state->initialised = 0; 1257 state->demod_type = TDA1004X_DEMOD_TDA10046; 1258 1259 /* check if the demod is there */ 1260 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) { 1261 kfree(state); 1262 return NULL; 1263 } 1264 1265 /* create dvb_frontend */ 1266 state->frontend.ops = &state->ops; 1267 state->frontend.demodulator_priv = state; 1268 return &state->frontend; 1269} 1270 1271module_param(debug, int, 0644); 1272MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 1273 1274MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator"); 1275MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach"); 1276MODULE_LICENSE("GPL"); 1277 1278EXPORT_SYMBOL(tda10045_attach); 1279EXPORT_SYMBOL(tda10046_attach); 1280EXPORT_SYMBOL(tda1004x_write_byte); 1281