1/* 2 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR 3 * 4 * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com> 5 * 6 * Special thanks to Fintek for providing hardware and spec sheets. 7 * This driver is based upon the nuvoton, ite and ene drivers for 8 * similar hardware. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26#include <linux/spinlock.h> 27#include <linux/ioctl.h> 28 29/* platform driver name to register */ 30#define FINTEK_DRIVER_NAME "fintek-cir" 31#define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver" 32#define VENDOR_ID_FINTEK 0x1934 33 34 35/* debugging module parameter */ 36static int debug; 37 38#define fit_pr(level, text, ...) \ 39 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) 40 41#define fit_dbg(text, ...) \ 42 if (debug) \ 43 printk(KERN_DEBUG \ 44 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 45 46#define fit_dbg_verbose(text, ...) \ 47 if (debug > 1) \ 48 printk(KERN_DEBUG \ 49 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 50 51#define fit_dbg_wake(text, ...) \ 52 if (debug > 2) \ 53 printk(KERN_DEBUG \ 54 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 55 56 57#define TX_BUF_LEN 256 58#define RX_BUF_LEN 32 59 60struct fintek_dev { 61 struct pnp_dev *pdev; 62 struct rc_dev *rdev; 63 64 spinlock_t fintek_lock; 65 66 /* for rx */ 67 u8 buf[RX_BUF_LEN]; 68 unsigned int pkts; 69 70 struct { 71 spinlock_t lock; 72 u8 buf[TX_BUF_LEN]; 73 unsigned int buf_count; 74 unsigned int cur_buf_num; 75 wait_queue_head_t queue; 76 } tx; 77 78 /* Config register index/data port pair */ 79 u8 cr_ip; 80 u8 cr_dp; 81 82 /* hardware I/O settings */ 83 unsigned long cir_addr; 84 int cir_irq; 85 int cir_port_len; 86 87 /* hardware id */ 88 u8 chip_major; 89 u8 chip_minor; 90 u16 chip_vendor; 91 92 /* hardware features */ 93 bool hw_learning_capable; 94 bool hw_tx_capable; 95 96 /* rx settings */ 97 bool learning_enabled; 98 bool carrier_detect_enabled; 99 100 enum { 101 CMD_HEADER = 0, 102 SUBCMD, 103 CMD_DATA, 104 PARSE_IRDATA, 105 } parser_state; 106 107 u8 cmd, rem; 108 109 /* carrier period = 1 / frequency */ 110 u32 carrier; 111}; 112 113/* buffer packet constants, largely identical to mceusb.c */ 114#define BUF_PULSE_BIT 0x80 115#define BUF_LEN_MASK 0x1f 116#define BUF_SAMPLE_MASK 0x7f 117 118#define BUF_COMMAND_HEADER 0x9f 119#define BUF_COMMAND_MASK 0xe0 120#define BUF_COMMAND_NULL 0x00 121#define BUF_HW_CMD_HEADER 0xff 122#define BUF_CMD_G_REVISION 0x0b 123#define BUF_CMD_S_CARRIER 0x06 124#define BUF_CMD_S_TIMEOUT 0x0c 125#define BUF_CMD_SIG_END 0x01 126#define BUF_CMD_S_TXMASK 0x08 127#define BUF_CMD_S_RXSENSOR 0x14 128#define BUF_RSP_PULSE_COUNT 0x15 129 130#define CIR_SAMPLE_PERIOD 50 131 132/* 133 * Configuration Register: 134 * Index Port 135 * Data Port 136 */ 137#define CR_INDEX_PORT 0x2e 138#define CR_DATA_PORT 0x2f 139 140/* Possible alternate values, depends on how the chip is wired */ 141#define CR_INDEX_PORT2 0x4e 142#define CR_DATA_PORT2 0x4f 143 144/* 145 * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is 146 * active. 1 = 0x4e, 0 = 0x2e 147 */ 148#define PORT_SEL_PORT_4E_EN 0x10 149 150/* Extended Function Mode enable/disable magic values */ 151#define CONFIG_REG_ENABLE 0x87 152#define CONFIG_REG_DISABLE 0xaa 153 154/* Chip IDs found in CR_CHIP_ID_{HI,LO} */ 155#define CHIP_ID_HIGH_F71809U 0x04 156#define CHIP_ID_LOW_F71809U 0x08 157 158/* 159 * Global control regs we need to care about: 160 * Global Control def. 161 * Register name addr val. */ 162#define GCR_SOFTWARE_RESET 0x02 /* 0x00 */ 163#define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */ 164#define GCR_CHIP_ID_HI 0x20 /* 0x04 */ 165#define GCR_CHIP_ID_LO 0x21 /* 0x08 */ 166#define GCR_VENDOR_ID_HI 0x23 /* 0x19 */ 167#define GCR_VENDOR_ID_LO 0x24 /* 0x34 */ 168#define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */ 169#define GCR_KBMOUSE_WAKEUP 0x27 170 171#define LOGICAL_DEV_DISABLE 0x00 172#define LOGICAL_DEV_ENABLE 0x01 173 174/* Logical device number of the CIR function */ 175#define LOGICAL_DEV_CIR 0x05 176 177/* CIR Logical Device (LDN 0x08) config registers */ 178#define CIR_CR_COMMAND_INDEX 0x04 179#define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host 180 must set to 1. When host finshes write 181 command to IR, host must clear to 0. */ 182#define CIR_CR_COMMAND_DATA 0x06 /* Host read or write comand data */ 183#define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx, 184 0x33 = rx + 1 tx */ 185#define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */ 186#define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */ 187#define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */ 188#define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */ 189#define CIR_CR_PSOUT_STATUS 0xf1 190#define CIR_CR_WAKE_KEY3_ADDR 0xf8 191#define CIR_CR_WAKE_KEY3_CODE 0xf9 192#define CIR_CR_WAKE_KEY3_DC 0xfa 193#define CIR_CR_WAKE_CONTROL 0xfb 194#define CIR_CR_WAKE_KEY12_ADDR 0xfc 195#define CIR_CR_WAKE_KEY4_ADDR 0xfd 196#define CIR_CR_WAKE_KEY5_ADDR 0xfe 197 198#define CLASS_RX_ONLY 0xff 199#define CLASS_RX_2TX 0x66 200#define CLASS_RX_1TX 0x33 201 202/* CIR device registers */ 203#define CIR_STATUS 0x00 204#define CIR_RX_DATA 0x01 205#define CIR_TX_CONTROL 0x02 206#define CIR_TX_DATA 0x03 207#define CIR_CONTROL 0x04 208 209/* Bits to enable CIR wake */ 210#define LOGICAL_DEV_ACPI 0x01 211#define LDEV_ACPI_WAKE_EN_REG 0xe8 212#define ACPI_WAKE_EN_CIR_BIT 0x04 213 214#define LDEV_ACPI_PME_EN_REG 0xf0 215#define LDEV_ACPI_PME_CLR_REG 0xf1 216#define ACPI_PME_CIR_BIT 0x02 217 218#define LDEV_ACPI_STATE_REG 0xf4 219#define ACPI_STATE_CIR_BIT 0x20 220 221/* 222 * CIR status register (0x00): 223 * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable) 224 * 3 - TX_FINISH (1 when TX finished, write 1 to clear) 225 * 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear) 226 * 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear) 227 * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear) 228 */ 229#define CIR_STATUS_IRQ_EN 0x80 230#define CIR_STATUS_TX_FINISH 0x08 231#define CIR_STATUS_TX_UNDERRUN 0x04 232#define CIR_STATUS_RX_TIMEOUT 0x02 233#define CIR_STATUS_RX_RECEIVE 0x01 234#define CIR_STATUS_IRQ_MASK 0x0f 235 236/* 237 * CIR TX control register (0x02): 238 * 7 - TX_START (1 to indicate TX start, auto-cleared when done) 239 * 6 - TX_END (1 to indicate TX data written to TX fifo) 240 */ 241#define CIR_TX_CONTROL_TX_START 0x80 242#define CIR_TX_CONTROL_TX_END 0x40 243 244