11577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming/* 21577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * Freescale PowerQUICC MDIO Driver -- MII Management Bus Implementation 31577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * Driver for the MDIO bus controller on Freescale PowerQUICC processors 41577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * 51577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * Author: Andy Fleming 61d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet * Modifier: Sandeep Gopalpet 71577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * 81d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. 91577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * 101577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * This program is free software; you can redistribute it and/or modify it 111577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * under the terms of the GNU General Public License as published by the 121577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * Free Software Foundation; either version 2 of the License, or (at your 131577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * option) any later version. 141577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming * 151577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming */ 161577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#ifndef __FSL_PQ_MDIO_H 171577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#define __FSL_PQ_MDIO_H 181577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming 191577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#define MIIMIND_BUSY 0x00000001 201577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#define MIIMIND_NOTVALID 0x00000004 211577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#define MIIMCFG_INIT_VALUE 0x00000007 221577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#define MIIMCFG_RESET 0x80000000 231577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming 241577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#define MII_READ_COMMAND 0x00000001 251577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming 261577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingstruct fsl_pq_mdio { 271d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u8 res1[16]; 281d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ 291d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ 301d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u8 res2[4]; 311d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u32 emapm; /* MDIO Event mapping register (for etsec2)*/ 321d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u8 res3[1280]; 331577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 miimcfg; /* MII management configuration reg */ 341577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 miimcom; /* MII management command reg */ 351577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 miimadd; /* MII management address reg */ 361577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 miimcon; /* MII management control reg */ 371577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 miimstat; /* MII management status reg */ 381577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 miimind; /* MII management indication reg */ 391577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u8 reserved[28]; /* Space holder */ 401577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming u32 utbipar; /* TBI phy address reg (only on UCC) */ 411d2397d742b7a2b39b2f09dd9da3b9d1463f55e9Sandeep Gopalpet u8 res4[2728]; 42ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 431577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming 441577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingint fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum); 451577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingint fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value); 461577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingint fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id, 471577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming int regnum, u16 value); 481577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingint fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, int mii_id, int regnum); 491577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingint __init fsl_pq_mdio_init(void); 501577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingvoid fsl_pq_mdio_exit(void); 511577ecef766650a57fceb171acee2b13cbfaf1d3Andy Flemingvoid fsl_pq_mdio_bus_name(char *name, struct device_node *np); 521577ecef766650a57fceb171acee2b13cbfaf1d3Andy Fleming#endif /* FSL_PQ_MDIO_H */ 53