1/* 2 * linux/drivers/acorn/net/ether1.h 3 * 4 * Copyright (C) 1996 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Network driver for Acorn Ether1 cards. 11 */ 12 13#ifndef _LINUX_ether1_H 14#define _LINUX_ether1_H 15 16#ifdef __ETHER1_C 17/* use 0 for production, 1 for verification, >2 for debug */ 18#ifndef NET_DEBUG 19#define NET_DEBUG 0 20#endif 21 22#define priv(dev) ((struct ether1_priv *)netdev_priv(dev)) 23 24/* Page register */ 25#define REG_PAGE (priv(dev)->base + 0x0000) 26 27/* Control register */ 28#define REG_CONTROL (priv(dev)->base + 0x0004) 29#define CTRL_RST 0x01 30#define CTRL_LOOPBACK 0x02 31#define CTRL_CA 0x04 32#define CTRL_ACK 0x08 33 34#define ETHER1_RAM (priv(dev)->base + 0x2000) 35 36/* HW address */ 37#define IDPROM_ADDRESS (priv(dev)->base + 0x0024) 38 39struct ether1_priv { 40 void __iomem *base; 41 unsigned int tx_link; 42 unsigned int tx_head; 43 volatile unsigned int tx_tail; 44 volatile unsigned int rx_head; 45 volatile unsigned int rx_tail; 46 unsigned char bus_type; 47 unsigned char resetting; 48 unsigned char initialising : 1; 49 unsigned char restart : 1; 50}; 51 52#define I82586_NULL (-1) 53 54typedef struct { /* tdr */ 55 unsigned short tdr_status; 56 unsigned short tdr_command; 57 unsigned short tdr_link; 58 unsigned short tdr_result; 59#define TDR_TIME (0x7ff) 60#define TDR_SHORT (1 << 12) 61#define TDR_OPEN (1 << 13) 62#define TDR_XCVRPROB (1 << 14) 63#define TDR_LNKOK (1 << 15) 64} tdr_t; 65 66typedef struct { /* transmit */ 67 unsigned short tx_status; 68 unsigned short tx_command; 69 unsigned short tx_link; 70 unsigned short tx_tbdoffset; 71} tx_t; 72 73typedef struct { /* tbd */ 74 unsigned short tbd_opts; 75#define TBD_CNT (0x3fff) 76#define TBD_EOL (1 << 15) 77 unsigned short tbd_link; 78 unsigned short tbd_bufl; 79 unsigned short tbd_bufh; 80} tbd_t; 81 82typedef struct { /* rfd */ 83 unsigned short rfd_status; 84#define RFD_NOEOF (1 << 6) 85#define RFD_FRAMESHORT (1 << 7) 86#define RFD_DMAOVRN (1 << 8) 87#define RFD_NORESOURCES (1 << 9) 88#define RFD_ALIGNERROR (1 << 10) 89#define RFD_CRCERROR (1 << 11) 90#define RFD_OK (1 << 13) 91#define RFD_FDCONSUMED (1 << 14) 92#define RFD_COMPLETE (1 << 15) 93 unsigned short rfd_command; 94#define RFD_CMDSUSPEND (1 << 14) 95#define RFD_CMDEL (1 << 15) 96 unsigned short rfd_link; 97 unsigned short rfd_rbdoffset; 98 unsigned char rfd_dest[6]; 99 unsigned char rfd_src[6]; 100 unsigned short rfd_len; 101} rfd_t; 102 103typedef struct { /* rbd */ 104 unsigned short rbd_status; 105#define RBD_ACNT (0x3fff) 106#define RBD_ACNTVALID (1 << 14) 107#define RBD_EOF (1 << 15) 108 unsigned short rbd_link; 109 unsigned short rbd_bufl; 110 unsigned short rbd_bufh; 111 unsigned short rbd_len; 112} rbd_t; 113 114typedef struct { /* nop */ 115 unsigned short nop_status; 116 unsigned short nop_command; 117 unsigned short nop_link; 118} nop_t; 119 120typedef struct { /* set multicast */ 121 unsigned short mc_status; 122 unsigned short mc_command; 123 unsigned short mc_link; 124 unsigned short mc_cnt; 125 unsigned char mc_addrs[1][6]; 126} mc_t; 127 128typedef struct { /* set address */ 129 unsigned short sa_status; 130 unsigned short sa_command; 131 unsigned short sa_link; 132 unsigned char sa_addr[6]; 133} sa_t; 134 135typedef struct { /* config command */ 136 unsigned short cfg_status; 137 unsigned short cfg_command; 138 unsigned short cfg_link; 139 unsigned char cfg_bytecnt; /* size foll data: 4 - 12 */ 140 unsigned char cfg_fifolim; /* FIFO threshold */ 141 unsigned char cfg_byte8; 142#define CFG8_SRDY (1 << 6) 143#define CFG8_SAVEBADF (1 << 7) 144 unsigned char cfg_byte9; 145#define CFG9_ADDRLEN(x) (x) 146#define CFG9_ADDRLENBUF (1 << 3) 147#define CFG9_PREAMB2 (0 << 4) 148#define CFG9_PREAMB4 (1 << 4) 149#define CFG9_PREAMB8 (2 << 4) 150#define CFG9_PREAMB16 (3 << 4) 151#define CFG9_ILOOPBACK (1 << 6) 152#define CFG9_ELOOPBACK (1 << 7) 153 unsigned char cfg_byte10; 154#define CFG10_LINPRI(x) (x) 155#define CFG10_ACR(x) (x << 4) 156#define CFG10_BOFMET (1 << 7) 157 unsigned char cfg_ifs; 158 unsigned char cfg_slotl; 159 unsigned char cfg_byte13; 160#define CFG13_SLOTH(x) (x) 161#define CFG13_RETRY(x) (x << 4) 162 unsigned char cfg_byte14; 163#define CFG14_PROMISC (1 << 0) 164#define CFG14_DISBRD (1 << 1) 165#define CFG14_MANCH (1 << 2) 166#define CFG14_TNCRS (1 << 3) 167#define CFG14_NOCRC (1 << 4) 168#define CFG14_CRC16 (1 << 5) 169#define CFG14_BTSTF (1 << 6) 170#define CFG14_FLGPAD (1 << 7) 171 unsigned char cfg_byte15; 172#define CFG15_CSTF(x) (x) 173#define CFG15_ICSS (1 << 3) 174#define CFG15_CDTF(x) (x << 4) 175#define CFG15_ICDS (1 << 7) 176 unsigned short cfg_minfrmlen; 177} cfg_t; 178 179typedef struct { /* scb */ 180 unsigned short scb_status; /* status of 82586 */ 181#define SCB_STRXMASK (7 << 4) /* Receive unit status */ 182#define SCB_STRXIDLE (0 << 4) /* Idle */ 183#define SCB_STRXSUSP (1 << 4) /* Suspended */ 184#define SCB_STRXNRES (2 << 4) /* No resources */ 185#define SCB_STRXRDY (4 << 4) /* Ready */ 186#define SCB_STCUMASK (7 << 8) /* Command unit status */ 187#define SCB_STCUIDLE (0 << 8) /* Idle */ 188#define SCB_STCUSUSP (1 << 8) /* Suspended */ 189#define SCB_STCUACTV (2 << 8) /* Active */ 190#define SCB_STRNR (1 << 12) /* Receive unit not ready */ 191#define SCB_STCNA (1 << 13) /* Command unit not ready */ 192#define SCB_STFR (1 << 14) /* Frame received */ 193#define SCB_STCX (1 << 15) /* Command completed */ 194 unsigned short scb_command; /* Next command */ 195#define SCB_CMDRXSTART (1 << 4) /* Start (at rfa_offset) */ 196#define SCB_CMDRXRESUME (2 << 4) /* Resume reception */ 197#define SCB_CMDRXSUSPEND (3 << 4) /* Suspend reception */ 198#define SCB_CMDRXABORT (4 << 4) /* Abort reception */ 199#define SCB_CMDCUCSTART (1 << 8) /* Start (at cbl_offset) */ 200#define SCB_CMDCUCRESUME (2 << 8) /* Resume execution */ 201#define SCB_CMDCUCSUSPEND (3 << 8) /* Suspend execution */ 202#define SCB_CMDCUCABORT (4 << 8) /* Abort execution */ 203#define SCB_CMDACKRNR (1 << 12) /* Ack RU not ready */ 204#define SCB_CMDACKCNA (1 << 13) /* Ack CU not ready */ 205#define SCB_CMDACKFR (1 << 14) /* Ack Frame received */ 206#define SCB_CMDACKCX (1 << 15) /* Ack Command complete */ 207 unsigned short scb_cbl_offset; /* Offset of first command unit */ 208 unsigned short scb_rfa_offset; /* Offset of first receive frame area */ 209 unsigned short scb_crc_errors; /* Properly aligned frame with CRC error*/ 210 unsigned short scb_aln_errors; /* Misaligned frames */ 211 unsigned short scb_rsc_errors; /* Frames lost due to no space */ 212 unsigned short scb_ovn_errors; /* Frames lost due to slow bus */ 213} scb_t; 214 215typedef struct { /* iscp */ 216 unsigned short iscp_busy; /* set by CPU before CA */ 217 unsigned short iscp_offset; /* offset of SCB */ 218 unsigned short iscp_basel; /* base of SCB */ 219 unsigned short iscp_baseh; 220} iscp_t; 221 222 /* this address must be 0xfff6 */ 223typedef struct { /* scp */ 224 unsigned short scp_sysbus; /* bus size */ 225#define SCP_SY_16BBUS 0x00 226#define SCP_SY_8BBUS 0x01 227 unsigned short scp_junk[2]; /* junk */ 228 unsigned short scp_iscpl; /* lower 16 bits of iscp */ 229 unsigned short scp_iscph; /* upper 16 bits of iscp */ 230} scp_t; 231 232/* commands */ 233#define CMD_NOP 0 234#define CMD_SETADDRESS 1 235#define CMD_CONFIG 2 236#define CMD_SETMULTICAST 3 237#define CMD_TX 4 238#define CMD_TDR 5 239#define CMD_DUMP 6 240#define CMD_DIAGNOSE 7 241 242#define CMD_MASK 7 243 244#define CMD_INTR (1 << 13) 245#define CMD_SUSP (1 << 14) 246#define CMD_EOL (1 << 15) 247 248#define STAT_COLLISIONS (15) 249#define STAT_COLLEXCESSIVE (1 << 5) 250#define STAT_COLLAFTERTX (1 << 6) 251#define STAT_TXDEFERRED (1 << 7) 252#define STAT_TXSLOWDMA (1 << 8) 253#define STAT_TXLOSTCTS (1 << 9) 254#define STAT_NOCARRIER (1 << 10) 255#define STAT_FAIL (1 << 11) 256#define STAT_ABORTED (1 << 12) 257#define STAT_OK (1 << 13) 258#define STAT_BUSY (1 << 14) 259#define STAT_COMPLETE (1 << 15) 260#endif 261#endif 262 263/* 264 * Ether1 card definitions: 265 * 266 * FAST accesses: 267 * +0 Page register 268 * 16 pages 269 * +4 Control 270 * '1' = reset 271 * '2' = loopback 272 * '4' = CA 273 * '8' = int ack 274 * 275 * RAM at address + 0x2000 276 * Pod. Prod id = 3 277 * Words after ID block [base + 8 words] 278 * +0 pcb issue (0x0c and 0xf3 invalid) 279 * +1 - +6 eth hw address 280 */ 281