1/* 2 * Copyright (c) 2004 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36#include <linux/gfp.h> 37#include <linux/export.h> 38#include <linux/init.h> 39 40#include <linux/mlx4/cmd.h> 41#include <linux/mlx4/qp.h> 42 43#include "mlx4.h" 44#include "icm.h" 45 46void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type) 47{ 48 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 49 struct mlx4_qp *qp; 50 51 spin_lock(&qp_table->lock); 52 53 qp = __mlx4_qp_lookup(dev, qpn); 54 if (qp) 55 atomic_inc(&qp->refcount); 56 57 spin_unlock(&qp_table->lock); 58 59 if (!qp) { 60 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn); 61 return; 62 } 63 64 qp->event(qp, event_type); 65 66 if (atomic_dec_and_test(&qp->refcount)) 67 complete(&qp->free); 68} 69 70static int is_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp) 71{ 72 return qp->qpn >= dev->caps.sqp_start && 73 qp->qpn <= dev->caps.sqp_start + 1; 74} 75 76static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 77 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 78 struct mlx4_qp_context *context, 79 enum mlx4_qp_optpar optpar, 80 int sqd_event, struct mlx4_qp *qp, int native) 81{ 82 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = { 83 [MLX4_QP_STATE_RST] = { 84 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 85 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 86 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP, 87 }, 88 [MLX4_QP_STATE_INIT] = { 89 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 90 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 91 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP, 92 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP, 93 }, 94 [MLX4_QP_STATE_RTR] = { 95 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 96 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 97 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP, 98 }, 99 [MLX4_QP_STATE_RTS] = { 100 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 101 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 102 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP, 103 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP, 104 }, 105 [MLX4_QP_STATE_SQD] = { 106 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 107 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 108 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP, 109 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP, 110 }, 111 [MLX4_QP_STATE_SQER] = { 112 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 113 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 114 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP, 115 }, 116 [MLX4_QP_STATE_ERR] = { 117 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 118 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 119 } 120 }; 121 122 struct mlx4_priv *priv = mlx4_priv(dev); 123 struct mlx4_cmd_mailbox *mailbox; 124 int ret = 0; 125 u8 port; 126 127 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE || 128 !op[cur_state][new_state]) 129 return -EINVAL; 130 131 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) { 132 ret = mlx4_cmd(dev, 0, qp->qpn, 2, 133 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native); 134 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR && 135 cur_state != MLX4_QP_STATE_RST && 136 is_qp0(dev, qp)) { 137 port = (qp->qpn & 1) + 1; 138 priv->mfunc.master.qp0_state[port].qp0_active = 0; 139 } 140 return ret; 141 } 142 143 mailbox = mlx4_alloc_cmd_mailbox(dev); 144 if (IS_ERR(mailbox)) 145 return PTR_ERR(mailbox); 146 147 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) { 148 u64 mtt_addr = mlx4_mtt_addr(dev, mtt); 149 context->mtt_base_addr_h = mtt_addr >> 32; 150 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 151 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; 152 } 153 154 port = ((context->pri_path.sched_queue >> 6) & 1) + 1; 155 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 156 context->pri_path.sched_queue = (context->pri_path.sched_queue & 157 0xc3); 158 159 *(__be32 *) mailbox->buf = cpu_to_be32(optpar); 160 memcpy(mailbox->buf + 8, context, sizeof *context); 161 162 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn = 163 cpu_to_be32(qp->qpn); 164 165 ret = mlx4_cmd(dev, mailbox->dma, 166 qp->qpn | (!!sqd_event << 31), 167 new_state == MLX4_QP_STATE_RST ? 2 : 0, 168 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native); 169 170 mlx4_free_cmd_mailbox(dev, mailbox); 171 return ret; 172} 173 174int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 175 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 176 struct mlx4_qp_context *context, 177 enum mlx4_qp_optpar optpar, 178 int sqd_event, struct mlx4_qp *qp) 179{ 180 return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context, 181 optpar, sqd_event, qp, 0); 182} 183EXPORT_SYMBOL_GPL(mlx4_qp_modify); 184 185int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 186 int *base) 187{ 188 struct mlx4_priv *priv = mlx4_priv(dev); 189 struct mlx4_qp_table *qp_table = &priv->qp_table; 190 191 *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align); 192 if (*base == -1) 193 return -ENOMEM; 194 195 return 0; 196} 197 198int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base) 199{ 200 u64 in_param; 201 u64 out_param; 202 int err; 203 204 if (mlx4_is_mfunc(dev)) { 205 set_param_l(&in_param, cnt); 206 set_param_h(&in_param, align); 207 err = mlx4_cmd_imm(dev, in_param, &out_param, 208 RES_QP, RES_OP_RESERVE, 209 MLX4_CMD_ALLOC_RES, 210 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 211 if (err) 212 return err; 213 214 *base = get_param_l(&out_param); 215 return 0; 216 } 217 return __mlx4_qp_reserve_range(dev, cnt, align, base); 218} 219EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range); 220 221void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) 222{ 223 struct mlx4_priv *priv = mlx4_priv(dev); 224 struct mlx4_qp_table *qp_table = &priv->qp_table; 225 226 if (mlx4_is_qp_reserved(dev, (u32) base_qpn)) 227 return; 228 mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt); 229} 230 231void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) 232{ 233 u64 in_param; 234 int err; 235 236 if (mlx4_is_mfunc(dev)) { 237 set_param_l(&in_param, base_qpn); 238 set_param_h(&in_param, cnt); 239 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE, 240 MLX4_CMD_FREE_RES, 241 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 242 if (err) { 243 mlx4_warn(dev, "Failed to release qp range" 244 " base:%d cnt:%d\n", base_qpn, cnt); 245 } 246 } else 247 __mlx4_qp_release_range(dev, base_qpn, cnt); 248} 249EXPORT_SYMBOL_GPL(mlx4_qp_release_range); 250 251int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn) 252{ 253 struct mlx4_priv *priv = mlx4_priv(dev); 254 struct mlx4_qp_table *qp_table = &priv->qp_table; 255 int err; 256 257 err = mlx4_table_get(dev, &qp_table->qp_table, qpn); 258 if (err) 259 goto err_out; 260 261 err = mlx4_table_get(dev, &qp_table->auxc_table, qpn); 262 if (err) 263 goto err_put_qp; 264 265 err = mlx4_table_get(dev, &qp_table->altc_table, qpn); 266 if (err) 267 goto err_put_auxc; 268 269 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn); 270 if (err) 271 goto err_put_altc; 272 273 err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn); 274 if (err) 275 goto err_put_rdmarc; 276 277 return 0; 278 279err_put_rdmarc: 280 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); 281 282err_put_altc: 283 mlx4_table_put(dev, &qp_table->altc_table, qpn); 284 285err_put_auxc: 286 mlx4_table_put(dev, &qp_table->auxc_table, qpn); 287 288err_put_qp: 289 mlx4_table_put(dev, &qp_table->qp_table, qpn); 290 291err_out: 292 return err; 293} 294 295static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn) 296{ 297 u64 param; 298 299 if (mlx4_is_mfunc(dev)) { 300 set_param_l(¶m, qpn); 301 return mlx4_cmd_imm(dev, param, ¶m, RES_QP, RES_OP_MAP_ICM, 302 MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A, 303 MLX4_CMD_WRAPPED); 304 } 305 return __mlx4_qp_alloc_icm(dev, qpn); 306} 307 308void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) 309{ 310 struct mlx4_priv *priv = mlx4_priv(dev); 311 struct mlx4_qp_table *qp_table = &priv->qp_table; 312 313 mlx4_table_put(dev, &qp_table->cmpt_table, qpn); 314 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); 315 mlx4_table_put(dev, &qp_table->altc_table, qpn); 316 mlx4_table_put(dev, &qp_table->auxc_table, qpn); 317 mlx4_table_put(dev, &qp_table->qp_table, qpn); 318} 319 320static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) 321{ 322 u64 in_param; 323 324 if (mlx4_is_mfunc(dev)) { 325 set_param_l(&in_param, qpn); 326 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM, 327 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 328 MLX4_CMD_WRAPPED)) 329 mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn); 330 } else 331 __mlx4_qp_free_icm(dev, qpn); 332} 333 334int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp) 335{ 336 struct mlx4_priv *priv = mlx4_priv(dev); 337 struct mlx4_qp_table *qp_table = &priv->qp_table; 338 int err; 339 340 if (!qpn) 341 return -EINVAL; 342 343 qp->qpn = qpn; 344 345 err = mlx4_qp_alloc_icm(dev, qpn); 346 if (err) 347 return err; 348 349 spin_lock_irq(&qp_table->lock); 350 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn & 351 (dev->caps.num_qps - 1), qp); 352 spin_unlock_irq(&qp_table->lock); 353 if (err) 354 goto err_icm; 355 356 atomic_set(&qp->refcount, 1); 357 init_completion(&qp->free); 358 359 return 0; 360 361err_icm: 362 mlx4_qp_free_icm(dev, qpn); 363 return err; 364} 365 366EXPORT_SYMBOL_GPL(mlx4_qp_alloc); 367 368void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp) 369{ 370 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 371 unsigned long flags; 372 373 spin_lock_irqsave(&qp_table->lock, flags); 374 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); 375 spin_unlock_irqrestore(&qp_table->lock, flags); 376} 377EXPORT_SYMBOL_GPL(mlx4_qp_remove); 378 379void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp) 380{ 381 if (atomic_dec_and_test(&qp->refcount)) 382 complete(&qp->free); 383 wait_for_completion(&qp->free); 384 385 mlx4_qp_free_icm(dev, qp->qpn); 386} 387EXPORT_SYMBOL_GPL(mlx4_qp_free); 388 389static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn) 390{ 391 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP, 392 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 393} 394 395int mlx4_init_qp_table(struct mlx4_dev *dev) 396{ 397 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 398 int err; 399 int reserved_from_top = 0; 400 401 spin_lock_init(&qp_table->lock); 402 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC); 403 if (mlx4_is_slave(dev)) 404 return 0; 405 406 /* 407 * We reserve 2 extra QPs per port for the special QPs. The 408 * block of special QPs must be aligned to a multiple of 8, so 409 * round up. 410 * 411 * We also reserve the MSB of the 24-bit QP number to indicate 412 * that a QP is an XRC QP. 413 */ 414 dev->caps.sqp_start = 415 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8); 416 417 { 418 int sort[MLX4_NUM_QP_REGION]; 419 int i, j, tmp; 420 int last_base = dev->caps.num_qps; 421 422 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) 423 sort[i] = i; 424 425 for (i = MLX4_NUM_QP_REGION; i > 0; --i) { 426 for (j = 2; j < i; ++j) { 427 if (dev->caps.reserved_qps_cnt[sort[j]] > 428 dev->caps.reserved_qps_cnt[sort[j - 1]]) { 429 tmp = sort[j]; 430 sort[j] = sort[j - 1]; 431 sort[j - 1] = tmp; 432 } 433 } 434 } 435 436 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) { 437 last_base -= dev->caps.reserved_qps_cnt[sort[i]]; 438 dev->caps.reserved_qps_base[sort[i]] = last_base; 439 reserved_from_top += 440 dev->caps.reserved_qps_cnt[sort[i]]; 441 } 442 443 } 444 445 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps, 446 (1 << 23) - 1, dev->caps.sqp_start + 8, 447 reserved_from_top); 448 if (err) 449 return err; 450 451 return mlx4_CONF_SPECIAL_QP(dev, dev->caps.sqp_start); 452} 453 454void mlx4_cleanup_qp_table(struct mlx4_dev *dev) 455{ 456 if (mlx4_is_slave(dev)) 457 return; 458 459 mlx4_CONF_SPECIAL_QP(dev, 0); 460 mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap); 461} 462 463int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 464 struct mlx4_qp_context *context) 465{ 466 struct mlx4_cmd_mailbox *mailbox; 467 int err; 468 469 mailbox = mlx4_alloc_cmd_mailbox(dev); 470 if (IS_ERR(mailbox)) 471 return PTR_ERR(mailbox); 472 473 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0, 474 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A, 475 MLX4_CMD_WRAPPED); 476 if (!err) 477 memcpy(context, mailbox->buf + 8, sizeof *context); 478 479 mlx4_free_cmd_mailbox(dev, mailbox); 480 return err; 481} 482EXPORT_SYMBOL_GPL(mlx4_qp_query); 483 484int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 485 struct mlx4_qp_context *context, 486 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state) 487{ 488 int err; 489 int i; 490 enum mlx4_qp_state states[] = { 491 MLX4_QP_STATE_RST, 492 MLX4_QP_STATE_INIT, 493 MLX4_QP_STATE_RTR, 494 MLX4_QP_STATE_RTS 495 }; 496 497 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 498 context->flags &= cpu_to_be32(~(0xf << 28)); 499 context->flags |= cpu_to_be32(states[i + 1] << 28); 500 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1], 501 context, 0, 0, qp); 502 if (err) { 503 mlx4_err(dev, "Failed to bring QP to state: " 504 "%d with error: %d\n", 505 states[i + 1], err); 506 return err; 507 } 508 509 *qp_state = states[i + 1]; 510 } 511 512 return 0; 513} 514EXPORT_SYMBOL_GPL(mlx4_qp_to_ready); 515