adm8211.h revision cc0b88cf5ecf13cdd750f08e201ce8fadcdb601f
1cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#ifndef ADM8211_H 2cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_H 3cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 4cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* ADM8211 Registers */ 5cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 6cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CR32 (SIG) signature */ 7cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SIG1 0x82011317 /* ADM8211A */ 8cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SIG2 0x82111317 /* ADM8211B/ADM8211C */ 9cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 10cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_READ(r) ioread32(&priv->map->r) 11cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r) 12cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 13cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR (Host Control and Status Registers) */ 14cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_csr { 15cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 PAR; /* 0x00 CSR0 */ 16cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 FRCTL; /* 0x04 CSR0A */ 17cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TDR; /* 0x08 CSR1 */ 18cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WTDP; /* 0x0C CSR1A */ 19cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 RDR; /* 0x10 CSR2 */ 20cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WRDP; /* 0x14 CSR2A */ 21cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 RDB; /* 0x18 CSR3 */ 22cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TDBH; /* 0x1C CSR3A */ 23cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TDBD; /* 0x20 CSR4 */ 24cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TDBP; /* 0x24 CSR4A */ 25cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 STSR; /* 0x28 CSR5 */ 26cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TDBB; /* 0x2C CSR5A */ 27cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 NAR; /* 0x30 CSR6 */ 28cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CSR6A; /* reserved */ 29cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 IER; /* 0x38 CSR7 */ 30cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TKIPSCEP; /* 0x3C CSR7A */ 31cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 LPC; /* 0x40 CSR8 */ 32cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CSR_TEST1; /* 0x44 CSR8A */ 33cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 SPR; /* 0x48 CSR9 */ 34cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CSR_TEST0; /* 0x4C CSR9A */ 35cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WCSR; /* 0x50 CSR10 */ 36cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WPDR; /* 0x54 CSR10A */ 37cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 GPTMR; /* 0x58 CSR11 */ 38cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 GPIO; /* 0x5C CSR11A */ 39cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 BBPCTL; /* 0x60 CSR12 */ 40cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 SYNCTL; /* 0x64 CSR12A */ 41cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 PLCPHD; /* 0x68 CSR13 */ 42cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MMIWA; /* 0x6C CSR13A */ 43cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MMIRD0; /* 0x70 CSR14 */ 44cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MMIRD1; /* 0x74 CSR14A */ 45cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TXBR; /* 0x78 CSR15 */ 46cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 SYNDATA; /* 0x7C CSR15A */ 47cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 ALCS; /* 0x80 CSR16 */ 48cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TOFS2; /* 0x84 CSR17 */ 49cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CMDR; /* 0x88 CSR18 */ 50cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 PCIC; /* 0x8C CSR19 */ 51cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 PMCSR; /* 0x90 CSR20 */ 52cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 PAR0; /* 0x94 CSR21 */ 53cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 PAR1; /* 0x98 CSR22 */ 54cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MAR0; /* 0x9C CSR23 */ 55cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MAR1; /* 0xA0 CSR24 */ 56cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 ATIMDA0; /* 0xA4 CSR25 */ 57cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 ABDA1; /* 0xA8 CSR26 */ 58cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 BSSID0; /* 0xAC CSR27 */ 59cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TXLMT; /* 0xB0 CSR28 */ 60cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MIBCNT; /* 0xB4 CSR29 */ 61cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 BCNT; /* 0xB8 CSR30 */ 62cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TSFTH; /* 0xBC CSR31 */ 63cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TSC; /* 0xC0 CSR32 */ 64cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 SYNRF; /* 0xC4 CSR33 */ 65cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 BPLI; /* 0xC8 CSR34 */ 66cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CAP0; /* 0xCC CSR35 */ 67cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CAP1; /* 0xD0 CSR36 */ 68cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 RMD; /* 0xD4 CSR37 */ 69cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 CFPP; /* 0xD8 CSR38 */ 70cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TOFS0; /* 0xDC CSR39 */ 71cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TOFS1; /* 0xE0 CSR40 */ 72cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 IFST; /* 0xE4 CSR41 */ 73cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 RSPT; /* 0xE8 CSR42 */ 74cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 TSFTL; /* 0xEC CSR43 */ 75cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WEPCTL; /* 0xF0 CSR44 */ 76cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WESK; /* 0xF4 CSR45 */ 77cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 WEPCNT; /* 0xF8 CSR46 */ 78cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 MACTEST; /* 0xFC CSR47 */ 79cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 FER; /* 0x100 */ 80cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 FEMR; /* 0x104 */ 81cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 FPSR; /* 0x108 */ 82cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 FFER; /* 0x10C */ 83cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu} __attribute__ ((packed)); 84cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 85cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR0 - PAR (PCI Address Register) */ 86cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_MWIE (1 << 24) 87cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_MRLE (1 << 23) 88cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_MRME (1 << 21) 89cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_RAP ((1 << 18) | (1 << 17)) 90cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_CAL ((1 << 15) | (1 << 14)) 91cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_PBL 0x00003f00 92cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_BLE (1 << 7) 93cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_DSL 0x0000007c 94cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_BAR (1 << 1) 95cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_PAR_SWR (1 << 0) 96cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 97cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR1 - FRCTL (Frame Control Register) */ 98cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FRCTL_PWRMGT (1 << 31) 99cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FRCTL_MAXPSP (1 << 27) 100cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FRCTL_DRVPRSP (1 << 26) 101cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FRCTL_DRVBCON (1 << 25) 102cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FRCTL_AID 0x0000ffff 103cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FRCTL_AID_ON 0x0000c000 104cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 105cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR5 - STSR (Status Register) */ 106cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_PCF (1 << 31) 107cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_BCNTC (1 << 30) 108cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_GPINT (1 << 29) 109cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_LinkOff (1 << 28) 110cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_ATIMTC (1 << 27) 111cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TSFTF (1 << 26) 112cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TSCZ (1 << 25) 113cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_LinkOn (1 << 24) 114cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_SQL (1 << 23) 115cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_WEPTD (1 << 22) 116cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_ATIME (1 << 21) 117cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TBTT (1 << 20) 118cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_NISS (1 << 16) 119cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_AISS (1 << 15) 120cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TEIS (1 << 14) 121cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_FBE (1 << 13) 122cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_REIS (1 << 12) 123cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_GPTT (1 << 11) 124cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_RPS (1 << 8) 125cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_RDU (1 << 7) 126cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_RCI (1 << 6) 127cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TUF (1 << 5) 128cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TRT (1 << 4) 129cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TLT (1 << 3) 130cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TDU (1 << 2) 131cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TPS (1 << 1) 132cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_STSR_TCI (1 << 0) 133cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 134cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR6 - NAR (Network Access Register) */ 135cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_TXCF (1 << 31) 136cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_HF (1 << 30) 137cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_UTR (1 << 29) 138cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_SQ (1 << 28) 139cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_CFP (1 << 27) 140cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_SF (1 << 21) 141cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_TR ((1 << 15) | (1 << 14)) 142cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_ST (1 << 13) 143cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_OM ((1 << 11) | (1 << 10)) 144cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_MM (1 << 7) 145cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_PR (1 << 6) 146cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_EA (1 << 5) 147cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_PB (1 << 3) 148cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_STPDMA (1 << 2) 149cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_SR (1 << 1) 150cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_NAR_CTX (1 << 0) 151cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 152cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IDLE() \ 153cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wudo { \ 154cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) { \ 155cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_CSR_WRITE(NAR, priv->nar & \ 156cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ~(ADM8211_NAR_SR | ADM8211_NAR_ST));\ 157cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_CSR_READ(NAR); \ 158cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu msleep(20); \ 159cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu } \ 160cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu} while (0) 161cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 162cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IDLE_RX() \ 163cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wudo { \ 164cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu if (priv->nar & ADM8211_NAR_SR) { \ 165cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_CSR_WRITE(NAR, priv->nar & ~ADM8211_NAR_SR); \ 166cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_CSR_READ(NAR); \ 167cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu mdelay(20); \ 168cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu } \ 169cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu} while (0) 170cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 171cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_RESTORE() \ 172cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wudo { \ 173cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) \ 174cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_CSR_WRITE(NAR, priv->nar); \ 175cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu} while (0) 176cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 177cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR7 - IER (Interrupt Enable Register) */ 178cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_PCFIE (1 << 31) 179cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_BCNTCIE (1 << 30) 180cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_GPIE (1 << 29) 181cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_LinkOffIE (1 << 28) 182cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_ATIMTCIE (1 << 27) 183cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TSFTFIE (1 << 26) 184cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TSCZE (1 << 25) 185cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_LinkOnIE (1 << 24) 186cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_SQLIE (1 << 23) 187cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_WEPIE (1 << 22) 188cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_ATIMEIE (1 << 21) 189cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TBTTIE (1 << 20) 190cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_NIE (1 << 16) 191cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_AIE (1 << 15) 192cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TEIE (1 << 14) 193cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_FBEIE (1 << 13) 194cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_REIE (1 << 12) 195cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_GPTIE (1 << 11) 196cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_RSIE (1 << 8) 197cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_RUIE (1 << 7) 198cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_RCIE (1 << 6) 199cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TUIE (1 << 5) 200cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TRTIE (1 << 4) 201cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TLTTIE (1 << 3) 202cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TDUIE (1 << 2) 203cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TPSIE (1 << 1) 204cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_IER_TCIE (1 << 0) 205cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 206cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR9 - SPR (Serial Port Register) */ 207cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SPR_SRS (1 << 11) 208cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SPR_SDO (1 << 3) 209cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SPR_SDI (1 << 2) 210cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SPR_SCLK (1 << 1) 211cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SPR_SCS (1 << 0) 212cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 213cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR9A - CSR_TEST0 */ 214cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_TEST0_EPNE (1 << 18) 215cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_TEST0_EPSNM (1 << 17) 216cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_TEST0_EPTYP (1 << 16) 217cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_TEST0_EPRLD (1 << 15) 218cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 219cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR10 - WCSR (Wake-up Control/Status Register) */ 220cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_CRCT (1 << 30) 221cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_TSFTWE (1 << 20) 222cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_TIMWE (1 << 19) 223cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_ATIMWE (1 << 18) 224cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_KEYWE (1 << 17) 225cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_MPRE (1 << 9) 226cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_LSOE (1 << 8) 227cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_KEYUP (1 << 6) 228cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_TSFTW (1 << 5) 229cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_TIMW (1 << 4) 230cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_ATIMW (1 << 3) 231cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_MPR (1 << 1) 232cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WCSR_LSO (1 << 0) 233cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 234cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR11A - GPIO */ 235cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_EN5 (1 << 17) 236cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_EN4 (1 << 16) 237cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_EN3 (1 << 15) 238cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_EN2 (1 << 14) 239cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_EN1 (1 << 13) 240cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_EN0 (1 << 12) 241cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_O5 (1 << 11) 242cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_O4 (1 << 10) 243cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_O3 (1 << 9) 244cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_O2 (1 << 8) 245cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_O1 (1 << 7) 246cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_O0 (1 << 6) 247cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CSR_GPIO_IN 0x0000003f 248cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 249cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR12 - BBPCTL (BBP Control port) */ 250cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_MMISEL (1 << 31) 251cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_SPICADD (0x7F << 24) 252cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_RF3000 (0x20 << 24) 253cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_TXCE (1 << 23) 254cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_RXCE (1 << 22) 255cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_CCAP (1 << 21) 256cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_TYPE 0x001c0000 257cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_WR (1 << 17) 258cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_RD (1 << 16) 259cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_ADDR 0x0000ff00 260cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBPCTL_DATA 0x000000ff 261cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 262cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR12A - SYNCTL (Synthesizer Control port) */ 263cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_WR (1 << 31) 264cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_RD (1 << 30) 265cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_CS0 (1 << 29) 266cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_CS1 (1 << 28) 267cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_CAL (1 << 27) 268cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_SELCAL (1 << 26) 269cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_RFtype ((1 << 24) || (1 << 23) || (1 << 22)) 270cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_RFMD (1 << 22) 271cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNCTL_GENERAL (0x7 << 22) 272cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* SYNCTL 21:0 Data (Si4126: 18-bit data, 4-bit address) */ 273cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 274cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR18 - CMDR (Command Register) */ 275cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_PM (1 << 19) 276cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_APM (1 << 18) 277cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_RTE (1 << 4) 278cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_DRT ((1 << 3) | (1 << 2)) 279cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_DRT_8DW (0x0 << 2) 280cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_DRT_16DW (0x1 << 2) 281cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_CMDR_DRT_SF (0x2 << 2) 282cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 283cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR33 - SYNRF (SYNRF direct control) */ 284cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_SELSYN (1 << 31) 285cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_SELRF (1 << 30) 286cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_LERF (1 << 29) 287cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_LEIF (1 << 28) 288cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_SYNCLK (1 << 27) 289cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_SYNDATA (1 << 26) 290cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_PE1 (1 << 25) 291cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_PE2 (1 << 24) 292cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_PA_PE (1 << 23) 293cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_TR_SW (1 << 22) 294cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_TR_SWN (1 << 21) 295cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_RADIO (1 << 20) 296cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_CAL_EN (1 << 19) 297cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_PHYRST (1 << 18) 298cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 299cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_IF_SELECT_0 (1 << 31) 300cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_IF_SELECT_1 ((1 << 31) | (1 << 28)) 301cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_WRITE_SYNDATA_0 (1 << 31) 302cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_WRITE_SYNDATA_1 ((1 << 31) | (1 << 26)) 303cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_WRITE_CLOCK_0 (1 << 31) 304cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SYNRF_WRITE_CLOCK_1 ((1 << 31) | (1 << 27)) 305cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 306cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR44 - WEPCTL (WEP Control) */ 307cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_WEPENABLE (1 << 31) 308cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_WPAENABLE (1 << 30) 309cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_CURRENT_TABLE (1 << 29) 310cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_TABLE_WR (1 << 28) 311cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_TABLE_RD (1 << 27) 312cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_WEPRXBYP (1 << 25) 313cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_SEL_WEPTABLE (1 << 23) 314cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WEPCTL_ADDR (0x000001ff) 315cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 316cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* CSR45 - WESK (Data Entry for Share/Individual Key) */ 317cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_WESK_DATA (0x0000ffff) 318cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 319cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* FER (Function Event Register) */ 320cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_FER_INTR_EV_ENT (1 << 15) 321cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 322cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 323cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* Si4126 RF Synthesizer - Control Registers */ 324cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_MAIN_CONF 0 325cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_PHASE_DET_GAIN 1 326cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_POWERDOWN 2 327cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_RF1_N_DIV 3 /* only Si4136 */ 328cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_RF2_N_DIV 4 329cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_IF_N_DIV 5 330cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_RF1_R_DIV 6 /* only Si4136 */ 331cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_RF2_R_DIV 7 332cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_IF_R_DIV 8 333cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 334cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* Main Configuration */ 335cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_MAIN_XINDIV2 (1 << 6) 336cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_MAIN_IFDIV ((1 << 11) | (1 << 10)) 337cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* Powerdown */ 338cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_POWERDOWN_PDIB (1 << 1) 339cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define SI4126_POWERDOWN_PDRB (1 << 0) 340cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 341cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 342cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* RF3000 BBP - Control Port Registers */ 343cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* 0x00 - reserved */ 344cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_MODEM_CTRL__RX_STATUS 0x01 345cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_CCA_CTRL 0x02 346cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_DIVERSITY__RSSI 0x03 347cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_RX_SIGNAL_FIELD 0x04 348cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_RX_LEN_MSB 0x05 349cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_RX_LEN_LSB 0x06 350cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_RX_SERVICE_FIELD 0x07 351cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11 352cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_TX_LEN_MSB 0x12 353cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_TX_LEN_LSB 0x13 354cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_LOW_GAIN_CALIB 0x14 355cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RF3000_HIGH_GAIN_CALIB 0x15 356cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 357cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* ADM8211 revisions */ 358cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_REV_AB 0x11 359cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_REV_AF 0x15 360cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_REV_BA 0x20 361cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_REV_CA 0x30 362cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 363cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_desc { 364cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 status; 365cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 length; 366cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 buffer1; 367cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le32 buffer2; 368cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 369cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 370cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_OWN (1 << 31) 371cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_ES (1 << 30) 372cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_SQL (1 << 29) 373cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_DE (1 << 28) 374cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_FS (1 << 27) 375cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_LS (1 << 26) 376cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_PCF (1 << 25) 377cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_SFDE (1 << 24) 378cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_SIGE (1 << 23) 379cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_CRC16E (1 << 22) 380cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_RXTOE (1 << 21) 381cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_CRC32E (1 << 20) 382cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_ICVE (1 << 19) 383cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_DA1 (1 << 17) 384cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_DA0 (1 << 16) 385cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_RXDR ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12)) 386cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES0_STATUS_FL (0x00000fff) 387cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 388cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES1_CONTROL_RER (1 << 25) 389cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES1_CONTROL_RCH (1 << 24) 390cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES1_CONTROL_RBS2 (0x00fff000) 391cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES1_CONTROL_RBS1 (0x00000fff) 392cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 393cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RDES1_STATUS_RSSI (0x0000007f) 394cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 395cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 396cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_CONTROL_OWN (1 << 31) 397cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_CONTROL_DONE (1 << 30) 398cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_CONTROL_TXDR (0x0ff00000) 399cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 400cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_OWN (1 << 31) 401cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_DONE (1 << 30) 402cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_ES (1 << 29) 403cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_TLT (1 << 28) 404cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_TRT (1 << 27) 405cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_TUF (1 << 26) 406cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_TRO (1 << 25) 407cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_SOFBR (1 << 24) 408cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES0_STATUS_ACR (0x00000fff) 409cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 410cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_IC (1 << 31) 411cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_LS (1 << 30) 412cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_FS (1 << 29) 413cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_TER (1 << 25) 414cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_TCH (1 << 24) 415cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_RBS2 (0x00fff000) 416cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define TDES1_CONTROL_RBS1 (0x00000fff) 417cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 418cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* SRAM offsets */ 419cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM(x) (priv->revid < ADM8211_REV_BA ? \ 420cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x) 421cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 422cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_INDIV_KEY 0x0000 423cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_A_SHARE_KEY 0x0160 424cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_B_SHARE_KEY 0x00c0 425cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 426cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_A_SSID 0x0180 427cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_B_SSID 0x00d4 428cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_SSID ADM8211_SRAM(SSID) 429cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 430cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_A_SUPP_RATE 0x0191 431cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_B_SUPP_RATE 0x00dd 432cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE) 433cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 434cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_A_SIZE 0x0200 435cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_B_SIZE 0x01c0 436cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE) 437cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 438cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_rx_ring_info { 439cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct sk_buff *skb; 440cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu dma_addr_t mapping; 441cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 442cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 443cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_tx_ring_info { 444cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct sk_buff *skb; 445cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu dma_addr_t mapping; 446cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct ieee80211_tx_control tx_control; 447cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu size_t hdrlen; 448cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 449cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 450cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define PLCP_SIGNAL_1M 0x0a 451cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define PLCP_SIGNAL_2M 0x14 452cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define PLCP_SIGNAL_5M5 0x37 453cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define PLCP_SIGNAL_11M 0x6e 454cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 455cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_tx_hdr { 456cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 da[6]; 457cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 signal; /* PLCP signal / TX rate in 100 Kbps */ 458cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 service; 459cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 frame_body_size; 460cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 frame_control; 461cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 plcp_frag_tail_len; 462cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 plcp_frag_head_len; 463cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 dur_frag_tail; 464cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 dur_frag_head; 465cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 addr4[6]; 466cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 467cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_SHORT_PREAMBLE (1 << 0) 468cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_MORE_FRAG (1 << 1) 469cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_MORE_DATA (1 << 2) 470cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_FRAG_NO (1 << 3) /* ? */ 471cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_ENABLE_RTS (1 << 4) 472cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE (1 << 5) 473cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER (1 << 15) /* ? */ 474cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 header_control; 475cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 frag; 476cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 reserved_0; 477cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 retry_limit; 478cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 479cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u32 wep2key0; 480cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u32 wep2key1; 481cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u32 wep2key2; 482cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u32 wep2key3; 483cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 484cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 keyid; 485cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 entry_control; // huh?? 486cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u16 reserved_1; 487cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u32 reserved_2; 488cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu} __attribute__ ((packed)); 489cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 490cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 491cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RX_COPY_BREAK 128 492cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define RX_PKT_SIZE 2500 493cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 494cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_eeprom { 495cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 signature; /* 0x00 */ 496cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 major_version; /* 0x02 */ 497cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 minor_version; /* 0x03 */ 498cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 reserved_1[4]; /* 0x04 */ 499cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 hwaddr[6]; /* 0x08 */ 500cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 reserved_2[8]; /* 0x1E */ 501cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 cr49; /* 0x16 */ 502cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 cr03; /* 0x18 */ 503cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 cr28; /* 0x19 */ 504cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 cr29; /* 0x1A */ 505cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 country_code; /* 0x1B */ 506cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 507cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu/* specific bbp types */ 508cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBP_RFMD3000 0x00 509cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBP_RFMD3002 0x01 510cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_BBP_ADM8011 0x04 511cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 specific_bbptype; /* 0x1C */ 512cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 specific_rftype; /* 0x1D */ 513cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 reserved_3[2]; /* 0x1E */ 514cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 device_id; /* 0x20 */ 515cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 vendor_id; /* 0x22 */ 516cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 subsystem_id; /* 0x24 */ 517cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 subsystem_vendor_id; /* 0x26 */ 518cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 maxlat; /* 0x28 */ 519cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 mingnt; /* 0x29 */ 520cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 cis_pointer_low; /* 0x2A */ 521cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 cis_pointer_high; /* 0x2C */ 522cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 csr18; /* 0x2E */ 523cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 reserved_4[16]; /* 0x30 */ 524cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 d1_pwrdara; /* 0x40 */ 525cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 d0_pwrdara; /* 0x41 */ 526cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 d3_pwrdara; /* 0x42 */ 527cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 d2_pwrdara; /* 0x43 */ 528cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 antenna_power[14]; /* 0x44 */ 529cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 cis_wordcnt; /* 0x52 */ 530cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 tx_power[14]; /* 0x54 */ 531cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 lpf_cutoff[14]; /* 0x62 */ 532cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 lnags_threshold[14]; /* 0x70 */ 533cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu __le16 checksum; /* 0x7E */ 534cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 cis_data[0]; /* 0x80, 384 bytes */ 535cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu} __attribute__ ((packed)); 536cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 537cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustatic const struct ieee80211_rate adm8211_rates[] = { 538cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .rate = 10, 539cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val = 10, 540cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val2 = -10, 541cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .flags = IEEE80211_RATE_CCK_2 }, 542cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .rate = 20, 543cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val = 20, 544cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val2 = -20, 545cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .flags = IEEE80211_RATE_CCK_2 }, 546cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .rate = 55, 547cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val = 55, 548cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val2 = -55, 549cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .flags = IEEE80211_RATE_CCK_2 }, 550cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .rate = 110, 551cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val = 110, 552cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .val2 = -110, 553cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .flags = IEEE80211_RATE_CCK_2 } 554cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 555cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 556cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct ieee80211_chan_range { 557cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 min; 558cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 max; 559cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 560cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 561cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustatic const struct ieee80211_channel adm8211_channels[] = { 562cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 1, 563cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2412}, 564cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 2, 565cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2417}, 566cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 3, 567cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2422}, 568cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 4, 569cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2427}, 570cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 5, 571cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2432}, 572cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 6, 573cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2437}, 574cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 7, 575cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2442}, 576cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 8, 577cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2447}, 578cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 9, 579cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2452}, 580cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 10, 581cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2457}, 582cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 11, 583cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2462}, 584cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 12, 585cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2467}, 586cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 13, 587cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2472}, 588cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu { .chan = 14, 589cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu .freq = 2484}, 590cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 591cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 592cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustruct adm8211_priv { 593cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct pci_dev *pdev; 594cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu spinlock_t lock; 595cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct adm8211_csr __iomem *map; 596cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct adm8211_desc *rx_ring; 597cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct adm8211_desc *tx_ring; 598cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu dma_addr_t rx_ring_dma; 599cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu dma_addr_t tx_ring_dma; 600cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct adm8211_rx_ring_info *rx_buffers; 601cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct adm8211_tx_ring_info *tx_buffers; 602cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu unsigned int rx_ring_size, tx_ring_size; 603cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu unsigned int cur_tx, dirty_tx, cur_rx; 604cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 605cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct ieee80211_low_level_stats stats; 606cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct ieee80211_hw_mode modes[1]; 607cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct ieee80211_channel channels[ARRAY_SIZE(adm8211_channels)]; 608cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct ieee80211_rate rates[ARRAY_SIZE(adm8211_rates)]; 609cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu int mode; 610cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 611cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu int channel; 612cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 bssid[ETH_ALEN]; 613cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 ssid[32]; 614cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu size_t ssid_len; 615cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 *mac_addr; 616cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 617cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 soft_rx_crc; 618cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 retry_limit; 619cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 620cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 ant_power; 621cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 tx_power; 622cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 lpf_cutoff; 623cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 lnags_threshold; 624cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu struct adm8211_eeprom *eeprom; 625cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu size_t eeprom_len; 626cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 627cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 revid; 628cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 629cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u32 nar; 630cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 631cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TYPE_INTERSIL 0x00 632cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TYPE_RFMD 0x01 633cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TYPE_MARVEL 0x02 634cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TYPE_AIROHA 0x03 635cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#define ADM8211_TYPE_ADMTEK 0x05 636cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu unsigned int rf_type:3; 637cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu unsigned int bbp_type:3; 638cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 639cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu u8 specific_bbptype; 640cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu enum { 641cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_RFMD2948 = 0x0, 642cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_RFMD2958 = 0x1, 643cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2, 644cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_MAX2820 = 0x8, 645cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu ADM8211_AL2210L = 0xC, /* Airoha */ 646cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu } transceiver_type; 647cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 648cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 649cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wustatic const struct ieee80211_chan_range cranges[] = { 650cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {1, 11}, /* FCC */ 651cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {1, 11}, /* IC */ 652cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {1, 13}, /* ETSI */ 653cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {10, 11}, /* SPAIN */ 654cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {10, 13}, /* FRANCE */ 655cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {14, 14}, /* MMK */ 656cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu {1, 14}, /* MMK2 */ 657cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu}; 658cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu 659cc0b88cf5ecf13cdd750f08e201ce8fadcdb601fMichael Wu#endif /* ADM8211_H */ 660