ar9003_mac.c revision 5519541d5a5f19893546883547e2f0f2e5934df7
1/* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16#include "hw.h" 17#include "ar9003_mac.h" 18 19static void ar9003_hw_rx_enable(struct ath_hw *hw) 20{ 21 REG_WRITE(hw, AR_CR, 0); 22} 23 24static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) 25{ 26 int checksum; 27 28 checksum = ads->info + ads->link 29 + ads->data0 + ads->ctl3 30 + ads->data1 + ads->ctl5 31 + ads->data2 + ads->ctl7 32 + ads->data3 + ads->ctl9; 33 34 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum; 35} 36 37static void ar9003_hw_set_desc_link(void *ds, u32 ds_link) 38{ 39 struct ar9003_txc *ads = ds; 40 41 ads->link = ds_link; 42 ads->ctl10 &= ~AR_TxPtrChkSum; 43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); 44} 45 46static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link) 47{ 48 struct ar9003_txc *ads = ds; 49 50 *ds_link = &ads->link; 51} 52 53static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 54{ 55 u32 isr = 0; 56 u32 mask2 = 0; 57 struct ath9k_hw_capabilities *pCap = &ah->caps; 58 u32 sync_cause = 0; 59 struct ath_common *common = ath9k_hw_common(ah); 60 61 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 62 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 63 == AR_RTC_STATUS_ON) 64 isr = REG_READ(ah, AR_ISR); 65 } 66 67 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; 68 69 *masked = 0; 70 71 if (!isr && !sync_cause) 72 return false; 73 74 if (isr) { 75 if (isr & AR_ISR_BCNMISC) { 76 u32 isr2; 77 isr2 = REG_READ(ah, AR_ISR_S2); 78 79 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> 80 MAP_ISR_S2_TIM); 81 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> 82 MAP_ISR_S2_DTIM); 83 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> 84 MAP_ISR_S2_DTIMSYNC); 85 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> 86 MAP_ISR_S2_CABEND); 87 mask2 |= ((isr2 & AR_ISR_S2_GTT) << 88 MAP_ISR_S2_GTT); 89 mask2 |= ((isr2 & AR_ISR_S2_CST) << 90 MAP_ISR_S2_CST); 91 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> 92 MAP_ISR_S2_TSFOOR); 93 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> 94 MAP_ISR_S2_BB_WATCHDOG); 95 96 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 97 REG_WRITE(ah, AR_ISR_S2, isr2); 98 isr &= ~AR_ISR_BCNMISC; 99 } 100 } 101 102 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) 103 isr = REG_READ(ah, AR_ISR_RAC); 104 105 if (isr == 0xffffffff) { 106 *masked = 0; 107 return false; 108 } 109 110 *masked = isr & ATH9K_INT_COMMON; 111 112 if (ah->config.rx_intr_mitigation) 113 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 114 *masked |= ATH9K_INT_RXLP; 115 116 if (ah->config.tx_intr_mitigation) 117 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 118 *masked |= ATH9K_INT_TX; 119 120 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 121 *masked |= ATH9K_INT_RXLP; 122 123 if (isr & AR_ISR_HP_RXOK) 124 *masked |= ATH9K_INT_RXHP; 125 126 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { 127 *masked |= ATH9K_INT_TX; 128 129 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 130 u32 s0, s1; 131 s0 = REG_READ(ah, AR_ISR_S0); 132 REG_WRITE(ah, AR_ISR_S0, s0); 133 s1 = REG_READ(ah, AR_ISR_S1); 134 REG_WRITE(ah, AR_ISR_S1, s1); 135 136 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | 137 AR_ISR_TXEOL); 138 } 139 } 140 141 if (isr & AR_ISR_GENTMR) { 142 u32 s5; 143 144 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) 145 s5 = REG_READ(ah, AR_ISR_S5_S); 146 else 147 s5 = REG_READ(ah, AR_ISR_S5); 148 149 ah->intr_gen_timer_trigger = 150 MS(s5, AR_ISR_S5_GENTIMER_TRIG); 151 152 ah->intr_gen_timer_thresh = 153 MS(s5, AR_ISR_S5_GENTIMER_THRESH); 154 155 if (ah->intr_gen_timer_trigger) 156 *masked |= ATH9K_INT_GENTIMER; 157 158 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 159 REG_WRITE(ah, AR_ISR_S5, s5); 160 isr &= ~AR_ISR_GENTMR; 161 } 162 163 } 164 165 *masked |= mask2; 166 167 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 168 REG_WRITE(ah, AR_ISR, isr); 169 170 (void) REG_READ(ah, AR_ISR); 171 } 172 173 if (*masked & ATH9K_INT_BB_WATCHDOG) 174 ar9003_hw_bb_watchdog_read(ah); 175 } 176 177 if (sync_cause) { 178 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 179 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 180 REG_WRITE(ah, AR_RC, 0); 181 *masked |= ATH9K_INT_FATAL; 182 } 183 184 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 185 ath_dbg(common, ATH_DBG_INTERRUPT, 186 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 187 188 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 189 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 190 191 } 192 return true; 193} 194 195static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, 196 bool is_firstseg, bool is_lastseg, 197 const void *ds0, dma_addr_t buf_addr, 198 unsigned int qcu) 199{ 200 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 201 unsigned int descid = 0; 202 203 ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) | 204 (1 << AR_TxRxDesc_S) | 205 (1 << AR_CtrlStat_S) | 206 (qcu << AR_TxQcuNum_S) | 0x17; 207 208 ads->data0 = buf_addr; 209 ads->data1 = 0; 210 ads->data2 = 0; 211 ads->data3 = 0; 212 213 ads->ctl3 = (seglen << AR_BufLen_S); 214 ads->ctl3 &= AR_BufLen; 215 216 /* Fill in pointer checksum and descriptor id */ 217 ads->ctl10 = ar9003_calc_ptr_chksum(ads); 218 ads->ctl10 |= (descid << AR_TxDescId_S); 219 220 if (is_firstseg) { 221 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore); 222 } else if (is_lastseg) { 223 ads->ctl11 = 0; 224 ads->ctl12 = 0; 225 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13; 226 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14; 227 } else { 228 /* XXX Intermediate descriptor in a multi-descriptor frame.*/ 229 ads->ctl11 = 0; 230 ads->ctl12 = AR_TxMore; 231 ads->ctl13 = 0; 232 ads->ctl14 = 0; 233 } 234} 235 236static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, 237 struct ath_tx_status *ts) 238{ 239 struct ar9003_txs *ads; 240 u32 status; 241 242 ads = &ah->ts_ring[ah->ts_tail]; 243 244 status = ACCESS_ONCE(ads->status8); 245 if ((status & AR_TxDone) == 0) 246 return -EINPROGRESS; 247 248 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; 249 250 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 251 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 252 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 253 "Tx Descriptor error %x\n", ads->ds_info); 254 memset(ads, 0, sizeof(*ads)); 255 return -EIO; 256 } 257 258 if (status & AR_TxOpExceeded) 259 ts->ts_status |= ATH9K_TXERR_XTXOP; 260 ts->ts_rateindex = MS(status, AR_FinalTxIdx); 261 ts->ts_seqnum = MS(status, AR_SeqNum); 262 ts->tid = MS(status, AR_TxTid); 263 264 ts->qid = MS(ads->ds_info, AR_TxQcuNum); 265 ts->desc_id = MS(ads->status1, AR_TxDescId); 266 ts->ts_tstamp = ads->status4; 267 ts->ts_status = 0; 268 ts->ts_flags = 0; 269 270 status = ACCESS_ONCE(ads->status2); 271 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); 272 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); 273 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); 274 if (status & AR_TxBaStatus) { 275 ts->ts_flags |= ATH9K_TX_BA; 276 ts->ba_low = ads->status5; 277 ts->ba_high = ads->status6; 278 } 279 280 status = ACCESS_ONCE(ads->status3); 281 if (status & AR_ExcessiveRetries) 282 ts->ts_status |= ATH9K_TXERR_XRETRY; 283 if (status & AR_Filtered) 284 ts->ts_status |= ATH9K_TXERR_FILT; 285 if (status & AR_FIFOUnderrun) { 286 ts->ts_status |= ATH9K_TXERR_FIFO; 287 ath9k_hw_updatetxtriglevel(ah, true); 288 } 289 if (status & AR_TxTimerExpired) 290 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 291 if (status & AR_DescCfgErr) 292 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; 293 if (status & AR_TxDataUnderrun) { 294 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; 295 ath9k_hw_updatetxtriglevel(ah, true); 296 } 297 if (status & AR_TxDelimUnderrun) { 298 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 299 ath9k_hw_updatetxtriglevel(ah, true); 300 } 301 ts->ts_shortretry = MS(status, AR_RTSFailCnt); 302 ts->ts_longretry = MS(status, AR_DataFailCnt); 303 ts->ts_virtcol = MS(status, AR_VirtRetryCnt); 304 305 status = ACCESS_ONCE(ads->status7); 306 ts->ts_rssi = MS(status, AR_TxRSSICombined); 307 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); 308 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); 309 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); 310 311 memset(ads, 0, sizeof(*ads)); 312 313 return 0; 314} 315 316static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds, 317 u32 pktlen, enum ath9k_pkt_type type, u32 txpower, 318 u32 keyIx, enum ath9k_key_type keyType, u32 flags) 319{ 320 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 321 322 if (txpower > ah->txpower_limit) 323 txpower = ah->txpower_limit; 324 325 if (txpower > 63) 326 txpower = 63; 327 328 ads->ctl11 = (pktlen & AR_FrameLen) 329 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 330 | SM(txpower, AR_XmitPower) 331 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 332 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) 333 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0); 334 335 ads->ctl12 = 336 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) 337 | SM(type, AR_FrameType) 338 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 339 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 340 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 341 342 ads->ctl17 = SM(keyType, AR_EncrType) | 343 (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); 344 ads->ctl18 = 0; 345 ads->ctl19 = AR_Not_Sounding; 346 347 ads->ctl20 = 0; 348 ads->ctl21 = 0; 349 ads->ctl22 = 0; 350} 351 352static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) 353{ 354 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 355 356 if (val) 357 ads->ctl11 |= AR_ClrDestMask; 358 else 359 ads->ctl11 &= ~AR_ClrDestMask; 360} 361 362static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, 363 void *lastds, 364 u32 durUpdateEn, u32 rtsctsRate, 365 u32 rtsctsDuration, 366 struct ath9k_11n_rate_series series[], 367 u32 nseries, u32 flags) 368{ 369 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 370 struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds; 371 u_int32_t ctl11; 372 373 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { 374 ctl11 = ads->ctl11; 375 376 if (flags & ATH9K_TXDESC_RTSENA) { 377 ctl11 &= ~AR_CTSEnable; 378 ctl11 |= AR_RTSEnable; 379 } else { 380 ctl11 &= ~AR_RTSEnable; 381 ctl11 |= AR_CTSEnable; 382 } 383 384 ads->ctl11 = ctl11; 385 } else { 386 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable)); 387 } 388 389 ads->ctl13 = set11nTries(series, 0) 390 | set11nTries(series, 1) 391 | set11nTries(series, 2) 392 | set11nTries(series, 3) 393 | (durUpdateEn ? AR_DurUpdateEna : 0) 394 | SM(0, AR_BurstDur); 395 396 ads->ctl14 = set11nRate(series, 0) 397 | set11nRate(series, 1) 398 | set11nRate(series, 2) 399 | set11nRate(series, 3); 400 401 ads->ctl15 = set11nPktDurRTSCTS(series, 0) 402 | set11nPktDurRTSCTS(series, 1); 403 404 ads->ctl16 = set11nPktDurRTSCTS(series, 2) 405 | set11nPktDurRTSCTS(series, 3); 406 407 ads->ctl18 = set11nRateFlags(series, 0) 408 | set11nRateFlags(series, 1) 409 | set11nRateFlags(series, 2) 410 | set11nRateFlags(series, 3) 411 | SM(rtsctsRate, AR_RTSCTSRate); 412 ads->ctl19 = AR_Not_Sounding; 413 414 last_ads->ctl13 = ads->ctl13; 415 last_ads->ctl14 = ads->ctl14; 416} 417 418static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, 419 u32 aggrLen) 420{ 421#define FIRST_DESC_NDELIMS 60 422 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 423 424 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 425 426 if (ah->ent_mode & AR_ENT_OTP_MPSD) { 427 u32 ctl17, ndelim; 428 /* 429 * Add delimiter when using RTS/CTS with aggregation 430 * and non enterprise AR9003 card 431 */ 432 ctl17 = ads->ctl17; 433 ndelim = MS(ctl17, AR_PadDelim); 434 435 if (ndelim < FIRST_DESC_NDELIMS) { 436 aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4; 437 ndelim = FIRST_DESC_NDELIMS; 438 } 439 440 ctl17 &= ~AR_AggrLen; 441 ctl17 |= SM(aggrLen, AR_AggrLen); 442 443 ctl17 &= ~AR_PadDelim; 444 ctl17 |= SM(ndelim, AR_PadDelim); 445 446 ads->ctl17 = ctl17; 447 } else { 448 ads->ctl17 &= ~AR_AggrLen; 449 ads->ctl17 |= SM(aggrLen, AR_AggrLen); 450 } 451} 452 453static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, 454 u32 numDelims) 455{ 456 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 457 unsigned int ctl17; 458 459 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 460 461 /* 462 * We use a stack variable to manipulate ctl6 to reduce uncached 463 * read modify, modfiy, write. 464 */ 465 ctl17 = ads->ctl17; 466 ctl17 &= ~AR_PadDelim; 467 ctl17 |= SM(numDelims, AR_PadDelim); 468 ads->ctl17 = ctl17; 469} 470 471static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) 472{ 473 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 474 475 ads->ctl12 |= AR_IsAggr; 476 ads->ctl12 &= ~AR_MoreAggr; 477 ads->ctl17 &= ~AR_PadDelim; 478} 479 480static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds) 481{ 482 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 483 484 ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr); 485} 486 487static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds, 488 u32 burstDuration) 489{ 490 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 491 492 ads->ctl13 &= ~AR_BurstDur; 493 ads->ctl13 |= SM(burstDuration, AR_BurstDur); 494 495} 496 497void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains) 498{ 499 struct ar9003_txc *ads = ds; 500 501 ads->ctl12 |= SM(chains, AR_PAPRDChainMask); 502} 503EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc); 504 505void ar9003_hw_attach_mac_ops(struct ath_hw *hw) 506{ 507 struct ath_hw_ops *ops = ath9k_hw_ops(hw); 508 509 ops->rx_enable = ar9003_hw_rx_enable; 510 ops->set_desc_link = ar9003_hw_set_desc_link; 511 ops->get_desc_link = ar9003_hw_get_desc_link; 512 ops->get_isr = ar9003_hw_get_isr; 513 ops->fill_txdesc = ar9003_hw_fill_txdesc; 514 ops->proc_txdesc = ar9003_hw_proc_txdesc; 515 ops->set11n_txdesc = ar9003_hw_set11n_txdesc; 516 ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario; 517 ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first; 518 ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle; 519 ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last; 520 ops->clr11n_aggr = ar9003_hw_clr11n_aggr; 521 ops->set11n_burstduration = ar9003_hw_set11n_burstduration; 522 ops->set_clrdmask = ar9003_hw_set_clrdmask; 523} 524 525void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) 526{ 527 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); 528} 529EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize); 530 531void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, 532 enum ath9k_rx_qtype qtype) 533{ 534 if (qtype == ATH9K_RX_QUEUE_HP) 535 REG_WRITE(ah, AR_HP_RXDP, rxdp); 536 else 537 REG_WRITE(ah, AR_LP_RXDP, rxdp); 538} 539EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma); 540 541int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, 542 void *buf_addr) 543{ 544 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr; 545 unsigned int phyerr; 546 547 /* TODO: byte swap on big endian for ar9300_10 */ 548 549 if ((rxsp->status11 & AR_RxDone) == 0) 550 return -EINPROGRESS; 551 552 if (MS(rxsp->ds_info, AR_DescId) != 0x168c) 553 return -EINVAL; 554 555 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) 556 return -EINPROGRESS; 557 558 if (!rxs) 559 return 0; 560 561 rxs->rs_status = 0; 562 rxs->rs_flags = 0; 563 564 rxs->rs_datalen = rxsp->status2 & AR_DataLen; 565 rxs->rs_tstamp = rxsp->status3; 566 567 /* XXX: Keycache */ 568 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); 569 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00); 570 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01); 571 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02); 572 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10); 573 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11); 574 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12); 575 576 if (rxsp->status11 & AR_RxKeyIdxValid) 577 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); 578 else 579 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; 580 581 rxs->rs_rate = MS(rxsp->status1, AR_RxRate); 582 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; 583 584 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; 585 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; 586 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); 587 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0; 588 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0; 589 590 rxs->evm0 = rxsp->status6; 591 rxs->evm1 = rxsp->status7; 592 rxs->evm2 = rxsp->status8; 593 rxs->evm3 = rxsp->status9; 594 rxs->evm4 = (rxsp->status10 & 0xffff); 595 596 if (rxsp->status11 & AR_PreDelimCRCErr) 597 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 598 599 if (rxsp->status11 & AR_PostDelimCRCErr) 600 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 601 602 if (rxsp->status11 & AR_DecryptBusyErr) 603 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 604 605 if ((rxsp->status11 & AR_RxFrameOK) == 0) { 606 /* 607 * AR_CRCErr will bet set to true if we're on the last 608 * subframe and the AR_PostDelimCRCErr is caught. 609 * In a way this also gives us a guarantee that when 610 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot 611 * possibly be reviewing the last subframe. AR_CRCErr 612 * is the CRC of the actual data. 613 */ 614 if (rxsp->status11 & AR_CRCErr) 615 rxs->rs_status |= ATH9K_RXERR_CRC; 616 else if (rxsp->status11 & AR_PHYErr) { 617 phyerr = MS(rxsp->status11, AR_PHYErrCode); 618 /* 619 * If we reach a point here where AR_PostDelimCRCErr is 620 * true it implies we're *not* on the last subframe. In 621 * in that case that we know already that the CRC of 622 * the frame was OK, and MAC would send an ACK for that 623 * subframe, even if we did get a phy error of type 624 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable 625 * to frame that are prior to the last subframe. 626 * The AR_PostDelimCRCErr is the CRC for the MPDU 627 * delimiter, which contains the 4 reserved bits, 628 * the MPDU length (12 bits), and follows the MPDU 629 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). 630 */ 631 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) && 632 (rxsp->status11 & AR_PostDelimCRCErr)) { 633 rxs->rs_phyerr = 0; 634 } else { 635 rxs->rs_status |= ATH9K_RXERR_PHY; 636 rxs->rs_phyerr = phyerr; 637 } 638 639 } else if (rxsp->status11 & AR_DecryptCRCErr) 640 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 641 else if (rxsp->status11 & AR_MichaelErr) 642 rxs->rs_status |= ATH9K_RXERR_MIC; 643 644 if (rxsp->status11 & AR_KeyMiss) 645 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 646 } 647 648 return 0; 649} 650EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma); 651 652void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) 653{ 654 ah->ts_tail = 0; 655 656 memset((void *) ah->ts_ring, 0, 657 ah->ts_size * sizeof(struct ar9003_txs)); 658 659 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 660 "TS Start 0x%x End 0x%x Virt %p, Size %d\n", 661 ah->ts_paddr_start, ah->ts_paddr_end, 662 ah->ts_ring, ah->ts_size); 663 664 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); 665 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); 666} 667 668void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, 669 u32 ts_paddr_start, 670 u8 size) 671{ 672 673 ah->ts_paddr_start = ts_paddr_start; 674 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); 675 ah->ts_size = size; 676 ah->ts_ring = (struct ar9003_txs *) ts_start; 677 678 ath9k_hw_reset_txstatus_ring(ah); 679} 680EXPORT_SYMBOL(ath9k_hw_setup_statusring); 681