1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef	_BRCM_NICPCI_H_
18#define	_BRCM_NICPCI_H_
19
20#include "types.h"
21
22/* PCI configuration address space size */
23#define PCI_SZPCR		256
24
25/* Brcm PCI configuration registers */
26/* backplane address space accessed by BAR0 */
27#define PCI_BAR0_WIN		0x80
28/* sprom property control */
29#define PCI_SPROM_CONTROL	0x88
30/* mask of PCI and other cores interrupts */
31#define PCI_INT_MASK		0x94
32/* backplane core interrupt mask bits offset */
33#define  PCI_SBIM_SHIFT		8
34/* backplane address space accessed by second 4KB of BAR0 */
35#define PCI_BAR0_WIN2		0xac
36/* pci config space gpio input (>=rev3) */
37#define PCI_GPIO_IN		0xb0
38/* pci config space gpio output (>=rev3) */
39#define PCI_GPIO_OUT		0xb4
40/* pci config space gpio output enable (>=rev3) */
41#define PCI_GPIO_OUTEN		0xb8
42
43/* bar0 + 4K accesses external sprom */
44#define PCI_BAR0_SPROM_OFFSET	(4 * 1024)
45/* bar0 + 6K accesses pci core registers */
46#define PCI_BAR0_PCIREGS_OFFSET	(6 * 1024)
47/*
48 * pci core SB registers are at the end of the
49 * 8KB window, so their address is the "regular"
50 * address plus 4K
51 */
52#define PCI_BAR0_PCISBR_OFFSET	(4 * 1024)
53/* bar0 window size Match with corerev 13 */
54#define PCI_BAR0_WINSZ		(16 * 1024)
55/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
56/* bar0 + 8K accesses pci/pcie core registers */
57#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
58/* bar0 + 12K accesses chipc core registers */
59#define PCI_16KB0_CCREGS_OFFSET	(12 * 1024)
60
61struct sbpciregs;
62struct sbpcieregs;
63
64extern struct pcicore_info *pcicore_init(struct si_pub *sih,
65					 struct bcma_device *core);
66extern void pcicore_deinit(struct pcicore_info *pch);
67extern void pcicore_attach(struct pcicore_info *pch, int state);
68extern void pcicore_hwup(struct pcicore_info *pch);
69extern void pcicore_up(struct pcicore_info *pch, int state);
70extern void pcicore_sleep(struct pcicore_info *pch);
71extern void pcicore_down(struct pcicore_info *pch, int state);
72extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
73				      unsigned char *buf, u32 *buflen);
74extern void pcicore_fixcfg(struct pcicore_info *pch);
75extern void pcicore_pci_setup(struct pcicore_info *pch);
76
77#endif /* _BRCM_NICPCI_H_ */
78