csr.h revision 3b98c7f49b675eb13e723967cf1264e3d562c480
1be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/****************************************************************************** 2be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 3be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * This file is provided under a dual BSD/GPLv2 license. When using or 4be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * redistributing this file, you may do so under either license. 5be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 6be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * GPL LICENSE SUMMARY 7be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 8be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 9be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 10be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * This program is free software; you can redistribute it and/or modify 11be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * it under the terms of version 2 of the GNU General Public License as 12be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * published by the Free Software Foundation. 13be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 14be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * This program is distributed in the hope that it will be useful, but 15be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * WITHOUT ANY WARRANTY; without even the implied warranty of 16be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * General Public License for more details. 18be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 19be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * You should have received a copy of the GNU General Public License 20be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * along with this program; if not, write to the Free Software 21be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 22be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * USA 23be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 24be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * The full GNU General Public License is included in this distribution 25be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * in the file called LICENSE.GPL. 26be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 27be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Contact Information: 28be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Intel Linux Wireless <ilw@linux.intel.com> 29be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 31be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * BSD LICENSE 32be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 33be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 34be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * All rights reserved. 35be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 36be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Redistribution and use in source and binary forms, with or without 37be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * modification, are permitted provided that the following conditions 38be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * are met: 39be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 40be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * * Redistributions of source code must retain the above copyright 41be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * notice, this list of conditions and the following disclaimer. 42be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * * Redistributions in binary form must reproduce the above copyright 43be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * notice, this list of conditions and the following disclaimer in 44be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * the documentation and/or other materials provided with the 45be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * distribution. 46be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * * Neither the name Intel Corporation nor the names of its 47be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * contributors may be used to endorse or promote products derived 48be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * from this software without specific prior written permission. 49be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 50be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 51be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 52be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 53be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 54be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 56be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 60be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 62be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy *****************************************************************************/ 63e2ebc8337d116acdc25469ec8547ae665f50a4c1Stanislaw Gruszka#ifndef __il_csr_h__ 64e2ebc8337d116acdc25469ec8547ae665f50a4c1Stanislaw Gruszka#define __il_csr_h__ 65be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 66be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * CSR (control and status registers) 67be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 68be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * CSR registers are mapped directly into PCI bus space, and are accessible 69be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * whenever platform supplies power to device, even when device is in 70be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * low power states due to driver-invoked device resets 71be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 72be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 73841b2ccac3251fdbf7a0bc26724874cdc35df96cStanislaw Gruszka * Use _il_wr() and _il_rd() family to access these registers; 74be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * these provide simple PCI bus access, without waking up the MAC. 750c1a94e299eed7ea11ebc407d1e08a26c594abe5Stanislaw Gruszka * Do not use il_wr() family for these registers; 76be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 77be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * The MAC (uCode processor, etc.) does not need to be powered up for accessing 78be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * the CSR registers. 79be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 80be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: Device does need to be awake in order to read this memory 81be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * via CSR_EEPROM register 82be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 83be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_BASE (0x000) 84be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 85be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 86be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 87be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 88be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 89be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 90be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 91be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 92be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL (CSR_BASE+0x024) 93be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 94841b2ccac3251fdbf7a0bc26724874cdc35df96cStanislaw Gruszka/* 2nd byte of CSR_INT_COALESCING, not accessible via _il_wr()! */ 95be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 96be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 97be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 98be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Hardware revision info 99be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit fields: 100be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 31-8: Reserved 101be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 102be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 103be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 1-0: "Dash" (-) value, as in A-1, etc. 104be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 105be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: Revision step affects calculation of CCK txpower for 4965. 106be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965). 107be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 108be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_REV (CSR_BASE+0x028) 109be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 110be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 111be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * EEPROM memory reads 112be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 113be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: Device must be awake, initialized via apm_ops.init(), 114be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * in order to read. 115be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 116be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_REG (CSR_BASE+0x02c) 117be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_GP (CSR_BASE+0x030) 118be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 119be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GIO_REG (CSR_BASE+0x03C) 120be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_UCODE_REG (CSR_BASE+0x048) 121be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 122be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 123be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 124be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * UCODE-DRIVER GP (general purpose) mailbox registers. 125be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * SET/CLR registers set/clear bit(s) if "1" is written. 126be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 127be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 128be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 129be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 130be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 131be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 132be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_LED_REG (CSR_BASE+0x094) 133be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 134be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 135be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* GIO Chicken Bits (PCI Express bus link power management) */ 136be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 137be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 138be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* Analog phase-lock-loop configuration */ 139be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 140be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 141be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 142be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * CSR Hardware Revision Workaround Register. Indicates hardware rev; 143be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 144be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * See also CSR_HW_REV register. 145be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit fields: 146be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 147be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 1-0: "Dash" (-) value, as in C-1, etc. 148be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 149be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 150be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 151be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 152be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 153be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 154be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* Bits for CSR_HW_IF_CONFIG_REG */ 155be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) 156be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 157be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 158be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 159be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 160be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100) 161be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200) 162be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) 163be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) 164be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) 165be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) 166be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 167be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 168be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 169be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 170be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 171be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 172be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 173be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 174be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 175be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 176be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 177be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * acknowledged (reset) by host writing "1" to flagged bits. */ 178be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 179be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 180be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 181be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 182be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 183be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 184be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 185be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 186be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ 187be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 188be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 189be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 190be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 191be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_HW_ERR | \ 192be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_FH_TX | \ 193be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_SW_ERR | \ 194be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_RF_KILL | \ 195be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_SW_RX | \ 196be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_WAKEUP | \ 197be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_INT_BIT_ALIVE) 198be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 199be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 200be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 201be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 202be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */ 203be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 204be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 205be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */ 206be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 207be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 208be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 209be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 210be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR39_FH_INT_BIT_RX_CHNL2 | \ 211be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_RX_CHNL1 | \ 212be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_RX_CHNL0) 213be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 214be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 215be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \ 216be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_TX_CHNL1 | \ 217be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_TX_CHNL0) 218be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 219be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 220be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_RX_CHNL1 | \ 221be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_RX_CHNL0) 222be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 223be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 224be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy CSR_FH_INT_BIT_TX_CHNL0) 225be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 226be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* GPIO */ 227be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 228be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 229be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 230be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 231be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* RESET */ 232be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 233be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 234be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 235be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 236be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 237be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 238be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 239be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 240be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * GP (general purpose) CONTROL REGISTER 241be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit fields: 242be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 27: HW_RF_KILL_SW 243be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Indicates state of (platform's) hardware RF-Kill switch 244be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 26-24: POWER_SAVE_TYPE 245be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Indicates current power-saving mode: 246be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 000 -- No power saving 247be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 001 -- MAC power-down 248be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 010 -- PHY (radio) power-down 249be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 011 -- Error 250be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 9-6: SYS_CONFIG 251be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Indicates current system configuration, reflecting pins on chip 252be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * as forced high/low by device circuit board. 253be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 4: GOING_TO_SLEEP 254be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Indicates MAC is entering a power-saving sleep power-down. 255be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Not a good time to access device-internal resources. 256be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 3: MAC_ACCESS_REQ 257be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host sets this to request and maintain MAC wakeup, to allow host 258be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * access to device-internal resources. Host must wait for 259be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 260be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * device registers. 261be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 2: INIT_DONE 262be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host sets this to put device into fully operational D0 power mode. 263be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host resets this after SW_RESET to put device into low power mode. 264be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 0: MAC_CLOCK_READY 265be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Indicates MAC (ucode processor, etc.) is powered up and can run. 266be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Internal resources are accessible. 267be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: This does not indicate that the processor is actually running. 268be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: This does not indicate that 4965 or 3945 has completed 269be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * init or post-power-down restore of internal SRAM memory. 270be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 271be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * SRAM is restored and uCode is in normal operation mode. 272be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 273be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * do not need to save/restore it. 274be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: After device reset, this bit remains "0" until host sets 275be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * INIT_DONE 276be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 277be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 278be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 279be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 280be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 281be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 282be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 283be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 284be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 285be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 286be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 287be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 288be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 289be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* EEPROM REG */ 290be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 291be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_REG_BIT_CMD (0x00000002) 292be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 293be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 294be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 295be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* EEPROM GP */ 296be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 297be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 298be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 299be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 300be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 301be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* GP REG */ 302be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 303be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 304be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 305be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 306be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 307be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 308be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 309be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* CSR GIO */ 310be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 311be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 312be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 313be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * UCODE-DRIVER GP (general purpose) mailbox register 1 314be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host driver and uCode write and/or read this register to communicate with 315be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * each other. 316be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit fields: 317be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 4: UCODE_DISABLE 318be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host sets this to request permanent halt of uCode, same as 319be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * sending CARD_STATE command with "halt" bit set. 320be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 3: CT_KILL_EXIT 321be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host sets this to request exit from CT_KILL state, i.e. host thinks 322be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * device temperature is low enough to continue normal operation. 323be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 2: CMD_BLOCKED 324be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 325be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * to release uCode to clear all Tx and command queues, enter 326be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * unassociated mode, and power down. 327be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 328be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 1: SW_BIT_RFKILL 329be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Host sets this when issuing CARD_STATE command to request 330be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * device sleep. 331be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 0: MAC_SLEEP 332be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * uCode sets this when preparing a power-saving power-down. 333be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * uCode resets this when power-up is complete and SRAM is sane. 334be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * NOTE: 3945/4965 saves internal SRAM data to host when powering down, 335be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * and must restore this data after powering back up. 336be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * MAC_SLEEP is the best indication that restore is complete. 337be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 338be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * do not need to save/restore it. 339be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 340be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 341be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 342be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 343be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 344be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 345be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* GIO Chicken Bits (PCI Express bus link power management) */ 346be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 347be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 348be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 349be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* LED */ 350be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 351be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_LED_REG_TRUN_ON (0x78) 352be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_LED_REG_TRUN_OFF (0x38) 353be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 354be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* ANA_PLL */ 355be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR39_ANA_PLL_CFG_VAL (0x01000000) 356be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 357be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* HPET MEM debug */ 358be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 359be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 3603b98c7f49b675eb13e723967cf1264e3d562c480Stanislaw Gruszka/* DRAM INT TBL */ 361be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 362be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 363be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 364be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 365be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * HBUS (Host-side Bus) 366be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 367be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * HBUS registers are mapped directly into PCI bus space, but are used 368be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * to indirectly access device's internal memory or registers that 369be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * may be powered-down. 370be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 3710c1a94e299eed7ea11ebc407d1e08a26c594abe5Stanislaw Gruszka * Use il_wr()/il_rd() family 372be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * for these registers; 373be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 374be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * to make sure the MAC (uCode processor, etc.) is powered up for accessing 375be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * internal resources. 376be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 377841b2ccac3251fdbf7a0bc26724874cdc35df96cStanislaw Gruszka * Do not use _il_wr()/_il_rd() family to access these registers; 378be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * these provide only simple PCI bus access, without waking up the MAC. 379be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 380be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_BASE (0x400) 381be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 382be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 383be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 384be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * structures, error log, event log, verifying uCode load). 385be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * First write to address register, then read from or write to data register 386be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * to complete the job. Once the address register is set up, accesses to 387be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * data registers auto-increment the address by one dword. 388be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit usage for address registers (read or write): 389be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 0-31: memory address within device 390be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 391be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 392be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 393be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 394be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 395be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 396be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 397be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 398be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 399be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 400be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 401be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Registers for accessing device's internal peripheral registers 402be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * (e.g. SCD, BSM, etc.). First write to address register, 403be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * then read from or write to data register to complete the job. 404be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit usage for address registers (read or write): 405be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 0-15: register address (offset) within device 406be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 407be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 408be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 409be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 410be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 411be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 412be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 413be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy/* 4140c2c885200057c44ac5660d123e199192689ca5dStanislaw Gruszka * Per-Tx-queue write pointer (idx, really!) 4150c2c885200057c44ac5660d123e199192689ca5dStanislaw Gruszka * Indicates idx to next TFD that driver will fill (1 past latest filled). 416be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * Bit usage: 4170c2c885200057c44ac5660d123e199192689ca5dStanislaw Gruszka * 0-7: queue write idx 418be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy * 11-8: queue selector 419be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy */ 420be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 421be663ab67077fac8e23eb8e231a8c1c94cb32e54Wey-Yi Guy 422e2ebc8337d116acdc25469ec8547ae665f50a4c1Stanislaw Gruszka#endif /* !__il_csr_h__ */ 423