iwl-trans-pcie-int.h revision 81a3de1ce2929fef2b112c048c50bc52b686f94d
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/****************************************************************************** 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Portions of this file are derived from the ipw3945 project, as well 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * as portions of the ieee80211 subsystem header files. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify it 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * under the terms of version 2 of the GNU General Public License as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is distributed in the hope that it will be useful, but WITHOUT 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * more details. 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * You should have received a copy of the GNU General Public License along with 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * this program; if not, write to the Free Software Foundation, Inc., 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The full GNU General Public License is included in this distribution in the 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * file called LICENSE. 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Contact Information: 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Intel Linux Wireless <ilw@linux.intel.com> 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *****************************************************************************/ 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef __iwl_trans_int_pcie_h__ 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __iwl_trans_int_pcie_h__ 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/spinlock.h> 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/interrupt.h> 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/skbuff.h> 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pci.h> 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "iwl-fh.h" 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "iwl-csr.h" 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "iwl-shared.h" 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "iwl-trans.h" 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "iwl-debug.h" 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "iwl-io.h" 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_tx_queue; 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_queue; 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_host_cmd; 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*This file includes the declaration that are internal to the 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * trans_pcie layer */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * struct isr_statistics - interrupt statistics 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct isr_statistics { 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 hw; 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 sw; 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 err_code; 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 sch; 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 alive; 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 rfkill; 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ctkill; 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 wakeup; 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 rx; 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 tx; 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 unhandled; 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * struct iwl_rx_queue - Rx queue 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @pool: 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @queue: 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @read: Shared index to newest available Rx buffer 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @write: Shared index to oldest written Rx packet 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @free_count: Number of pre-allocated buffers in rx_free 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @write_actual: 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @rx_free: list of free SKBs for use 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @rx_used: List of Rx buffers with no SKB 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @need_update: flag to indicate we need to update read/write index 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @rb_stts: driver's pointer to receive buffer status 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @rb_stts_dma: bus address of receive buffer status 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @lock: 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_rx_queue { 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le32 *bd; 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t bd_dma; 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 read; 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 write; 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 free_count; 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 write_actual; 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct list_head rx_free; 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct list_head rx_used; 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int need_update; 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_rb_status *rb_stts; 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t rb_stts_dma; 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds spinlock_t lock; 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_dma_ptr { 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t dma; 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void *addr; 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds size_t size; 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This queue number is required for proper operation 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * because the ucode will stop/start the scheduler as 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * required. 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_IPAN_MCAST_QUEUE 8 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_cmd_meta { 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* only for SYNC commands, iff the reply skb is wanted */ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_host_cmd *source; 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 flags; 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds DEFINE_DMA_UNMAP_ADDR(mapping); 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds DEFINE_DMA_UNMAP_LEN(len); 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Generic queue structure 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Contains common data for Rx and Tx queues. 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note the difference between n_bd and n_window: the hardware 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * always assumes 256 descriptors, so n_bd is always 256 (unless 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * there might be HW changes in the future). For the normal TX 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * queues, n_window, which is the size of the software queue data 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is also 256; however, for the command queue, n_window is only 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 32 since we don't need so many commands pending. Since the HW 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * still uses 256 BDs for DMA though, n_bd stays 256. As a result, 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the software buffers (in the variables @meta, @txb in struct 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * in the same struct) have 256. 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This means that we end up with the following: 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * SW entries: | 0 | ... | 31 | 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * where N is a number between 0 and 7. This means that the SW 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * data is a window overlayed over the HW queue. 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_queue { 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int n_bd; /* number of BDs in this queue */ 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int write_ptr; /* 1-st empty entry (index) host_w*/ 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int read_ptr; /* last used entry (index) host_r*/ 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* use for monitoring and recovering the stuck queue */ 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t dma_addr; /* physical addr for BD's */ 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int n_window; /* safe queue window */ 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 id; 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int low_mark; /* low watermark, resume queue if free 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space more than this */ 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int high_mark; /* high watermark, stop queue if free 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space less than this */ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * struct iwl_tx_queue - Tx Queue for DMA 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @q: generic Rx/Tx queue descriptor 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @bd: base of circular buffer of TFDs 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @cmd: array of command/TX buffer pointers 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @meta: array of meta data for each command/tx buffer 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @dma_addr_cmd: physical address of cmd/tx buffer array 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @txb: array of per-TFD driver data 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @time_stamp: time (in jiffies) of last read_ptr change 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @need_update: indicates need to update read/write index 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @sta_id: valid if sched_retry is set 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @tid: valid if sched_retry is set 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * descriptors) and required locking structures. 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TFD_TX_CMD_SLOTS 256 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TFD_CMD_SLOTS 32 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_tx_queue { 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_queue q; 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tfd *tfds; 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_device_cmd **cmd; 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_cmd_meta *meta; 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct sk_buff **skbs; 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long time_stamp; 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 need_update; 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 sched_retry; 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 active; 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 swq_id; 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 sta_id; 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 tid; 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * struct iwl_trans_pcie - PCIe transport specific data 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @rxq: all the RX queue data 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @rx_replenish: work that will be called when buffers need to be allocated 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @trans: pointer to the generic transport area 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @scd_base_addr: scheduler sram base address in SRAM 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @scd_bc_tbls: pointer to the byte count table of the scheduler 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @kw: keep warm address 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @ac_to_fifo: to what fifo is a specifc AC mapped ? 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @ac_to_queue: to what tx queue is a specifc AC mapped ? 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @mcast_queue: 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @txq: Tx DMA processing queues 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @txq_ctx_active_msk: what queue is active 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * queue_stopped: tracks what queue is stopped 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * queue_stop_count: tracks what SW queue is stopped 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct iwl_trans_pcie { 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_rx_queue rxq; 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct work_struct rx_replenish; 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_trans *trans; 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* INT ICT Table */ 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le32 *ict_tbl; 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void *ict_tbl_vir; 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t ict_tbl_dma; 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t aligned_ict_tbl_dma; 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int ict_index; 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 inta; 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bool use_ict; 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct tasklet_struct irq_tasklet; 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct isr_statistics isr_stats; 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 inta_mask; 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 scd_base_addr; 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_dma_ptr scd_bc_tbls; 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_dma_ptr kw; 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds const u8 *ac_to_fifo[NUM_IWL_RXON_CTX]; 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds const u8 *ac_to_queue[NUM_IWL_RXON_CTX]; 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 mcast_queue[NUM_IWL_RXON_CTX]; 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq; 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long txq_ctx_active_msk; 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_MAX_HW_QUEUES 32 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds atomic_t queue_stop_count[4]; 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************** 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds* RX 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds******************************************************/ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_bg_rx_replenish(struct work_struct *data); 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_irq_tasklet(struct iwl_trans *trans); 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwlagn_rx_replenish(struct iwl_trans *trans); 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_rx_queue *q); 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************** 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds* ICT 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds******************************************************/ 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_reset_ict(struct iwl_trans *trans); 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_disable_ict(struct iwl_trans *trans); 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_alloc_isr_ict(struct iwl_trans *trans); 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_free_isr_ict(struct iwl_trans *trans); 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsirqreturn_t iwl_isr_ict(int irq, void *data); 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************** 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds* TX / HCMD 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds******************************************************/ 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_txq_update_write_ptr(struct iwl_trans *trans, 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq); 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq, 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t addr, u16 len, u8 reset); 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id); 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_tx_cmd_complete(struct iwl_trans *trans, 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_rx_mem_buffer *rxb, int handler_status); 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq, 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 byte_cnt); 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id); 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds enum iwl_rxon_context_id ctx, int sta_id, 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tid); 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index); 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_trans_tx_queue_set_status(struct iwl_trans *trans, 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq, 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tx_fifo_id, int scd_retry); 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds enum iwl_rxon_context_id ctx, int sta_id, 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tid, u16 *ssn); 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds enum iwl_rxon_context_id ctx, 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int sta_id, int tid, int frame_limit); 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int index, enum dma_data_direction dma_dir); 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct sk_buff_head *skbs); 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_queue_space(const struct iwl_queue *q); 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************** 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds* Error handling 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds******************************************************/ 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log, 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds char **buf, bool display); 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display); 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvoid iwl_dump_csr(struct iwl_trans *trans); 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************** 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds* Helpers 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds******************************************************/ 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_disable_interrupts(struct iwl_trans *trans) 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clear_bit(STATUS_INT_ENABLED, &trans->shrd->status); 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* disable interrupts from uCode/NIC to host */ 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000); 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* acknowledge/clear/reset any interrupts still pending 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * from uCode or flow handler (Rx/Tx DMA) */ 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iwl_write32(bus(trans), CSR_INT, 0xffffffff); 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff); 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_enable_interrupts(struct iwl_trans *trans) 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_trans_pcie *trans_pcie = 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_TRANS_GET_PCIE_TRANS(trans); 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds set_bit(STATUS_INT_ENABLED, &trans->shrd->status); 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask); 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * we have 8 bits used like this: 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 7 6 5 4 3 2 1 0 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * | | | | | | | | 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * | | | | | | +-+-------- AC queue (0-3) 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * | | | | | | 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * | +-+-+-+-+------------ HW queue ID 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * | 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * +---------------------- unused 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq) 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds BUG_ON(ac > 3); /* only have 2 bits */ 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds BUG_ON(hwq > 31); /* only use 5 bits */ 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds txq->swq_id = (hwq << 2) | ac; 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_wake_queue(struct iwl_trans *trans, 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq, const char *msg) 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 queue = txq->swq_id; 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 ac = queue & 3; 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 hwq = (queue >> 2) & 0x1f; 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_trans_pcie *trans_pcie = 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_TRANS_GET_PCIE_TRANS(trans); 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (test_and_clear_bit(hwq, trans_pcie->queue_stopped)) { 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0) { 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iwl_wake_sw_queue(priv(trans), ac); 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d ac %d. %s", 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds hwq, ac, msg); 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_TX_QUEUES(trans, "Don't wake hwq %d ac %d" 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " stop count %d. %s", 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds hwq, ac, atomic_read(&trans_pcie-> 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds queue_stop_count[ac]), msg); 3761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_stop_queue(struct iwl_trans *trans, 3811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_tx_queue *txq, const char *msg) 3821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 queue = txq->swq_id; 3841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 ac = queue & 3; 3851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 hwq = (queue >> 2) & 0x1f; 3861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct iwl_trans_pcie *trans_pcie = 3871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_TRANS_GET_PCIE_TRANS(trans); 3881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!test_and_set_bit(hwq, trans_pcie->queue_stopped)) { 3901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0) { 3911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iwl_stop_sw_queue(priv(trans), ac); 3921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d ac %d" 3931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " stop count %d. %s", 3941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds hwq, ac, atomic_read(&trans_pcie-> 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds queue_stop_count[ac]), msg); 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 3971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_TX_QUEUES(trans, "Don't stop hwq %d ac %d" 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " stop count %d. %s", 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds hwq, ac, atomic_read(&trans_pcie-> 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds queue_stop_count[ac]), msg); 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds IWL_DEBUG_TX_QUEUES(trans, "stop hwq %d, but it is stopped/ %s", 4041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds hwq, msg); 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef ieee80211_stop_queue 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#undef ieee80211_stop_queue 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 4111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef ieee80211_wake_queue 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#undef ieee80211_wake_queue 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie, 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int txq_id) 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds set_bit(txq_id, &trans_pcie->txq_ctx_active_msk); 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie, 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int txq_id) 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk); 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline int iwl_queue_used(const struct iwl_queue *q, int i) 4331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return q->write_ptr >= q->read_ptr ? 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (i >= q->read_ptr && i < q->write_ptr) : 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds !(i < q->read_ptr && i >= q->write_ptr); 4371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline u8 get_cmd_index(struct iwl_queue *q, u32 index) 4401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return index & (q->n_window - 1); 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_BK 0 /* shared */ 4451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_BE 1 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_VI 2 /* shared */ 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_VO 3 4481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK 4491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_BE_IPAN 4 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_VO_IPAN 5 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* re-uses the VO FIFO, uCode will properly flush/schedule */ 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_AUX 5 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_TX_FIFO_UNUSED -1 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* AUX (TX during scan dwell) queue */ 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IWL_AUX_QUEUE 10 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* __iwl_trans_int_pcie_h__ */ 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds