1f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#ifndef RTL8180_H 2f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define RTL8180_H 3f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 4f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#include "rtl818x.h" 5f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 6f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define MAX_RX_SIZE IEEE80211_MAX_RTS_THRESHOLD 7f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 8f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define RF_PARAM_ANALOGPHY (1 << 0) 9f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define RF_PARAM_ANTBDEFAULT (1 << 1) 10f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define RF_PARAM_CARRIERSENSE1 (1 << 2) 11f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define RF_PARAM_CARRIERSENSE2 (1 << 3) 12f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 13f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define BB_ANTATTEN_CHAN14 0x0C 14f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define BB_ANTENNA_B 0x40 15f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 16f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define BB_HOST_BANG (1 << 30) 17f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define BB_HOST_BANG_EN (1 << 2) 18f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define BB_HOST_BANG_CLK (1 << 1) 19f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define BB_HOST_BANG_DATA 1 20f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 21f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define ANAPARAM_TXDACOFF_SHIFT 27 22f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define ANAPARAM_PWR0_SHIFT 28 23f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define ANAPARAM_PWR0_MASK (0x07 << ANAPARAM_PWR0_SHIFT) 24f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define ANAPARAM_PWR1_SHIFT 20 25f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#define ANAPARAM_PWR1_MASK (0x7F << ANAPARAM_PWR1_SHIFT) 26f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 27f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustruct rtl8180_tx_desc { 28f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 flags; 29f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le16 rts_duration; 30f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le16 plcp_len; 31f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 tx_buf; 32f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 frame_len; 33f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 next_tx_desc; 34f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u8 cw; 35f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u8 retry_limit; 36f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u8 agc; 37f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u8 flags2; 38f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u32 reserved[2]; 39ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 40f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 41f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustruct rtl8180_rx_desc { 42f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 flags; 43f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 flags2; 44f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu union { 45f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 rx_buf; 46f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le64 tsft; 47f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu }; 48ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 49f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 50f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustruct rtl8180_tx_ring { 51f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct rtl8180_tx_desc *desc; 52f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu dma_addr_t dma; 53f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu unsigned int idx; 54f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu unsigned int entries; 55f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct sk_buff_head queue; 56f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu}; 57f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 58c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linvillestruct rtl8180_vif { 59c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville struct ieee80211_hw *dev; 60c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville 61c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville /* beaconing */ 62c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville struct delayed_work beacon_work; 63c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville bool enable_beacon; 64c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville}; 65c809e86c11a64488acc85ddf12ece3c9b879ccb6John W. Linville 66f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustruct rtl8180_priv { 67f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu /* common between rtl818x drivers */ 68f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct rtl818x_csr __iomem *map; 69f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu const struct rtl818x_rf_ops *rf; 7032bfd35d4b63bd63de4bb0d791ef049c3c868726Johannes Berg struct ieee80211_vif *vif; 71f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 72f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu /* rtl8180 driver specific */ 73f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu spinlock_t lock; 74f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct rtl8180_rx_desc *rx_ring; 75f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu dma_addr_t rx_ring_dma; 76f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu unsigned int rx_idx; 77f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct sk_buff *rx_buf[32]; 78f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct rtl8180_tx_ring tx_ring[4]; 79f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct ieee80211_channel channels[14]; 80f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct ieee80211_rate rates[12]; 818318d78a44d49ac1edf2bdec7299de3617c4232eJohannes Berg struct ieee80211_supported_band band; 82f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu struct pci_dev *pdev; 83f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u32 rx_conf; 84f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 85f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu int r8185; 86f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u32 anaparam; 87f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u16 rfparam; 88f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u8 csthreshold; 8951e080deba57437459571f26a3c6f3db03324c4cJohn W. Linville 9051e080deba57437459571f26a3c6f3db03324c4cJohn W. Linville /* sequence # */ 9151e080deba57437459571f26a3c6f3db03324c4cJohn W. Linville u16 seqno; 92f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu}; 93f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 94f653211197f3841f383fa9757ef8ce182c6cf627Michael Wuvoid rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data); 95f653211197f3841f383fa9757ef8ce182c6cf627Michael Wuvoid rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam); 96f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 97f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustatic inline u8 rtl818x_ioread8(struct rtl8180_priv *priv, u8 __iomem *addr) 98f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu{ 99f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu return ioread8(addr); 100f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu} 101f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 102f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustatic inline u16 rtl818x_ioread16(struct rtl8180_priv *priv, __le16 __iomem *addr) 103f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu{ 104f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu return ioread16(addr); 105f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu} 106f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 107f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustatic inline u32 rtl818x_ioread32(struct rtl8180_priv *priv, __le32 __iomem *addr) 108f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu{ 109f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu return ioread32(addr); 110f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu} 111f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 112f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustatic inline void rtl818x_iowrite8(struct rtl8180_priv *priv, 113f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu u8 __iomem *addr, u8 val) 114f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu{ 115f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu iowrite8(val, addr); 116f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu} 117f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 118f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustatic inline void rtl818x_iowrite16(struct rtl8180_priv *priv, 119f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le16 __iomem *addr, u16 val) 120f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu{ 121f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu iowrite16(val, addr); 122f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu} 123f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 124f653211197f3841f383fa9757ef8ce182c6cf627Michael Wustatic inline void rtl818x_iowrite32(struct rtl8180_priv *priv, 125f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu __le32 __iomem *addr, u32 val) 126f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu{ 127f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu iowrite32(val, addr); 128f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu} 129f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu 130f653211197f3841f383fa9757ef8ce182c6cf627Michael Wu#endif /* RTL8180_H */ 131