zd_chip.h revision 741fec53f268b691b869ffc70023319406e0cc97
1/* zd_chip.h 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License as published by 5 * the Free Software Foundation; either version 2 of the License, or 6 * (at your option) any later version. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 */ 17 18#ifndef _ZD_CHIP_H 19#define _ZD_CHIP_H 20 21#include "zd_types.h" 22#include "zd_rf.h" 23#include "zd_usb.h" 24 25/* Header for the Media Access Controller (MAC) and the Baseband Processor 26 * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and 27 * adds a processor for handling the USB protocol. 28 */ 29 30/* 8-bit hardware registers */ 31#define CR0 CTL_REG(0x0000) 32#define CR1 CTL_REG(0x0004) 33#define CR2 CTL_REG(0x0008) 34#define CR3 CTL_REG(0x000C) 35 36#define CR5 CTL_REG(0x0010) 37/* bit 5: if set short preamble used 38 * bit 6: filter band - Japan channel 14 on, else off 39 */ 40#define CR6 CTL_REG(0x0014) 41#define CR7 CTL_REG(0x0018) 42#define CR8 CTL_REG(0x001C) 43 44#define CR4 CTL_REG(0x0020) 45 46#define CR9 CTL_REG(0x0024) 47/* bit 2: antenna switch (together with CR10) */ 48#define CR10 CTL_REG(0x0028) 49/* bit 1: antenna switch (together with CR9) 50 * RF2959 controls with CR11 radion on and off 51 */ 52#define CR11 CTL_REG(0x002C) 53/* bit 6: TX power control for OFDM 54 * RF2959 controls with CR10 radio on and off 55 */ 56#define CR12 CTL_REG(0x0030) 57#define CR13 CTL_REG(0x0034) 58#define CR14 CTL_REG(0x0038) 59#define CR15 CTL_REG(0x003C) 60#define CR16 CTL_REG(0x0040) 61#define CR17 CTL_REG(0x0044) 62#define CR18 CTL_REG(0x0048) 63#define CR19 CTL_REG(0x004C) 64#define CR20 CTL_REG(0x0050) 65#define CR21 CTL_REG(0x0054) 66#define CR22 CTL_REG(0x0058) 67#define CR23 CTL_REG(0x005C) 68#define CR24 CTL_REG(0x0060) /* CCA threshold */ 69#define CR25 CTL_REG(0x0064) 70#define CR26 CTL_REG(0x0068) 71#define CR27 CTL_REG(0x006C) 72#define CR28 CTL_REG(0x0070) 73#define CR29 CTL_REG(0x0074) 74#define CR30 CTL_REG(0x0078) 75#define CR31 CTL_REG(0x007C) /* TX power control for RF in CCK mode */ 76#define CR32 CTL_REG(0x0080) 77#define CR33 CTL_REG(0x0084) 78#define CR34 CTL_REG(0x0088) 79#define CR35 CTL_REG(0x008C) 80#define CR36 CTL_REG(0x0090) 81#define CR37 CTL_REG(0x0094) 82#define CR38 CTL_REG(0x0098) 83#define CR39 CTL_REG(0x009C) 84#define CR40 CTL_REG(0x00A0) 85#define CR41 CTL_REG(0x00A4) 86#define CR42 CTL_REG(0x00A8) 87#define CR43 CTL_REG(0x00AC) 88#define CR44 CTL_REG(0x00B0) 89#define CR45 CTL_REG(0x00B4) 90#define CR46 CTL_REG(0x00B8) 91#define CR47 CTL_REG(0x00BC) /* CCK baseband gain 92 * (patch value might be in EEPROM) 93 */ 94#define CR48 CTL_REG(0x00C0) 95#define CR49 CTL_REG(0x00C4) 96#define CR50 CTL_REG(0x00C8) 97#define CR51 CTL_REG(0x00CC) /* TX power control for RF in 6-36M modes */ 98#define CR52 CTL_REG(0x00D0) /* TX power control for RF in 48M mode */ 99#define CR53 CTL_REG(0x00D4) /* TX power control for RF in 54M mode */ 100#define CR54 CTL_REG(0x00D8) 101#define CR55 CTL_REG(0x00DC) 102#define CR56 CTL_REG(0x00E0) 103#define CR57 CTL_REG(0x00E4) 104#define CR58 CTL_REG(0x00E8) 105#define CR59 CTL_REG(0x00EC) 106#define CR60 CTL_REG(0x00F0) 107#define CR61 CTL_REG(0x00F4) 108#define CR62 CTL_REG(0x00F8) 109#define CR63 CTL_REG(0x00FC) 110#define CR64 CTL_REG(0x0100) 111#define CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ 112#define CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ 113#define CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ 114#define CR68 CTL_REG(0x0110) /* CCK calibration */ 115#define CR69 CTL_REG(0x0114) 116#define CR70 CTL_REG(0x0118) 117#define CR71 CTL_REG(0x011C) 118#define CR72 CTL_REG(0x0120) 119#define CR73 CTL_REG(0x0124) 120#define CR74 CTL_REG(0x0128) 121#define CR75 CTL_REG(0x012C) 122#define CR76 CTL_REG(0x0130) 123#define CR77 CTL_REG(0x0134) 124#define CR78 CTL_REG(0x0138) 125#define CR79 CTL_REG(0x013C) 126#define CR80 CTL_REG(0x0140) 127#define CR81 CTL_REG(0x0144) 128#define CR82 CTL_REG(0x0148) 129#define CR83 CTL_REG(0x014C) 130#define CR84 CTL_REG(0x0150) 131#define CR85 CTL_REG(0x0154) 132#define CR86 CTL_REG(0x0158) 133#define CR87 CTL_REG(0x015C) 134#define CR88 CTL_REG(0x0160) 135#define CR89 CTL_REG(0x0164) 136#define CR90 CTL_REG(0x0168) 137#define CR91 CTL_REG(0x016C) 138#define CR92 CTL_REG(0x0170) 139#define CR93 CTL_REG(0x0174) 140#define CR94 CTL_REG(0x0178) 141#define CR95 CTL_REG(0x017C) 142#define CR96 CTL_REG(0x0180) 143#define CR97 CTL_REG(0x0184) 144#define CR98 CTL_REG(0x0188) 145#define CR99 CTL_REG(0x018C) 146#define CR100 CTL_REG(0x0190) 147#define CR101 CTL_REG(0x0194) 148#define CR102 CTL_REG(0x0198) 149#define CR103 CTL_REG(0x019C) 150#define CR104 CTL_REG(0x01A0) 151#define CR105 CTL_REG(0x01A4) 152#define CR106 CTL_REG(0x01A8) 153#define CR107 CTL_REG(0x01AC) 154#define CR108 CTL_REG(0x01B0) 155#define CR109 CTL_REG(0x01B4) 156#define CR110 CTL_REG(0x01B8) 157#define CR111 CTL_REG(0x01BC) 158#define CR112 CTL_REG(0x01C0) 159#define CR113 CTL_REG(0x01C4) 160#define CR114 CTL_REG(0x01C8) 161#define CR115 CTL_REG(0x01CC) 162#define CR116 CTL_REG(0x01D0) 163#define CR117 CTL_REG(0x01D4) 164#define CR118 CTL_REG(0x01D8) 165#define CR119 CTL_REG(0x01DC) 166#define CR120 CTL_REG(0x01E0) 167#define CR121 CTL_REG(0x01E4) 168#define CR122 CTL_REG(0x01E8) 169#define CR123 CTL_REG(0x01EC) 170#define CR124 CTL_REG(0x01F0) 171#define CR125 CTL_REG(0x01F4) 172#define CR126 CTL_REG(0x01F8) 173#define CR127 CTL_REG(0x01FC) 174#define CR128 CTL_REG(0x0200) 175#define CR129 CTL_REG(0x0204) 176#define CR130 CTL_REG(0x0208) 177#define CR131 CTL_REG(0x020C) 178#define CR132 CTL_REG(0x0210) 179#define CR133 CTL_REG(0x0214) 180#define CR134 CTL_REG(0x0218) 181#define CR135 CTL_REG(0x021C) 182#define CR136 CTL_REG(0x0220) 183#define CR137 CTL_REG(0x0224) 184#define CR138 CTL_REG(0x0228) 185#define CR139 CTL_REG(0x022C) 186#define CR140 CTL_REG(0x0230) 187#define CR141 CTL_REG(0x0234) 188#define CR142 CTL_REG(0x0238) 189#define CR143 CTL_REG(0x023C) 190#define CR144 CTL_REG(0x0240) 191#define CR145 CTL_REG(0x0244) 192#define CR146 CTL_REG(0x0248) 193#define CR147 CTL_REG(0x024C) 194#define CR148 CTL_REG(0x0250) 195#define CR149 CTL_REG(0x0254) 196#define CR150 CTL_REG(0x0258) 197#define CR151 CTL_REG(0x025C) 198#define CR152 CTL_REG(0x0260) 199#define CR153 CTL_REG(0x0264) 200#define CR154 CTL_REG(0x0268) 201#define CR155 CTL_REG(0x026C) 202#define CR156 CTL_REG(0x0270) 203#define CR157 CTL_REG(0x0274) 204#define CR158 CTL_REG(0x0278) 205#define CR159 CTL_REG(0x027C) 206#define CR160 CTL_REG(0x0280) 207#define CR161 CTL_REG(0x0284) 208#define CR162 CTL_REG(0x0288) 209#define CR163 CTL_REG(0x028C) 210#define CR164 CTL_REG(0x0290) 211#define CR165 CTL_REG(0x0294) 212#define CR166 CTL_REG(0x0298) 213#define CR167 CTL_REG(0x029C) 214#define CR168 CTL_REG(0x02A0) 215#define CR169 CTL_REG(0x02A4) 216#define CR170 CTL_REG(0x02A8) 217#define CR171 CTL_REG(0x02AC) 218#define CR172 CTL_REG(0x02B0) 219#define CR173 CTL_REG(0x02B4) 220#define CR174 CTL_REG(0x02B8) 221#define CR175 CTL_REG(0x02BC) 222#define CR176 CTL_REG(0x02C0) 223#define CR177 CTL_REG(0x02C4) 224#define CR178 CTL_REG(0x02C8) 225#define CR179 CTL_REG(0x02CC) 226#define CR180 CTL_REG(0x02D0) 227#define CR181 CTL_REG(0x02D4) 228#define CR182 CTL_REG(0x02D8) 229#define CR183 CTL_REG(0x02DC) 230#define CR184 CTL_REG(0x02E0) 231#define CR185 CTL_REG(0x02E4) 232#define CR186 CTL_REG(0x02E8) 233#define CR187 CTL_REG(0x02EC) 234#define CR188 CTL_REG(0x02F0) 235#define CR189 CTL_REG(0x02F4) 236#define CR190 CTL_REG(0x02F8) 237#define CR191 CTL_REG(0x02FC) 238#define CR192 CTL_REG(0x0300) 239#define CR193 CTL_REG(0x0304) 240#define CR194 CTL_REG(0x0308) 241#define CR195 CTL_REG(0x030C) 242#define CR196 CTL_REG(0x0310) 243#define CR197 CTL_REG(0x0314) 244#define CR198 CTL_REG(0x0318) 245#define CR199 CTL_REG(0x031C) 246#define CR200 CTL_REG(0x0320) 247#define CR201 CTL_REG(0x0324) 248#define CR202 CTL_REG(0x0328) 249#define CR203 CTL_REG(0x032C) /* I2C bus template value & flash control */ 250#define CR204 CTL_REG(0x0330) 251#define CR205 CTL_REG(0x0334) 252#define CR206 CTL_REG(0x0338) 253#define CR207 CTL_REG(0x033C) 254#define CR208 CTL_REG(0x0340) 255#define CR209 CTL_REG(0x0344) 256#define CR210 CTL_REG(0x0348) 257#define CR211 CTL_REG(0x034C) 258#define CR212 CTL_REG(0x0350) 259#define CR213 CTL_REG(0x0354) 260#define CR214 CTL_REG(0x0358) 261#define CR215 CTL_REG(0x035C) 262#define CR216 CTL_REG(0x0360) 263#define CR217 CTL_REG(0x0364) 264#define CR218 CTL_REG(0x0368) 265#define CR219 CTL_REG(0x036C) 266#define CR220 CTL_REG(0x0370) 267#define CR221 CTL_REG(0x0374) 268#define CR222 CTL_REG(0x0378) 269#define CR223 CTL_REG(0x037C) 270#define CR224 CTL_REG(0x0380) 271#define CR225 CTL_REG(0x0384) 272#define CR226 CTL_REG(0x0388) 273#define CR227 CTL_REG(0x038C) 274#define CR228 CTL_REG(0x0390) 275#define CR229 CTL_REG(0x0394) 276#define CR230 CTL_REG(0x0398) 277#define CR231 CTL_REG(0x039C) 278#define CR232 CTL_REG(0x03A0) 279#define CR233 CTL_REG(0x03A4) 280#define CR234 CTL_REG(0x03A8) 281#define CR235 CTL_REG(0x03AC) 282#define CR236 CTL_REG(0x03B0) 283 284#define CR240 CTL_REG(0x03C0) 285/* bit 7: host-controlled RF register writes 286 * CR241-CR245: for hardware controlled writing of RF bits, not needed for 287 * USB 288 */ 289#define CR241 CTL_REG(0x03C4) 290#define CR242 CTL_REG(0x03C8) 291#define CR243 CTL_REG(0x03CC) 292#define CR244 CTL_REG(0x03D0) 293#define CR245 CTL_REG(0x03D4) 294 295#define CR251 CTL_REG(0x03EC) /* only used for activation and deactivation of 296 * Airoha RFs AL2230 and AL7230B 297 */ 298#define CR252 CTL_REG(0x03F0) 299#define CR253 CTL_REG(0x03F4) 300#define CR254 CTL_REG(0x03F8) 301#define CR255 CTL_REG(0x03FC) 302 303#define CR_MAX_PHY_REG 255 304 305/* Taken from the ZYDAS driver, not all of them are relevant for the ZSD1211 306 * driver. 307 */ 308 309#define CR_RF_IF_CLK CTL_REG(0x0400) 310#define CR_RF_IF_DATA CTL_REG(0x0404) 311#define CR_PE1_PE2 CTL_REG(0x0408) 312#define CR_PE2_DLY CTL_REG(0x040C) 313#define CR_LE1 CTL_REG(0x0410) 314#define CR_LE2 CTL_REG(0x0414) 315/* Seems to enable/disable GPI (General Purpose IO?) */ 316#define CR_GPI_EN CTL_REG(0x0418) 317#define CR_RADIO_PD CTL_REG(0x042C) 318#define CR_RF2948_PD CTL_REG(0x042C) 319#define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) 320#define CR_CONFIG_PHILIPS CTL_REG(0x0440) 321#define CR_SA2400_SER_AP CTL_REG(0x0444) 322#define CR_I2C_WRITE CTL_REG(0x0444) 323#define CR_SA2400_SER_RP CTL_REG(0x0448) 324#define CR_RADIO_PE CTL_REG(0x0458) 325#define CR_RST_BUS_MASTER CTL_REG(0x045C) 326#define CR_RFCFG CTL_REG(0x0464) 327#define CR_HSTSCHG CTL_REG(0x046C) 328#define CR_PHY_ON CTL_REG(0x0474) 329#define CR_RX_DELAY CTL_REG(0x0478) 330#define CR_RX_PE_DELAY CTL_REG(0x047C) 331#define CR_GPIO_1 CTL_REG(0x0490) 332#define CR_GPIO_2 CTL_REG(0x0494) 333#define CR_EncryBufMux CTL_REG(0x04A8) 334#define CR_PS_CTRL CTL_REG(0x0500) 335#define CR_ADDA_PWR_DWN CTL_REG(0x0504) 336#define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) 337#define CR_MAC_PS_STATE CTL_REG(0x050C) 338 339#define CR_INTERRUPT CTL_REG(0x0510) 340#define INT_TX_COMPLETE (1 << 0) 341#define INT_RX_COMPLETE (1 << 1) 342#define INT_RETRY_FAIL (1 << 2) 343#define INT_WAKEUP (1 << 3) 344#define INT_DTIM_NOTIFY (1 << 5) 345#define INT_CFG_NEXT_BCN (1 << 6) 346#define INT_BUS_ABORT (1 << 7) 347#define INT_TX_FIFO_READY (1 << 8) 348#define INT_UART (1 << 9) 349#define INT_TX_COMPLETE_EN (1 << 16) 350#define INT_RX_COMPLETE_EN (1 << 17) 351#define INT_RETRY_FAIL_EN (1 << 18) 352#define INT_WAKEUP_EN (1 << 19) 353#define INT_DTIM_NOTIFY_EN (1 << 21) 354#define INT_CFG_NEXT_BCN_EN (1 << 22) 355#define INT_BUS_ABORT_EN (1 << 23) 356#define INT_TX_FIFO_READY_EN (1 << 24) 357#define INT_UART_EN (1 << 25) 358 359#define CR_TSF_LOW_PART CTL_REG(0x0514) 360#define CR_TSF_HIGH_PART CTL_REG(0x0518) 361 362/* Following three values are in time units (1024us) 363 * Following condition must be met: 364 * atim < tbtt < bcn 365 */ 366#define CR_ATIM_WND_PERIOD CTL_REG(0x051C) 367#define CR_BCN_INTERVAL CTL_REG(0x0520) 368#define CR_PRE_TBTT CTL_REG(0x0524) 369/* in units of TU(1024us) */ 370 371/* for UART support */ 372#define CR_UART_RBR_THR_DLL CTL_REG(0x0540) 373#define CR_UART_DLM_IER CTL_REG(0x0544) 374#define CR_UART_IIR_FCR CTL_REG(0x0548) 375#define CR_UART_LCR CTL_REG(0x054c) 376#define CR_UART_MCR CTL_REG(0x0550) 377#define CR_UART_LSR CTL_REG(0x0554) 378#define CR_UART_MSR CTL_REG(0x0558) 379#define CR_UART_ECR CTL_REG(0x055c) 380#define CR_UART_STATUS CTL_REG(0x0560) 381 382#define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600) 383#define CR_PCI_TX_AddR_P2 CTL_REG(0x0604) 384#define CR_PCI_RX_AddR_P1 CTL_REG(0x0608) 385#define CR_PCI_RX_AddR_P2 CTL_REG(0x060C) 386 387/* must be overwritten if custom MAC address will be used */ 388#define CR_MAC_ADDR_P1 CTL_REG(0x0610) 389#define CR_MAC_ADDR_P2 CTL_REG(0x0614) 390#define CR_BSSID_P1 CTL_REG(0x0618) 391#define CR_BSSID_P2 CTL_REG(0x061C) 392#define CR_BCN_PLCP_CFG CTL_REG(0x0620) 393#define CR_GROUP_HASH_P1 CTL_REG(0x0624) 394#define CR_GROUP_HASH_P2 CTL_REG(0x0628) 395#define CR_RX_TIMEOUT CTL_REG(0x062C) 396 397/* Basic rates supported by the BSS. When producing ACK or CTS messages, the 398 * device will use a rate in this table that is less than or equal to the rate 399 * of the incoming frame which prompted the response */ 400#define CR_BASIC_RATE_TBL CTL_REG(0x0630) 401#define CR_RATE_1M (1 << 0) /* 802.11b */ 402#define CR_RATE_2M (1 << 1) /* 802.11b */ 403#define CR_RATE_5_5M (1 << 2) /* 802.11b */ 404#define CR_RATE_11M (1 << 3) /* 802.11b */ 405#define CR_RATE_6M (1 << 8) /* 802.11g */ 406#define CR_RATE_9M (1 << 9) /* 802.11g */ 407#define CR_RATE_12M (1 << 10) /* 802.11g */ 408#define CR_RATE_18M (1 << 11) /* 802.11g */ 409#define CR_RATE_24M (1 << 12) /* 802.11g */ 410#define CR_RATE_36M (1 << 13) /* 802.11g */ 411#define CR_RATE_48M (1 << 14) /* 802.11g */ 412#define CR_RATE_54M (1 << 15) /* 802.11g */ 413#define CR_RATES_80211G 0xff00 414#define CR_RATES_80211B 0x000f 415 416/* Mandatory rates required in the BSS. When producing ACK or CTS messages, if 417 * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will 418 * look for a rate in this table that is less than or equal to the rate of 419 * the incoming frame. */ 420#define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) 421#define CR_RTS_CTS_RATE CTL_REG(0x0638) 422 423#define CR_WEP_PROTECT CTL_REG(0x063C) 424#define CR_RX_THRESHOLD CTL_REG(0x0640) 425 426/* register for controlling the LEDS */ 427#define CR_LED CTL_REG(0x0644) 428/* masks for controlling LEDs */ 429#define LED1 (1 << 8) 430#define LED2 (1 << 9) 431#define LED_SW (1 << 10) 432 433/* Seems to indicate that the configuration is over. 434 */ 435#define CR_AFTER_PNP CTL_REG(0x0648) 436#define CR_ACK_TIME_80211 CTL_REG(0x0658) 437 438#define CR_RX_OFFSET CTL_REG(0x065c) 439 440#define CR_PHY_DELAY CTL_REG(0x066C) 441#define CR_BCN_FIFO CTL_REG(0x0670) 442#define CR_SNIFFER_ON CTL_REG(0x0674) 443 444#define CR_ENCRYPTION_TYPE CTL_REG(0x0678) 445#define NO_WEP 0 446#define WEP64 1 447#define WEP128 5 448#define WEP256 6 449#define ENC_SNIFFER 8 450 451#define CR_ZD1211_RETRY_MAX CTL_REG(0x067C) 452 453#define CR_REG1 CTL_REG(0x0680) 454/* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical 455 * registers, so one could argue it is a LOCK bit. But calling it 456 * LOCK_PHY_REGS makes it confusing. 457 */ 458#define UNLOCK_PHY_REGS (1 << 7) 459 460#define CR_DEVICE_STATE CTL_REG(0x0684) 461#define CR_UNDERRUN_CNT CTL_REG(0x0688) 462 463#define CR_RX_FILTER CTL_REG(0x068c) 464#define RX_FILTER_ASSOC_RESPONSE (1 << 1) 465#define RX_FILTER_REASSOC_RESPONSE (1 << 3) 466#define RX_FILTER_PROBE_RESPONSE (1 << 5) 467#define RX_FILTER_BEACON (1 << 8) 468#define RX_FILTER_DISASSOC (1 << 10) 469#define RX_FILTER_AUTH (1 << 11) 470#define AP_RX_FILTER 0x0400feff 471#define STA_RX_FILTER 0x0000ffff 472 473/* Monitor mode sets filter to 0xfffff */ 474 475#define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690) 476#define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694) 477 478#define CR_IFS_VALUE CTL_REG(0x0698) 479#define IFS_VALUE_DIFS_SH 0 480#define IFS_VALUE_EIFS_SH 12 481#define IFS_VALUE_SIFS_SH 24 482#define IFS_VALUE_DEFAULT (( 50 << IFS_VALUE_DIFS_SH) | \ 483 (1148 << IFS_VALUE_EIFS_SH) | \ 484 ( 10 << IFS_VALUE_SIFS_SH)) 485 486#define CR_RX_TIME_OUT CTL_REG(0x069C) 487#define CR_TOTAL_RX_FRM CTL_REG(0x06A0) 488#define CR_CRC32_CNT CTL_REG(0x06A4) 489#define CR_CRC16_CNT CTL_REG(0x06A8) 490#define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC) 491#define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0) 492 493#define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC) 494 495#define CR_NAV_CNT CTL_REG(0x06C4) 496#define CR_NAV_CCA CTL_REG(0x06C8) 497#define CR_RETRY_CNT CTL_REG(0x06CC) 498 499#define CR_READ_TCB_ADDR CTL_REG(0x06E8) 500#define CR_READ_RFD_ADDR CTL_REG(0x06EC) 501#define CR_CWMIN_CWMAX CTL_REG(0x06F0) 502#define CR_TOTAL_TX_FRM CTL_REG(0x06F4) 503 504/* CAM: Continuous Access Mode (power management) */ 505#define CR_CAM_MODE CTL_REG(0x0700) 506#define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704) 507#define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708) 508#define CR_CAM_ADDRESS CTL_REG(0x070C) 509#define CR_CAM_DATA CTL_REG(0x0710) 510 511#define CR_ROMDIR CTL_REG(0x0714) 512 513#define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714) 514#define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718) 515 516#define CR_WEPKEY0 CTL_REG(0x0720) 517#define CR_WEPKEY1 CTL_REG(0x0724) 518#define CR_WEPKEY2 CTL_REG(0x0728) 519#define CR_WEPKEY3 CTL_REG(0x072C) 520#define CR_WEPKEY4 CTL_REG(0x0730) 521#define CR_WEPKEY5 CTL_REG(0x0734) 522#define CR_WEPKEY6 CTL_REG(0x0738) 523#define CR_WEPKEY7 CTL_REG(0x073C) 524#define CR_WEPKEY8 CTL_REG(0x0740) 525#define CR_WEPKEY9 CTL_REG(0x0744) 526#define CR_WEPKEY10 CTL_REG(0x0748) 527#define CR_WEPKEY11 CTL_REG(0x074C) 528#define CR_WEPKEY12 CTL_REG(0x0750) 529#define CR_WEPKEY13 CTL_REG(0x0754) 530#define CR_WEPKEY14 CTL_REG(0x0758) 531#define CR_WEPKEY15 CTL_REG(0x075c) 532#define CR_TKIP_MODE CTL_REG(0x0760) 533 534#define CR_EEPROM_PROTECT0 CTL_REG(0x0758) 535#define CR_EEPROM_PROTECT1 CTL_REG(0x075C) 536 537#define CR_DBG_FIFO_RD CTL_REG(0x0800) 538#define CR_DBG_SELECT CTL_REG(0x0804) 539#define CR_FIFO_Length CTL_REG(0x0808) 540 541 542#define CR_RSSI_MGC CTL_REG(0x0810) 543 544#define CR_PON CTL_REG(0x0818) 545#define CR_RX_ON CTL_REG(0x081C) 546#define CR_TX_ON CTL_REG(0x0820) 547#define CR_CHIP_EN CTL_REG(0x0824) 548#define CR_LO_SW CTL_REG(0x0828) 549#define CR_TXRX_SW CTL_REG(0x082C) 550#define CR_S_MD CTL_REG(0x0830) 551 552#define CR_USB_DEBUG_PORT CTL_REG(0x0888) 553 554#define CR_ZD1211B_TX_PWR_CTL1 CTL_REG(0x0b00) 555#define CR_ZD1211B_TX_PWR_CTL2 CTL_REG(0x0b04) 556#define CR_ZD1211B_TX_PWR_CTL3 CTL_REG(0x0b08) 557#define CR_ZD1211B_TX_PWR_CTL4 CTL_REG(0x0b0c) 558#define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10) 559#define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14) 560#define CR_ZD1211B_TXOP CTL_REG(0x0b20) 561#define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28) 562 563#define CWIN_SIZE 0x007f043f 564 565 566#define HWINT_ENABLED 0x004f0000 567#define HWINT_DISABLED 0 568 569#define E2P_PWR_INT_GUARD 8 570#define E2P_CHANNEL_COUNT 14 571 572/* If you compare this addresses with the ZYDAS orignal driver, please notify 573 * that we use word mapping for the EEPROM. 574 */ 575 576/* 577 * Upper 16 bit contains the regulatory domain. 578 */ 579#define E2P_SUBID E2P_REG(0x00) 580#define E2P_POD E2P_REG(0x02) 581#define E2P_MAC_ADDR_P1 E2P_REG(0x04) 582#define E2P_MAC_ADDR_P2 E2P_REG(0x06) 583#define E2P_PWR_CAL_VALUE1 E2P_REG(0x08) 584#define E2P_PWR_CAL_VALUE2 E2P_REG(0x0a) 585#define E2P_PWR_CAL_VALUE3 E2P_REG(0x0c) 586#define E2P_PWR_CAL_VALUE4 E2P_REG(0x0e) 587#define E2P_PWR_INT_VALUE1 E2P_REG(0x10) 588#define E2P_PWR_INT_VALUE2 E2P_REG(0x12) 589#define E2P_PWR_INT_VALUE3 E2P_REG(0x14) 590#define E2P_PWR_INT_VALUE4 E2P_REG(0x16) 591 592/* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) 593 * also only 11 channels. */ 594#define E2P_ALLOWED_CHANNEL E2P_REG(0x18) 595 596#define E2P_PHY_REG E2P_REG(0x1a) 597#define E2P_DEVICE_VER E2P_REG(0x20) 598#define E2P_36M_CAL_VALUE1 E2P_REG(0x28) 599#define E2P_36M_CAL_VALUE2 E2P_REG(0x2a) 600#define E2P_36M_CAL_VALUE3 E2P_REG(0x2c) 601#define E2P_36M_CAL_VALUE4 E2P_REG(0x2e) 602#define E2P_11A_INT_VALUE1 E2P_REG(0x30) 603#define E2P_11A_INT_VALUE2 E2P_REG(0x32) 604#define E2P_11A_INT_VALUE3 E2P_REG(0x34) 605#define E2P_11A_INT_VALUE4 E2P_REG(0x36) 606#define E2P_48M_CAL_VALUE1 E2P_REG(0x38) 607#define E2P_48M_CAL_VALUE2 E2P_REG(0x3a) 608#define E2P_48M_CAL_VALUE3 E2P_REG(0x3c) 609#define E2P_48M_CAL_VALUE4 E2P_REG(0x3e) 610#define E2P_48M_INT_VALUE1 E2P_REG(0x40) 611#define E2P_48M_INT_VALUE2 E2P_REG(0x42) 612#define E2P_48M_INT_VALUE3 E2P_REG(0x44) 613#define E2P_48M_INT_VALUE4 E2P_REG(0x46) 614#define E2P_54M_CAL_VALUE1 E2P_REG(0x48) /* ??? */ 615#define E2P_54M_CAL_VALUE2 E2P_REG(0x4a) 616#define E2P_54M_CAL_VALUE3 E2P_REG(0x4c) 617#define E2P_54M_CAL_VALUE4 E2P_REG(0x4e) 618#define E2P_54M_INT_VALUE1 E2P_REG(0x50) 619#define E2P_54M_INT_VALUE2 E2P_REG(0x52) 620#define E2P_54M_INT_VALUE3 E2P_REG(0x54) 621#define E2P_54M_INT_VALUE4 E2P_REG(0x56) 622 623/* All 16 bit values */ 624#define FW_FIRMWARE_VER FW_REG(0) 625/* non-zero if USB high speed connection */ 626#define FW_USB_SPEED FW_REG(1) 627#define FW_FIX_TX_RATE FW_REG(2) 628/* Seems to be able to control LEDs over the firmware */ 629#define FW_LINK_STATUS FW_REG(3) 630#define FW_SOFT_RESET FW_REG(4) 631#define FW_FLASH_CHK FW_REG(5) 632 633#define FW_LINK_OFF 0x0 634#define FW_LINK_TX 0x1 635/* 0x2 - link led on? */ 636 637enum { 638 CR_BASE_OFFSET = 0x9000, 639 FW_START_OFFSET = 0xee00, 640 FW_BASE_ADDR_OFFSET = FW_START_OFFSET + 0x1d, 641 EEPROM_START_OFFSET = 0xf800, 642 EEPROM_SIZE = 0x800, /* words */ 643 LOAD_CODE_SIZE = 0xe, /* words */ 644 LOAD_VECT_SIZE = 0x10000 - 0xfff7, /* words */ 645 EEPROM_REGS_OFFSET = LOAD_CODE_SIZE + LOAD_VECT_SIZE, 646 EEPROM_REGS_SIZE = 0x7e, /* words */ 647 E2P_BASE_OFFSET = EEPROM_START_OFFSET + 648 EEPROM_REGS_OFFSET, 649}; 650 651#define FW_REG_TABLE_ADDR USB_ADDR(FW_START_OFFSET + 0x1d) 652 653enum { 654 /* indices for ofdm_cal_values */ 655 OFDM_36M_INDEX = 0, 656 OFDM_48M_INDEX = 1, 657 OFDM_54M_INDEX = 2, 658}; 659 660struct zd_chip { 661 struct zd_usb usb; 662 struct zd_rf rf; 663 struct mutex mutex; 664 u8 e2p_mac[ETH_ALEN]; 665 /* EepSetPoint in the vendor driver */ 666 u8 pwr_cal_values[E2P_CHANNEL_COUNT]; 667 /* integration values in the vendor driver */ 668 u8 pwr_int_values[E2P_CHANNEL_COUNT]; 669 /* SetPointOFDM in the vendor driver */ 670 u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; 671 u16 link_led; 672 unsigned int pa_type:4, 673 patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, 674 new_phy_layout:1, 675 is_zd1211b:1, supports_tx_led:1; 676}; 677 678static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) 679{ 680 return container_of(usb, struct zd_chip, usb); 681} 682 683static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) 684{ 685 return container_of(rf, struct zd_chip, rf); 686} 687 688#define zd_chip_dev(chip) (&(chip)->usb.intf->dev) 689 690void zd_chip_init(struct zd_chip *chip, 691 struct net_device *netdev, 692 struct usb_interface *intf); 693void zd_chip_clear(struct zd_chip *chip); 694int zd_chip_init_hw(struct zd_chip *chip, u8 device_type); 695int zd_chip_reset(struct zd_chip *chip); 696 697static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, 698 const zd_addr_t *addresses, 699 unsigned int count) 700{ 701 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 702 return zd_usb_ioread16v(&chip->usb, values, addresses, count); 703} 704 705static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, 706 const zd_addr_t addr) 707{ 708 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 709 return zd_usb_ioread16(&chip->usb, value, addr); 710} 711 712int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, 713 const zd_addr_t *addresses, unsigned int count); 714 715static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, 716 const zd_addr_t addr) 717{ 718 return zd_ioread32v_locked(chip, value, (const zd_addr_t *)&addr, 1); 719} 720 721static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, 722 zd_addr_t addr) 723{ 724 struct zd_ioreq16 ioreq; 725 726 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 727 ioreq.addr = addr; 728 ioreq.value = value; 729 730 return zd_usb_iowrite16v(&chip->usb, &ioreq, 1); 731} 732 733int zd_iowrite16a_locked(struct zd_chip *chip, 734 const struct zd_ioreq16 *ioreqs, unsigned int count); 735 736int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 737 unsigned int count); 738 739static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, 740 zd_addr_t addr) 741{ 742 struct zd_ioreq32 ioreq; 743 744 ioreq.addr = addr; 745 ioreq.value = value; 746 747 return _zd_iowrite32v_locked(chip, &ioreq, 1); 748} 749 750int zd_iowrite32a_locked(struct zd_chip *chip, 751 const struct zd_ioreq32 *ioreqs, unsigned int count); 752 753static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) 754{ 755 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 756 return zd_usb_rfwrite(&chip->usb, value, bits); 757} 758 759int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value); 760 761int zd_rfwritev_locked(struct zd_chip *chip, 762 const u32* values, unsigned int count, u8 bits); 763int zd_rfwritev_cr_locked(struct zd_chip *chip, 764 const u32* values, unsigned int count); 765 766/* Locking functions for reading and writing registers. 767 * The different parameters are intentional. 768 */ 769int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); 770int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); 771int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); 772int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); 773int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, 774 u32 *values, unsigned int count); 775int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 776 unsigned int count); 777 778int zd_chip_set_channel(struct zd_chip *chip, u8 channel); 779static inline u8 _zd_chip_get_channel(struct zd_chip *chip) 780{ 781 return chip->rf.channel; 782} 783u8 zd_chip_get_channel(struct zd_chip *chip); 784int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); 785void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr); 786int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr); 787int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); 788int zd_chip_switch_radio_on(struct zd_chip *chip); 789int zd_chip_switch_radio_off(struct zd_chip *chip); 790int zd_chip_enable_int(struct zd_chip *chip); 791void zd_chip_disable_int(struct zd_chip *chip); 792int zd_chip_enable_rx(struct zd_chip *chip); 793void zd_chip_disable_rx(struct zd_chip *chip); 794int zd_chip_enable_hwint(struct zd_chip *chip); 795int zd_chip_disable_hwint(struct zd_chip *chip); 796 797static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) 798{ 799 return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); 800} 801 802static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) 803{ 804 return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type); 805} 806 807static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) 808{ 809 return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); 810} 811 812int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); 813 814static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter) 815{ 816 return zd_iowrite32(chip, CR_RX_FILTER, filter); 817} 818 819int zd_chip_lock_phy_regs(struct zd_chip *chip); 820int zd_chip_unlock_phy_regs(struct zd_chip *chip); 821 822enum led_status { 823 LED_OFF = 0, 824 LED_SCANNING = 1, 825 LED_ASSOCIATED = 2, 826}; 827 828int zd_chip_control_leds(struct zd_chip *chip, enum led_status status); 829 830int zd_set_beacon_interval(struct zd_chip *chip, u32 interval); 831 832static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) 833{ 834 return zd_ioread32(chip, CR_BCN_INTERVAL, interval); 835} 836 837struct rx_status; 838 839u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, 840 const struct rx_status *status); 841u8 zd_rx_strength_percent(u8 rssi); 842 843u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status); 844 845#endif /* _ZD_CHIP_H */ 846