fsl_udc_core.c revision 2cd5bb29a42f305c5749571c8cd693fbe69cc28d
1/* 2 * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Li Yang <leoli@freescale.com> 5 * Jiang Bo <tanya.jiang@freescale.com> 6 * 7 * Description: 8 * Freescale high-speed USB SOC DR module device controller driver. 9 * This can be found on MPC8349E/MPC8313E cpus. 10 * The driver is previously named as mpc_udc. Based on bare board 11 * code from Dave Liu and Shlomi Gridish. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19#undef VERBOSE 20 21#include <linux/module.h> 22#include <linux/kernel.h> 23#include <linux/ioport.h> 24#include <linux/types.h> 25#include <linux/errno.h> 26#include <linux/slab.h> 27#include <linux/init.h> 28#include <linux/list.h> 29#include <linux/interrupt.h> 30#include <linux/proc_fs.h> 31#include <linux/mm.h> 32#include <linux/moduleparam.h> 33#include <linux/device.h> 34#include <linux/usb/ch9.h> 35#include <linux/usb/gadget.h> 36#include <linux/usb/otg.h> 37#include <linux/dma-mapping.h> 38#include <linux/platform_device.h> 39#include <linux/fsl_devices.h> 40#include <linux/dmapool.h> 41#include <linux/delay.h> 42 43#include <asm/byteorder.h> 44#include <asm/io.h> 45#include <asm/system.h> 46#include <asm/unaligned.h> 47#include <asm/dma.h> 48 49#include "fsl_usb2_udc.h" 50 51#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver" 52#define DRIVER_AUTHOR "Li Yang/Jiang Bo" 53#define DRIVER_VERSION "Apr 20, 2007" 54 55#define DMA_ADDR_INVALID (~(dma_addr_t)0) 56 57static const char driver_name[] = "fsl-usb2-udc"; 58static const char driver_desc[] = DRIVER_DESC; 59 60static struct usb_dr_device *dr_regs; 61#ifndef CONFIG_ARCH_MXC 62static struct usb_sys_interface *usb_sys_regs; 63#endif 64 65/* it is initialized in probe() */ 66static struct fsl_udc *udc_controller = NULL; 67 68static const struct usb_endpoint_descriptor 69fsl_ep0_desc = { 70 .bLength = USB_DT_ENDPOINT_SIZE, 71 .bDescriptorType = USB_DT_ENDPOINT, 72 .bEndpointAddress = 0, 73 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 74 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, 75}; 76 77static void fsl_ep_fifo_flush(struct usb_ep *_ep); 78 79#ifdef CONFIG_PPC32 80#define fsl_readl(addr) in_le32(addr) 81#define fsl_writel(val32, addr) out_le32(addr, val32) 82#else 83#define fsl_readl(addr) readl(addr) 84#define fsl_writel(val32, addr) writel(val32, addr) 85#endif 86 87/******************************************************************** 88 * Internal Used Function 89********************************************************************/ 90/*----------------------------------------------------------------- 91 * done() - retire a request; caller blocked irqs 92 * @status : request status to be set, only works when 93 * request is still in progress. 94 *--------------------------------------------------------------*/ 95static void done(struct fsl_ep *ep, struct fsl_req *req, int status) 96{ 97 struct fsl_udc *udc = NULL; 98 unsigned char stopped = ep->stopped; 99 struct ep_td_struct *curr_td, *next_td; 100 int j; 101 102 udc = (struct fsl_udc *)ep->udc; 103 /* Removed the req from fsl_ep->queue */ 104 list_del_init(&req->queue); 105 106 /* req.status should be set as -EINPROGRESS in ep_queue() */ 107 if (req->req.status == -EINPROGRESS) 108 req->req.status = status; 109 else 110 status = req->req.status; 111 112 /* Free dtd for the request */ 113 next_td = req->head; 114 for (j = 0; j < req->dtd_count; j++) { 115 curr_td = next_td; 116 if (j != req->dtd_count - 1) { 117 next_td = curr_td->next_td_virt; 118 } 119 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); 120 } 121 122 if (req->mapped) { 123 dma_unmap_single(ep->udc->gadget.dev.parent, 124 req->req.dma, req->req.length, 125 ep_is_in(ep) 126 ? DMA_TO_DEVICE 127 : DMA_FROM_DEVICE); 128 req->req.dma = DMA_ADDR_INVALID; 129 req->mapped = 0; 130 } else 131 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, 132 req->req.dma, req->req.length, 133 ep_is_in(ep) 134 ? DMA_TO_DEVICE 135 : DMA_FROM_DEVICE); 136 137 if (status && (status != -ESHUTDOWN)) 138 VDBG("complete %s req %p stat %d len %u/%u", 139 ep->ep.name, &req->req, status, 140 req->req.actual, req->req.length); 141 142 ep->stopped = 1; 143 144 spin_unlock(&ep->udc->lock); 145 /* complete() is from gadget layer, 146 * eg fsg->bulk_in_complete() */ 147 if (req->req.complete) 148 req->req.complete(&ep->ep, &req->req); 149 150 spin_lock(&ep->udc->lock); 151 ep->stopped = stopped; 152} 153 154/*----------------------------------------------------------------- 155 * nuke(): delete all requests related to this ep 156 * called with spinlock held 157 *--------------------------------------------------------------*/ 158static void nuke(struct fsl_ep *ep, int status) 159{ 160 ep->stopped = 1; 161 162 /* Flush fifo */ 163 fsl_ep_fifo_flush(&ep->ep); 164 165 /* Whether this eq has request linked */ 166 while (!list_empty(&ep->queue)) { 167 struct fsl_req *req = NULL; 168 169 req = list_entry(ep->queue.next, struct fsl_req, queue); 170 done(ep, req, status); 171 } 172} 173 174/*------------------------------------------------------------------ 175 Internal Hardware related function 176 ------------------------------------------------------------------*/ 177 178static int dr_controller_setup(struct fsl_udc *udc) 179{ 180 unsigned int tmp, portctrl; 181#ifndef CONFIG_ARCH_MXC 182 unsigned int ctrl; 183#endif 184 unsigned long timeout; 185#define FSL_UDC_RESET_TIMEOUT 1000 186 187 /* Config PHY interface */ 188 portctrl = fsl_readl(&dr_regs->portsc1); 189 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); 190 switch (udc->phy_mode) { 191 case FSL_USB2_PHY_ULPI: 192 portctrl |= PORTSCX_PTS_ULPI; 193 break; 194 case FSL_USB2_PHY_UTMI_WIDE: 195 portctrl |= PORTSCX_PTW_16BIT; 196 /* fall through */ 197 case FSL_USB2_PHY_UTMI: 198 portctrl |= PORTSCX_PTS_UTMI; 199 break; 200 case FSL_USB2_PHY_SERIAL: 201 portctrl |= PORTSCX_PTS_FSLS; 202 break; 203 default: 204 return -EINVAL; 205 } 206 fsl_writel(portctrl, &dr_regs->portsc1); 207 208 /* Stop and reset the usb controller */ 209 tmp = fsl_readl(&dr_regs->usbcmd); 210 tmp &= ~USB_CMD_RUN_STOP; 211 fsl_writel(tmp, &dr_regs->usbcmd); 212 213 tmp = fsl_readl(&dr_regs->usbcmd); 214 tmp |= USB_CMD_CTRL_RESET; 215 fsl_writel(tmp, &dr_regs->usbcmd); 216 217 /* Wait for reset to complete */ 218 timeout = jiffies + FSL_UDC_RESET_TIMEOUT; 219 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { 220 if (time_after(jiffies, timeout)) { 221 ERR("udc reset timeout!\n"); 222 return -ETIMEDOUT; 223 } 224 cpu_relax(); 225 } 226 227 /* Set the controller as device mode */ 228 tmp = fsl_readl(&dr_regs->usbmode); 229 tmp |= USB_MODE_CTRL_MODE_DEVICE; 230 /* Disable Setup Lockout */ 231 tmp |= USB_MODE_SETUP_LOCK_OFF; 232 fsl_writel(tmp, &dr_regs->usbmode); 233 234 /* Clear the setup status */ 235 fsl_writel(0, &dr_regs->usbsts); 236 237 tmp = udc->ep_qh_dma; 238 tmp &= USB_EP_LIST_ADDRESS_MASK; 239 fsl_writel(tmp, &dr_regs->endpointlistaddr); 240 241 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x", 242 udc->ep_qh, (int)tmp, 243 fsl_readl(&dr_regs->endpointlistaddr)); 244 245 /* Config control enable i/o output, cpu endian register */ 246#ifndef CONFIG_ARCH_MXC 247 ctrl = __raw_readl(&usb_sys_regs->control); 248 ctrl |= USB_CTRL_IOENB; 249 __raw_writel(ctrl, &usb_sys_regs->control); 250#endif 251 252#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 253 /* Turn on cache snooping hardware, since some PowerPC platforms 254 * wholly rely on hardware to deal with cache coherent. */ 255 256 /* Setup Snooping for all the 4GB space */ 257 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ 258 __raw_writel(tmp, &usb_sys_regs->snoop1); 259 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ 260 __raw_writel(tmp, &usb_sys_regs->snoop2); 261#endif 262 263 return 0; 264} 265 266/* Enable DR irq and set controller to run state */ 267static void dr_controller_run(struct fsl_udc *udc) 268{ 269 u32 temp; 270 271 /* Enable DR irq reg */ 272 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN 273 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN 274 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN; 275 276 fsl_writel(temp, &dr_regs->usbintr); 277 278 /* Clear stopped bit */ 279 udc->stopped = 0; 280 281 /* Set the controller as device mode */ 282 temp = fsl_readl(&dr_regs->usbmode); 283 temp |= USB_MODE_CTRL_MODE_DEVICE; 284 fsl_writel(temp, &dr_regs->usbmode); 285 286 /* Set controller to Run */ 287 temp = fsl_readl(&dr_regs->usbcmd); 288 temp |= USB_CMD_RUN_STOP; 289 fsl_writel(temp, &dr_regs->usbcmd); 290} 291 292static void dr_controller_stop(struct fsl_udc *udc) 293{ 294 unsigned int tmp; 295 296 /* disable all INTR */ 297 fsl_writel(0, &dr_regs->usbintr); 298 299 /* Set stopped bit for isr */ 300 udc->stopped = 1; 301 302 /* disable IO output */ 303/* usb_sys_regs->control = 0; */ 304 305 /* set controller to Stop */ 306 tmp = fsl_readl(&dr_regs->usbcmd); 307 tmp &= ~USB_CMD_RUN_STOP; 308 fsl_writel(tmp, &dr_regs->usbcmd); 309} 310 311static void dr_ep_setup(unsigned char ep_num, unsigned char dir, 312 unsigned char ep_type) 313{ 314 unsigned int tmp_epctrl = 0; 315 316 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 317 if (dir) { 318 if (ep_num) 319 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; 320 tmp_epctrl |= EPCTRL_TX_ENABLE; 321 tmp_epctrl |= ((unsigned int)(ep_type) 322 << EPCTRL_TX_EP_TYPE_SHIFT); 323 } else { 324 if (ep_num) 325 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; 326 tmp_epctrl |= EPCTRL_RX_ENABLE; 327 tmp_epctrl |= ((unsigned int)(ep_type) 328 << EPCTRL_RX_EP_TYPE_SHIFT); 329 } 330 331 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); 332} 333 334static void 335dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value) 336{ 337 u32 tmp_epctrl = 0; 338 339 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 340 341 if (value) { 342 /* set the stall bit */ 343 if (dir) 344 tmp_epctrl |= EPCTRL_TX_EP_STALL; 345 else 346 tmp_epctrl |= EPCTRL_RX_EP_STALL; 347 } else { 348 /* clear the stall bit and reset data toggle */ 349 if (dir) { 350 tmp_epctrl &= ~EPCTRL_TX_EP_STALL; 351 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; 352 } else { 353 tmp_epctrl &= ~EPCTRL_RX_EP_STALL; 354 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; 355 } 356 } 357 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); 358} 359 360/* Get stall status of a specific ep 361 Return: 0: not stalled; 1:stalled */ 362static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir) 363{ 364 u32 epctrl; 365 366 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 367 if (dir) 368 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0; 369 else 370 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0; 371} 372 373/******************************************************************** 374 Internal Structure Build up functions 375********************************************************************/ 376 377/*------------------------------------------------------------------ 378* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH 379 * @zlt: Zero Length Termination Select (1: disable; 0: enable) 380 * @mult: Mult field 381 ------------------------------------------------------------------*/ 382static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num, 383 unsigned char dir, unsigned char ep_type, 384 unsigned int max_pkt_len, 385 unsigned int zlt, unsigned char mult) 386{ 387 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir]; 388 unsigned int tmp = 0; 389 390 /* set the Endpoint Capabilites in QH */ 391 switch (ep_type) { 392 case USB_ENDPOINT_XFER_CONTROL: 393 /* Interrupt On Setup (IOS). for control ep */ 394 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) 395 | EP_QUEUE_HEAD_IOS; 396 break; 397 case USB_ENDPOINT_XFER_ISOC: 398 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) 399 | (mult << EP_QUEUE_HEAD_MULT_POS); 400 break; 401 case USB_ENDPOINT_XFER_BULK: 402 case USB_ENDPOINT_XFER_INT: 403 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS; 404 break; 405 default: 406 VDBG("error ep type is %d", ep_type); 407 return; 408 } 409 if (zlt) 410 tmp |= EP_QUEUE_HEAD_ZLT_SEL; 411 412 p_QH->max_pkt_length = cpu_to_le32(tmp); 413 p_QH->next_dtd_ptr = 1; 414 p_QH->size_ioc_int_sts = 0; 415} 416 417/* Setup qh structure and ep register for ep0. */ 418static void ep0_setup(struct fsl_udc *udc) 419{ 420 /* the intialization of an ep includes: fields in QH, Regs, 421 * fsl_ep struct */ 422 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, 423 USB_MAX_CTRL_PAYLOAD, 0, 0); 424 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, 425 USB_MAX_CTRL_PAYLOAD, 0, 0); 426 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); 427 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); 428 429 return; 430 431} 432 433/*********************************************************************** 434 Endpoint Management Functions 435***********************************************************************/ 436 437/*------------------------------------------------------------------------- 438 * when configurations are set, or when interface settings change 439 * for example the do_set_interface() in gadget layer, 440 * the driver will enable or disable the relevant endpoints 441 * ep0 doesn't use this routine. It is always enabled. 442-------------------------------------------------------------------------*/ 443static int fsl_ep_enable(struct usb_ep *_ep, 444 const struct usb_endpoint_descriptor *desc) 445{ 446 struct fsl_udc *udc = NULL; 447 struct fsl_ep *ep = NULL; 448 unsigned short max = 0; 449 unsigned char mult = 0, zlt; 450 int retval = -EINVAL; 451 unsigned long flags = 0; 452 453 ep = container_of(_ep, struct fsl_ep, ep); 454 455 /* catch various bogus parameters */ 456 if (!_ep || !desc || ep->desc 457 || (desc->bDescriptorType != USB_DT_ENDPOINT)) 458 return -EINVAL; 459 460 udc = ep->udc; 461 462 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) 463 return -ESHUTDOWN; 464 465 max = le16_to_cpu(desc->wMaxPacketSize); 466 467 /* Disable automatic zlp generation. Driver is reponsible to indicate 468 * explicitly through req->req.zero. This is needed to enable multi-td 469 * request. */ 470 zlt = 1; 471 472 /* Assume the max packet size from gadget is always correct */ 473 switch (desc->bmAttributes & 0x03) { 474 case USB_ENDPOINT_XFER_CONTROL: 475 case USB_ENDPOINT_XFER_BULK: 476 case USB_ENDPOINT_XFER_INT: 477 /* mult = 0. Execute N Transactions as demonstrated by 478 * the USB variable length packet protocol where N is 479 * computed using the Maximum Packet Length (dQH) and 480 * the Total Bytes field (dTD) */ 481 mult = 0; 482 break; 483 case USB_ENDPOINT_XFER_ISOC: 484 /* Calculate transactions needed for high bandwidth iso */ 485 mult = (unsigned char)(1 + ((max >> 11) & 0x03)); 486 max = max & 0x7ff; /* bit 0~10 */ 487 /* 3 transactions at most */ 488 if (mult > 3) 489 goto en_done; 490 break; 491 default: 492 goto en_done; 493 } 494 495 spin_lock_irqsave(&udc->lock, flags); 496 ep->ep.maxpacket = max; 497 ep->desc = desc; 498 ep->stopped = 0; 499 500 /* Controller related setup */ 501 /* Init EPx Queue Head (Ep Capabilites field in QH 502 * according to max, zlt, mult) */ 503 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep), 504 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) 505 ? USB_SEND : USB_RECV), 506 (unsigned char) (desc->bmAttributes 507 & USB_ENDPOINT_XFERTYPE_MASK), 508 max, zlt, mult); 509 510 /* Init endpoint ctrl register */ 511 dr_ep_setup((unsigned char) ep_index(ep), 512 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) 513 ? USB_SEND : USB_RECV), 514 (unsigned char) (desc->bmAttributes 515 & USB_ENDPOINT_XFERTYPE_MASK)); 516 517 spin_unlock_irqrestore(&udc->lock, flags); 518 retval = 0; 519 520 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name, 521 ep->desc->bEndpointAddress & 0x0f, 522 (desc->bEndpointAddress & USB_DIR_IN) 523 ? "in" : "out", max); 524en_done: 525 return retval; 526} 527 528/*--------------------------------------------------------------------- 529 * @ep : the ep being unconfigured. May not be ep0 530 * Any pending and uncomplete req will complete with status (-ESHUTDOWN) 531*---------------------------------------------------------------------*/ 532static int fsl_ep_disable(struct usb_ep *_ep) 533{ 534 struct fsl_udc *udc = NULL; 535 struct fsl_ep *ep = NULL; 536 unsigned long flags = 0; 537 u32 epctrl; 538 int ep_num; 539 540 ep = container_of(_ep, struct fsl_ep, ep); 541 if (!_ep || !ep->desc) { 542 VDBG("%s not enabled", _ep ? ep->ep.name : NULL); 543 return -EINVAL; 544 } 545 546 /* disable ep on controller */ 547 ep_num = ep_index(ep); 548 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 549 if (ep_is_in(ep)) 550 epctrl &= ~EPCTRL_TX_ENABLE; 551 else 552 epctrl &= ~EPCTRL_RX_ENABLE; 553 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 554 555 udc = (struct fsl_udc *)ep->udc; 556 spin_lock_irqsave(&udc->lock, flags); 557 558 /* nuke all pending requests (does flush) */ 559 nuke(ep, -ESHUTDOWN); 560 561 ep->desc = NULL; 562 ep->stopped = 1; 563 spin_unlock_irqrestore(&udc->lock, flags); 564 565 VDBG("disabled %s OK", _ep->name); 566 return 0; 567} 568 569/*--------------------------------------------------------------------- 570 * allocate a request object used by this endpoint 571 * the main operation is to insert the req->queue to the eq->queue 572 * Returns the request, or null if one could not be allocated 573*---------------------------------------------------------------------*/ 574static struct usb_request * 575fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 576{ 577 struct fsl_req *req = NULL; 578 579 req = kzalloc(sizeof *req, gfp_flags); 580 if (!req) 581 return NULL; 582 583 req->req.dma = DMA_ADDR_INVALID; 584 INIT_LIST_HEAD(&req->queue); 585 586 return &req->req; 587} 588 589static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req) 590{ 591 struct fsl_req *req = NULL; 592 593 req = container_of(_req, struct fsl_req, req); 594 595 if (_req) 596 kfree(req); 597} 598 599/*-------------------------------------------------------------------------*/ 600static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) 601{ 602 int i = ep_index(ep) * 2 + ep_is_in(ep); 603 u32 temp, bitmask, tmp_stat; 604 struct ep_queue_head *dQH = &ep->udc->ep_qh[i]; 605 606 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); 607 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ 608 609 bitmask = ep_is_in(ep) 610 ? (1 << (ep_index(ep) + 16)) 611 : (1 << (ep_index(ep))); 612 613 /* check if the pipe is empty */ 614 if (!(list_empty(&ep->queue))) { 615 /* Add td to the end */ 616 struct fsl_req *lastreq; 617 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); 618 lastreq->tail->next_td_ptr = 619 cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK); 620 /* Read prime bit, if 1 goto done */ 621 if (fsl_readl(&dr_regs->endpointprime) & bitmask) 622 goto out; 623 624 do { 625 /* Set ATDTW bit in USBCMD */ 626 temp = fsl_readl(&dr_regs->usbcmd); 627 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd); 628 629 /* Read correct status bit */ 630 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask; 631 632 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW)); 633 634 /* Write ATDTW bit to 0 */ 635 temp = fsl_readl(&dr_regs->usbcmd); 636 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); 637 638 if (tmp_stat) 639 goto out; 640 } 641 642 /* Write dQH next pointer and terminate bit to 0 */ 643 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; 644 dQH->next_dtd_ptr = cpu_to_le32(temp); 645 646 /* Clear active and halt bit */ 647 temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE 648 | EP_QUEUE_HEAD_STATUS_HALT)); 649 dQH->size_ioc_int_sts &= temp; 650 651 /* Ensure that updates to the QH will occure before priming. */ 652 wmb(); 653 654 /* Prime endpoint by writing 1 to ENDPTPRIME */ 655 temp = ep_is_in(ep) 656 ? (1 << (ep_index(ep) + 16)) 657 : (1 << (ep_index(ep))); 658 fsl_writel(temp, &dr_regs->endpointprime); 659out: 660 return; 661} 662 663/* Fill in the dTD structure 664 * @req: request that the transfer belongs to 665 * @length: return actually data length of the dTD 666 * @dma: return dma address of the dTD 667 * @is_last: return flag if it is the last dTD of the request 668 * return: pointer to the built dTD */ 669static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length, 670 dma_addr_t *dma, int *is_last) 671{ 672 u32 swap_temp; 673 struct ep_td_struct *dtd; 674 675 /* how big will this transfer be? */ 676 *length = min(req->req.length - req->req.actual, 677 (unsigned)EP_MAX_LENGTH_TRANSFER); 678 679 dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma); 680 if (dtd == NULL) 681 return dtd; 682 683 dtd->td_dma = *dma; 684 /* Clear reserved field */ 685 swap_temp = cpu_to_le32(dtd->size_ioc_sts); 686 swap_temp &= ~DTD_RESERVED_FIELDS; 687 dtd->size_ioc_sts = cpu_to_le32(swap_temp); 688 689 /* Init all of buffer page pointers */ 690 swap_temp = (u32) (req->req.dma + req->req.actual); 691 dtd->buff_ptr0 = cpu_to_le32(swap_temp); 692 dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000); 693 dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000); 694 dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000); 695 dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000); 696 697 req->req.actual += *length; 698 699 /* zlp is needed if req->req.zero is set */ 700 if (req->req.zero) { 701 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) 702 *is_last = 1; 703 else 704 *is_last = 0; 705 } else if (req->req.length == req->req.actual) 706 *is_last = 1; 707 else 708 *is_last = 0; 709 710 if ((*is_last) == 0) 711 VDBG("multi-dtd request!"); 712 /* Fill in the transfer size; set active bit */ 713 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); 714 715 /* Enable interrupt for the last dtd of a request */ 716 if (*is_last && !req->req.no_interrupt) 717 swap_temp |= DTD_IOC; 718 719 dtd->size_ioc_sts = cpu_to_le32(swap_temp); 720 721 mb(); 722 723 VDBG("length = %d address= 0x%x", *length, (int)*dma); 724 725 return dtd; 726} 727 728/* Generate dtd chain for a request */ 729static int fsl_req_to_dtd(struct fsl_req *req) 730{ 731 unsigned count; 732 int is_last; 733 int is_first =1; 734 struct ep_td_struct *last_dtd = NULL, *dtd; 735 dma_addr_t dma; 736 737 do { 738 dtd = fsl_build_dtd(req, &count, &dma, &is_last); 739 if (dtd == NULL) 740 return -ENOMEM; 741 742 if (is_first) { 743 is_first = 0; 744 req->head = dtd; 745 } else { 746 last_dtd->next_td_ptr = cpu_to_le32(dma); 747 last_dtd->next_td_virt = dtd; 748 } 749 last_dtd = dtd; 750 751 req->dtd_count++; 752 } while (!is_last); 753 754 dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE); 755 756 req->tail = dtd; 757 758 return 0; 759} 760 761/* queues (submits) an I/O request to an endpoint */ 762static int 763fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 764{ 765 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); 766 struct fsl_req *req = container_of(_req, struct fsl_req, req); 767 struct fsl_udc *udc; 768 unsigned long flags; 769 770 /* catch various bogus parameters */ 771 if (!_req || !req->req.complete || !req->req.buf 772 || !list_empty(&req->queue)) { 773 VDBG("%s, bad params", __func__); 774 return -EINVAL; 775 } 776 if (unlikely(!_ep || !ep->desc)) { 777 VDBG("%s, bad ep", __func__); 778 return -EINVAL; 779 } 780 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 781 if (req->req.length > ep->ep.maxpacket) 782 return -EMSGSIZE; 783 } 784 785 udc = ep->udc; 786 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 787 return -ESHUTDOWN; 788 789 req->ep = ep; 790 791 /* map virtual address to hardware */ 792 if (req->req.dma == DMA_ADDR_INVALID) { 793 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, 794 req->req.buf, 795 req->req.length, ep_is_in(ep) 796 ? DMA_TO_DEVICE 797 : DMA_FROM_DEVICE); 798 req->mapped = 1; 799 } else { 800 dma_sync_single_for_device(ep->udc->gadget.dev.parent, 801 req->req.dma, req->req.length, 802 ep_is_in(ep) 803 ? DMA_TO_DEVICE 804 : DMA_FROM_DEVICE); 805 req->mapped = 0; 806 } 807 808 req->req.status = -EINPROGRESS; 809 req->req.actual = 0; 810 req->dtd_count = 0; 811 812 spin_lock_irqsave(&udc->lock, flags); 813 814 /* build dtds and push them to device queue */ 815 if (!fsl_req_to_dtd(req)) { 816 fsl_queue_td(ep, req); 817 } else { 818 spin_unlock_irqrestore(&udc->lock, flags); 819 return -ENOMEM; 820 } 821 822 /* Update ep0 state */ 823 if ((ep_index(ep) == 0)) 824 udc->ep0_state = DATA_STATE_XMIT; 825 826 /* irq handler advances the queue */ 827 if (req != NULL) 828 list_add_tail(&req->queue, &ep->queue); 829 spin_unlock_irqrestore(&udc->lock, flags); 830 831 return 0; 832} 833 834/* dequeues (cancels, unlinks) an I/O request from an endpoint */ 835static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 836{ 837 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); 838 struct fsl_req *req; 839 unsigned long flags; 840 int ep_num, stopped, ret = 0; 841 u32 epctrl; 842 843 if (!_ep || !_req) 844 return -EINVAL; 845 846 spin_lock_irqsave(&ep->udc->lock, flags); 847 stopped = ep->stopped; 848 849 /* Stop the ep before we deal with the queue */ 850 ep->stopped = 1; 851 ep_num = ep_index(ep); 852 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 853 if (ep_is_in(ep)) 854 epctrl &= ~EPCTRL_TX_ENABLE; 855 else 856 epctrl &= ~EPCTRL_RX_ENABLE; 857 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 858 859 /* make sure it's actually queued on this endpoint */ 860 list_for_each_entry(req, &ep->queue, queue) { 861 if (&req->req == _req) 862 break; 863 } 864 if (&req->req != _req) { 865 ret = -EINVAL; 866 goto out; 867 } 868 869 /* The request is in progress, or completed but not dequeued */ 870 if (ep->queue.next == &req->queue) { 871 _req->status = -ECONNRESET; 872 fsl_ep_fifo_flush(_ep); /* flush current transfer */ 873 874 /* The request isn't the last request in this ep queue */ 875 if (req->queue.next != &ep->queue) { 876 struct ep_queue_head *qh; 877 struct fsl_req *next_req; 878 879 qh = ep->qh; 880 next_req = list_entry(req->queue.next, struct fsl_req, 881 queue); 882 883 /* Point the QH to the first TD of next request */ 884 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr); 885 } 886 887 /* The request hasn't been processed, patch up the TD chain */ 888 } else { 889 struct fsl_req *prev_req; 890 891 prev_req = list_entry(req->queue.prev, struct fsl_req, queue); 892 fsl_writel(fsl_readl(&req->tail->next_td_ptr), 893 &prev_req->tail->next_td_ptr); 894 895 } 896 897 done(ep, req, -ECONNRESET); 898 899 /* Enable EP */ 900out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 901 if (ep_is_in(ep)) 902 epctrl |= EPCTRL_TX_ENABLE; 903 else 904 epctrl |= EPCTRL_RX_ENABLE; 905 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 906 ep->stopped = stopped; 907 908 spin_unlock_irqrestore(&ep->udc->lock, flags); 909 return ret; 910} 911 912/*-------------------------------------------------------------------------*/ 913 914/*----------------------------------------------------------------- 915 * modify the endpoint halt feature 916 * @ep: the non-isochronous endpoint being stalled 917 * @value: 1--set halt 0--clear halt 918 * Returns zero, or a negative error code. 919*----------------------------------------------------------------*/ 920static int fsl_ep_set_halt(struct usb_ep *_ep, int value) 921{ 922 struct fsl_ep *ep = NULL; 923 unsigned long flags = 0; 924 int status = -EOPNOTSUPP; /* operation not supported */ 925 unsigned char ep_dir = 0, ep_num = 0; 926 struct fsl_udc *udc = NULL; 927 928 ep = container_of(_ep, struct fsl_ep, ep); 929 udc = ep->udc; 930 if (!_ep || !ep->desc) { 931 status = -EINVAL; 932 goto out; 933 } 934 935 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 936 status = -EOPNOTSUPP; 937 goto out; 938 } 939 940 /* Attempt to halt IN ep will fail if any transfer requests 941 * are still queue */ 942 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { 943 status = -EAGAIN; 944 goto out; 945 } 946 947 status = 0; 948 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; 949 ep_num = (unsigned char)(ep_index(ep)); 950 spin_lock_irqsave(&ep->udc->lock, flags); 951 dr_ep_change_stall(ep_num, ep_dir, value); 952 spin_unlock_irqrestore(&ep->udc->lock, flags); 953 954 if (ep_index(ep) == 0) { 955 udc->ep0_state = WAIT_FOR_SETUP; 956 udc->ep0_dir = 0; 957 } 958out: 959 VDBG(" %s %s halt stat %d", ep->ep.name, 960 value ? "set" : "clear", status); 961 962 return status; 963} 964 965static void fsl_ep_fifo_flush(struct usb_ep *_ep) 966{ 967 struct fsl_ep *ep; 968 int ep_num, ep_dir; 969 u32 bits; 970 unsigned long timeout; 971#define FSL_UDC_FLUSH_TIMEOUT 1000 972 973 if (!_ep) { 974 return; 975 } else { 976 ep = container_of(_ep, struct fsl_ep, ep); 977 if (!ep->desc) 978 return; 979 } 980 ep_num = ep_index(ep); 981 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; 982 983 if (ep_num == 0) 984 bits = (1 << 16) | 1; 985 else if (ep_dir == USB_SEND) 986 bits = 1 << (16 + ep_num); 987 else 988 bits = 1 << ep_num; 989 990 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT; 991 do { 992 fsl_writel(bits, &dr_regs->endptflush); 993 994 /* Wait until flush complete */ 995 while (fsl_readl(&dr_regs->endptflush)) { 996 if (time_after(jiffies, timeout)) { 997 ERR("ep flush timeout\n"); 998 return; 999 } 1000 cpu_relax(); 1001 } 1002 /* See if we need to flush again */ 1003 } while (fsl_readl(&dr_regs->endptstatus) & bits); 1004} 1005 1006static struct usb_ep_ops fsl_ep_ops = { 1007 .enable = fsl_ep_enable, 1008 .disable = fsl_ep_disable, 1009 1010 .alloc_request = fsl_alloc_request, 1011 .free_request = fsl_free_request, 1012 1013 .queue = fsl_ep_queue, 1014 .dequeue = fsl_ep_dequeue, 1015 1016 .set_halt = fsl_ep_set_halt, 1017 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ 1018}; 1019 1020/*------------------------------------------------------------------------- 1021 Gadget Driver Layer Operations 1022-------------------------------------------------------------------------*/ 1023 1024/*---------------------------------------------------------------------- 1025 * Get the current frame number (from DR frame_index Reg ) 1026 *----------------------------------------------------------------------*/ 1027static int fsl_get_frame(struct usb_gadget *gadget) 1028{ 1029 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS); 1030} 1031 1032/*----------------------------------------------------------------------- 1033 * Tries to wake up the host connected to this gadget 1034 -----------------------------------------------------------------------*/ 1035static int fsl_wakeup(struct usb_gadget *gadget) 1036{ 1037 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); 1038 u32 portsc; 1039 1040 /* Remote wakeup feature not enabled by host */ 1041 if (!udc->remote_wakeup) 1042 return -ENOTSUPP; 1043 1044 portsc = fsl_readl(&dr_regs->portsc1); 1045 /* not suspended? */ 1046 if (!(portsc & PORTSCX_PORT_SUSPEND)) 1047 return 0; 1048 /* trigger force resume */ 1049 portsc |= PORTSCX_PORT_FORCE_RESUME; 1050 fsl_writel(portsc, &dr_regs->portsc1); 1051 return 0; 1052} 1053 1054static int can_pullup(struct fsl_udc *udc) 1055{ 1056 return udc->driver && udc->softconnect && udc->vbus_active; 1057} 1058 1059/* Notify controller that VBUS is powered, Called by whatever 1060 detects VBUS sessions */ 1061static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) 1062{ 1063 struct fsl_udc *udc; 1064 unsigned long flags; 1065 1066 udc = container_of(gadget, struct fsl_udc, gadget); 1067 spin_lock_irqsave(&udc->lock, flags); 1068 VDBG("VBUS %s", is_active ? "on" : "off"); 1069 udc->vbus_active = (is_active != 0); 1070 if (can_pullup(udc)) 1071 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), 1072 &dr_regs->usbcmd); 1073 else 1074 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), 1075 &dr_regs->usbcmd); 1076 spin_unlock_irqrestore(&udc->lock, flags); 1077 return 0; 1078} 1079 1080/* constrain controller's VBUS power usage 1081 * This call is used by gadget drivers during SET_CONFIGURATION calls, 1082 * reporting how much power the device may consume. For example, this 1083 * could affect how quickly batteries are recharged. 1084 * 1085 * Returns zero on success, else negative errno. 1086 */ 1087static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1088{ 1089 struct fsl_udc *udc; 1090 1091 udc = container_of(gadget, struct fsl_udc, gadget); 1092 if (udc->transceiver) 1093 return otg_set_power(udc->transceiver, mA); 1094 return -ENOTSUPP; 1095} 1096 1097/* Change Data+ pullup status 1098 * this func is used by usb_gadget_connect/disconnet 1099 */ 1100static int fsl_pullup(struct usb_gadget *gadget, int is_on) 1101{ 1102 struct fsl_udc *udc; 1103 1104 udc = container_of(gadget, struct fsl_udc, gadget); 1105 udc->softconnect = (is_on != 0); 1106 if (can_pullup(udc)) 1107 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), 1108 &dr_regs->usbcmd); 1109 else 1110 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), 1111 &dr_regs->usbcmd); 1112 1113 return 0; 1114} 1115 1116/* defined in gadget.h */ 1117static struct usb_gadget_ops fsl_gadget_ops = { 1118 .get_frame = fsl_get_frame, 1119 .wakeup = fsl_wakeup, 1120/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ 1121 .vbus_session = fsl_vbus_session, 1122 .vbus_draw = fsl_vbus_draw, 1123 .pullup = fsl_pullup, 1124}; 1125 1126/* Set protocol stall on ep0, protocol stall will automatically be cleared 1127 on new transaction */ 1128static void ep0stall(struct fsl_udc *udc) 1129{ 1130 u32 tmp; 1131 1132 /* must set tx and rx to stall at the same time */ 1133 tmp = fsl_readl(&dr_regs->endptctrl[0]); 1134 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL; 1135 fsl_writel(tmp, &dr_regs->endptctrl[0]); 1136 udc->ep0_state = WAIT_FOR_SETUP; 1137 udc->ep0_dir = 0; 1138} 1139 1140/* Prime a status phase for ep0 */ 1141static int ep0_prime_status(struct fsl_udc *udc, int direction) 1142{ 1143 struct fsl_req *req = udc->status_req; 1144 struct fsl_ep *ep; 1145 1146 if (direction == EP_DIR_IN) 1147 udc->ep0_dir = USB_DIR_IN; 1148 else 1149 udc->ep0_dir = USB_DIR_OUT; 1150 1151 ep = &udc->eps[0]; 1152 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1153 1154 req->ep = ep; 1155 req->req.length = 0; 1156 req->req.status = -EINPROGRESS; 1157 req->req.actual = 0; 1158 req->req.complete = NULL; 1159 req->dtd_count = 0; 1160 1161 if (fsl_req_to_dtd(req) == 0) 1162 fsl_queue_td(ep, req); 1163 else 1164 return -ENOMEM; 1165 1166 list_add_tail(&req->queue, &ep->queue); 1167 1168 return 0; 1169} 1170 1171static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe) 1172{ 1173 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe); 1174 1175 if (ep->name) 1176 nuke(ep, -ESHUTDOWN); 1177} 1178 1179/* 1180 * ch9 Set address 1181 */ 1182static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length) 1183{ 1184 /* Save the new address to device struct */ 1185 udc->device_address = (u8) value; 1186 /* Update usb state */ 1187 udc->usb_state = USB_STATE_ADDRESS; 1188 /* Status phase */ 1189 if (ep0_prime_status(udc, EP_DIR_IN)) 1190 ep0stall(udc); 1191} 1192 1193/* 1194 * ch9 Get status 1195 */ 1196static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, 1197 u16 index, u16 length) 1198{ 1199 u16 tmp = 0; /* Status, cpu endian */ 1200 struct fsl_req *req; 1201 struct fsl_ep *ep; 1202 1203 ep = &udc->eps[0]; 1204 1205 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { 1206 /* Get device status */ 1207 tmp = 1 << USB_DEVICE_SELF_POWERED; 1208 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; 1209 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { 1210 /* Get interface status */ 1211 /* We don't have interface information in udc driver */ 1212 tmp = 0; 1213 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { 1214 /* Get endpoint status */ 1215 struct fsl_ep *target_ep; 1216 1217 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); 1218 1219 /* stall if endpoint doesn't exist */ 1220 if (!target_ep->desc) 1221 goto stall; 1222 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) 1223 << USB_ENDPOINT_HALT; 1224 } 1225 1226 udc->ep0_dir = USB_DIR_IN; 1227 /* Borrow the per device status_req */ 1228 req = udc->status_req; 1229 /* Fill in the reqest structure */ 1230 *((u16 *) req->req.buf) = cpu_to_le16(tmp); 1231 req->ep = ep; 1232 req->req.length = 2; 1233 req->req.status = -EINPROGRESS; 1234 req->req.actual = 0; 1235 req->req.complete = NULL; 1236 req->dtd_count = 0; 1237 1238 /* prime the data phase */ 1239 if ((fsl_req_to_dtd(req) == 0)) 1240 fsl_queue_td(ep, req); 1241 else /* no mem */ 1242 goto stall; 1243 1244 list_add_tail(&req->queue, &ep->queue); 1245 udc->ep0_state = DATA_STATE_XMIT; 1246 return; 1247stall: 1248 ep0stall(udc); 1249} 1250 1251static void setup_received_irq(struct fsl_udc *udc, 1252 struct usb_ctrlrequest *setup) 1253{ 1254 u16 wValue = le16_to_cpu(setup->wValue); 1255 u16 wIndex = le16_to_cpu(setup->wIndex); 1256 u16 wLength = le16_to_cpu(setup->wLength); 1257 1258 udc_reset_ep_queue(udc, 0); 1259 1260 /* We process some stardard setup requests here */ 1261 switch (setup->bRequest) { 1262 case USB_REQ_GET_STATUS: 1263 /* Data+Status phase from udc */ 1264 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) 1265 != (USB_DIR_IN | USB_TYPE_STANDARD)) 1266 break; 1267 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength); 1268 return; 1269 1270 case USB_REQ_SET_ADDRESS: 1271 /* Status phase from udc */ 1272 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD 1273 | USB_RECIP_DEVICE)) 1274 break; 1275 ch9setaddress(udc, wValue, wIndex, wLength); 1276 return; 1277 1278 case USB_REQ_CLEAR_FEATURE: 1279 case USB_REQ_SET_FEATURE: 1280 /* Status phase from udc */ 1281 { 1282 int rc = -EOPNOTSUPP; 1283 1284 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) 1285 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { 1286 int pipe = get_pipe_by_windex(wIndex); 1287 struct fsl_ep *ep; 1288 1289 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep) 1290 break; 1291 ep = get_ep_by_pipe(udc, pipe); 1292 1293 spin_unlock(&udc->lock); 1294 rc = fsl_ep_set_halt(&ep->ep, 1295 (setup->bRequest == USB_REQ_SET_FEATURE) 1296 ? 1 : 0); 1297 spin_lock(&udc->lock); 1298 1299 } else if ((setup->bRequestType & (USB_RECIP_MASK 1300 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE 1301 | USB_TYPE_STANDARD)) { 1302 /* Note: The driver has not include OTG support yet. 1303 * This will be set when OTG support is added */ 1304 if (!gadget_is_otg(&udc->gadget)) 1305 break; 1306 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) 1307 udc->gadget.b_hnp_enable = 1; 1308 else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT) 1309 udc->gadget.a_hnp_support = 1; 1310 else if (setup->bRequest == 1311 USB_DEVICE_A_ALT_HNP_SUPPORT) 1312 udc->gadget.a_alt_hnp_support = 1; 1313 else 1314 break; 1315 rc = 0; 1316 } else 1317 break; 1318 1319 if (rc == 0) { 1320 if (ep0_prime_status(udc, EP_DIR_IN)) 1321 ep0stall(udc); 1322 } 1323 return; 1324 } 1325 1326 default: 1327 break; 1328 } 1329 1330 /* Requests handled by gadget */ 1331 if (wLength) { 1332 /* Data phase from gadget, status phase from udc */ 1333 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) 1334 ? USB_DIR_IN : USB_DIR_OUT; 1335 spin_unlock(&udc->lock); 1336 if (udc->driver->setup(&udc->gadget, 1337 &udc->local_setup_buff) < 0) 1338 ep0stall(udc); 1339 spin_lock(&udc->lock); 1340 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) 1341 ? DATA_STATE_XMIT : DATA_STATE_RECV; 1342 } else { 1343 /* No data phase, IN status from gadget */ 1344 udc->ep0_dir = USB_DIR_IN; 1345 spin_unlock(&udc->lock); 1346 if (udc->driver->setup(&udc->gadget, 1347 &udc->local_setup_buff) < 0) 1348 ep0stall(udc); 1349 spin_lock(&udc->lock); 1350 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1351 } 1352} 1353 1354/* Process request for Data or Status phase of ep0 1355 * prime status phase if needed */ 1356static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, 1357 struct fsl_req *req) 1358{ 1359 if (udc->usb_state == USB_STATE_ADDRESS) { 1360 /* Set the new address */ 1361 u32 new_address = (u32) udc->device_address; 1362 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS, 1363 &dr_regs->deviceaddr); 1364 } 1365 1366 done(ep0, req, 0); 1367 1368 switch (udc->ep0_state) { 1369 case DATA_STATE_XMIT: 1370 /* receive status phase */ 1371 if (ep0_prime_status(udc, EP_DIR_OUT)) 1372 ep0stall(udc); 1373 break; 1374 case DATA_STATE_RECV: 1375 /* send status phase */ 1376 if (ep0_prime_status(udc, EP_DIR_IN)) 1377 ep0stall(udc); 1378 break; 1379 case WAIT_FOR_OUT_STATUS: 1380 udc->ep0_state = WAIT_FOR_SETUP; 1381 break; 1382 case WAIT_FOR_SETUP: 1383 ERR("Unexpect ep0 packets\n"); 1384 break; 1385 default: 1386 ep0stall(udc); 1387 break; 1388 } 1389} 1390 1391/* Tripwire mechanism to ensure a setup packet payload is extracted without 1392 * being corrupted by another incoming setup packet */ 1393static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr) 1394{ 1395 u32 temp; 1396 struct ep_queue_head *qh; 1397 1398 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; 1399 1400 /* Clear bit in ENDPTSETUPSTAT */ 1401 temp = fsl_readl(&dr_regs->endptsetupstat); 1402 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat); 1403 1404 /* while a hazard exists when setup package arrives */ 1405 do { 1406 /* Set Setup Tripwire */ 1407 temp = fsl_readl(&dr_regs->usbcmd); 1408 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); 1409 1410 /* Copy the setup packet to local buffer */ 1411 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); 1412 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); 1413 1414 /* Clear Setup Tripwire */ 1415 temp = fsl_readl(&dr_regs->usbcmd); 1416 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd); 1417} 1418 1419/* process-ep_req(): free the completed Tds for this req */ 1420static int process_ep_req(struct fsl_udc *udc, int pipe, 1421 struct fsl_req *curr_req) 1422{ 1423 struct ep_td_struct *curr_td; 1424 int td_complete, actual, remaining_length, j, tmp; 1425 int status = 0; 1426 int errors = 0; 1427 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe]; 1428 int direction = pipe % 2; 1429 1430 curr_td = curr_req->head; 1431 td_complete = 0; 1432 actual = curr_req->req.length; 1433 1434 for (j = 0; j < curr_req->dtd_count; j++) { 1435 remaining_length = (le32_to_cpu(curr_td->size_ioc_sts) 1436 & DTD_PACKET_SIZE) 1437 >> DTD_LENGTH_BIT_POS; 1438 actual -= remaining_length; 1439 1440 if ((errors = le32_to_cpu(curr_td->size_ioc_sts) & 1441 DTD_ERROR_MASK)) { 1442 if (errors & DTD_STATUS_HALTED) { 1443 ERR("dTD error %08x QH=%d\n", errors, pipe); 1444 /* Clear the errors and Halt condition */ 1445 tmp = le32_to_cpu(curr_qh->size_ioc_int_sts); 1446 tmp &= ~errors; 1447 curr_qh->size_ioc_int_sts = cpu_to_le32(tmp); 1448 status = -EPIPE; 1449 /* FIXME: continue with next queued TD? */ 1450 1451 break; 1452 } 1453 if (errors & DTD_STATUS_DATA_BUFF_ERR) { 1454 VDBG("Transfer overflow"); 1455 status = -EPROTO; 1456 break; 1457 } else if (errors & DTD_STATUS_TRANSACTION_ERR) { 1458 VDBG("ISO error"); 1459 status = -EILSEQ; 1460 break; 1461 } else 1462 ERR("Unknown error has occured (0x%x)!\n", 1463 errors); 1464 1465 } else if (le32_to_cpu(curr_td->size_ioc_sts) 1466 & DTD_STATUS_ACTIVE) { 1467 VDBG("Request not complete"); 1468 status = REQ_UNCOMPLETE; 1469 return status; 1470 } else if (remaining_length) { 1471 if (direction) { 1472 VDBG("Transmit dTD remaining length not zero"); 1473 status = -EPROTO; 1474 break; 1475 } else { 1476 td_complete++; 1477 break; 1478 } 1479 } else { 1480 td_complete++; 1481 VDBG("dTD transmitted successful"); 1482 } 1483 1484 if (j != curr_req->dtd_count - 1) 1485 curr_td = (struct ep_td_struct *)curr_td->next_td_virt; 1486 } 1487 1488 if (status) 1489 return status; 1490 1491 curr_req->req.actual = actual; 1492 1493 return 0; 1494} 1495 1496/* Process a DTD completion interrupt */ 1497static void dtd_complete_irq(struct fsl_udc *udc) 1498{ 1499 u32 bit_pos; 1500 int i, ep_num, direction, bit_mask, status; 1501 struct fsl_ep *curr_ep; 1502 struct fsl_req *curr_req, *temp_req; 1503 1504 /* Clear the bits in the register */ 1505 bit_pos = fsl_readl(&dr_regs->endptcomplete); 1506 fsl_writel(bit_pos, &dr_regs->endptcomplete); 1507 1508 if (!bit_pos) 1509 return; 1510 1511 for (i = 0; i < udc->max_ep * 2; i++) { 1512 ep_num = i >> 1; 1513 direction = i % 2; 1514 1515 bit_mask = 1 << (ep_num + 16 * direction); 1516 1517 if (!(bit_pos & bit_mask)) 1518 continue; 1519 1520 curr_ep = get_ep_by_pipe(udc, i); 1521 1522 /* If the ep is configured */ 1523 if (curr_ep->name == NULL) { 1524 WARNING("Invalid EP?"); 1525 continue; 1526 } 1527 1528 /* process the req queue until an uncomplete request */ 1529 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue, 1530 queue) { 1531 status = process_ep_req(udc, i, curr_req); 1532 1533 VDBG("status of process_ep_req= %d, ep = %d", 1534 status, ep_num); 1535 if (status == REQ_UNCOMPLETE) 1536 break; 1537 /* write back status to req */ 1538 curr_req->req.status = status; 1539 1540 if (ep_num == 0) { 1541 ep0_req_complete(udc, curr_ep, curr_req); 1542 break; 1543 } else 1544 done(curr_ep, curr_req, status); 1545 } 1546 } 1547} 1548 1549/* Process a port change interrupt */ 1550static void port_change_irq(struct fsl_udc *udc) 1551{ 1552 u32 speed; 1553 1554 /* Bus resetting is finished */ 1555 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) { 1556 /* Get the speed */ 1557 speed = (fsl_readl(&dr_regs->portsc1) 1558 & PORTSCX_PORT_SPEED_MASK); 1559 switch (speed) { 1560 case PORTSCX_PORT_SPEED_HIGH: 1561 udc->gadget.speed = USB_SPEED_HIGH; 1562 break; 1563 case PORTSCX_PORT_SPEED_FULL: 1564 udc->gadget.speed = USB_SPEED_FULL; 1565 break; 1566 case PORTSCX_PORT_SPEED_LOW: 1567 udc->gadget.speed = USB_SPEED_LOW; 1568 break; 1569 default: 1570 udc->gadget.speed = USB_SPEED_UNKNOWN; 1571 break; 1572 } 1573 } 1574 1575 /* Update USB state */ 1576 if (!udc->resume_state) 1577 udc->usb_state = USB_STATE_DEFAULT; 1578} 1579 1580/* Process suspend interrupt */ 1581static void suspend_irq(struct fsl_udc *udc) 1582{ 1583 udc->resume_state = udc->usb_state; 1584 udc->usb_state = USB_STATE_SUSPENDED; 1585 1586 /* report suspend to the driver, serial.c does not support this */ 1587 if (udc->driver->suspend) 1588 udc->driver->suspend(&udc->gadget); 1589} 1590 1591static void bus_resume(struct fsl_udc *udc) 1592{ 1593 udc->usb_state = udc->resume_state; 1594 udc->resume_state = 0; 1595 1596 /* report resume to the driver, serial.c does not support this */ 1597 if (udc->driver->resume) 1598 udc->driver->resume(&udc->gadget); 1599} 1600 1601/* Clear up all ep queues */ 1602static int reset_queues(struct fsl_udc *udc) 1603{ 1604 u8 pipe; 1605 1606 for (pipe = 0; pipe < udc->max_pipes; pipe++) 1607 udc_reset_ep_queue(udc, pipe); 1608 1609 /* report disconnect; the driver is already quiesced */ 1610 spin_unlock(&udc->lock); 1611 udc->driver->disconnect(&udc->gadget); 1612 spin_lock(&udc->lock); 1613 1614 return 0; 1615} 1616 1617/* Process reset interrupt */ 1618static void reset_irq(struct fsl_udc *udc) 1619{ 1620 u32 temp; 1621 unsigned long timeout; 1622 1623 /* Clear the device address */ 1624 temp = fsl_readl(&dr_regs->deviceaddr); 1625 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr); 1626 1627 udc->device_address = 0; 1628 1629 /* Clear usb state */ 1630 udc->resume_state = 0; 1631 udc->ep0_dir = 0; 1632 udc->ep0_state = WAIT_FOR_SETUP; 1633 udc->remote_wakeup = 0; /* default to 0 on reset */ 1634 udc->gadget.b_hnp_enable = 0; 1635 udc->gadget.a_hnp_support = 0; 1636 udc->gadget.a_alt_hnp_support = 0; 1637 1638 /* Clear all the setup token semaphores */ 1639 temp = fsl_readl(&dr_regs->endptsetupstat); 1640 fsl_writel(temp, &dr_regs->endptsetupstat); 1641 1642 /* Clear all the endpoint complete status bits */ 1643 temp = fsl_readl(&dr_regs->endptcomplete); 1644 fsl_writel(temp, &dr_regs->endptcomplete); 1645 1646 timeout = jiffies + 100; 1647 while (fsl_readl(&dr_regs->endpointprime)) { 1648 /* Wait until all endptprime bits cleared */ 1649 if (time_after(jiffies, timeout)) { 1650 ERR("Timeout for reset\n"); 1651 break; 1652 } 1653 cpu_relax(); 1654 } 1655 1656 /* Write 1s to the flush register */ 1657 fsl_writel(0xffffffff, &dr_regs->endptflush); 1658 1659 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { 1660 VDBG("Bus reset"); 1661 /* Reset all the queues, include XD, dTD, EP queue 1662 * head and TR Queue */ 1663 reset_queues(udc); 1664 udc->usb_state = USB_STATE_DEFAULT; 1665 } else { 1666 VDBG("Controller reset"); 1667 /* initialize usb hw reg except for regs for EP, not 1668 * touch usbintr reg */ 1669 dr_controller_setup(udc); 1670 1671 /* Reset all internal used Queues */ 1672 reset_queues(udc); 1673 1674 ep0_setup(udc); 1675 1676 /* Enable DR IRQ reg, Set Run bit, change udc state */ 1677 dr_controller_run(udc); 1678 udc->usb_state = USB_STATE_ATTACHED; 1679 } 1680} 1681 1682/* 1683 * USB device controller interrupt handler 1684 */ 1685static irqreturn_t fsl_udc_irq(int irq, void *_udc) 1686{ 1687 struct fsl_udc *udc = _udc; 1688 u32 irq_src; 1689 irqreturn_t status = IRQ_NONE; 1690 unsigned long flags; 1691 1692 /* Disable ISR for OTG host mode */ 1693 if (udc->stopped) 1694 return IRQ_NONE; 1695 spin_lock_irqsave(&udc->lock, flags); 1696 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); 1697 /* Clear notification bits */ 1698 fsl_writel(irq_src, &dr_regs->usbsts); 1699 1700 /* VDBG("irq_src [0x%8x]", irq_src); */ 1701 1702 /* Need to resume? */ 1703 if (udc->usb_state == USB_STATE_SUSPENDED) 1704 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0) 1705 bus_resume(udc); 1706 1707 /* USB Interrupt */ 1708 if (irq_src & USB_STS_INT) { 1709 VDBG("Packet int"); 1710 /* Setup package, we only support ep0 as control ep */ 1711 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { 1712 tripwire_handler(udc, 0, 1713 (u8 *) (&udc->local_setup_buff)); 1714 setup_received_irq(udc, &udc->local_setup_buff); 1715 status = IRQ_HANDLED; 1716 } 1717 1718 /* completion of dtd */ 1719 if (fsl_readl(&dr_regs->endptcomplete)) { 1720 dtd_complete_irq(udc); 1721 status = IRQ_HANDLED; 1722 } 1723 } 1724 1725 /* SOF (for ISO transfer) */ 1726 if (irq_src & USB_STS_SOF) { 1727 status = IRQ_HANDLED; 1728 } 1729 1730 /* Port Change */ 1731 if (irq_src & USB_STS_PORT_CHANGE) { 1732 port_change_irq(udc); 1733 status = IRQ_HANDLED; 1734 } 1735 1736 /* Reset Received */ 1737 if (irq_src & USB_STS_RESET) { 1738 reset_irq(udc); 1739 status = IRQ_HANDLED; 1740 } 1741 1742 /* Sleep Enable (Suspend) */ 1743 if (irq_src & USB_STS_SUSPEND) { 1744 suspend_irq(udc); 1745 status = IRQ_HANDLED; 1746 } 1747 1748 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) { 1749 VDBG("Error IRQ %x", irq_src); 1750 } 1751 1752 spin_unlock_irqrestore(&udc->lock, flags); 1753 return status; 1754} 1755 1756/*----------------------------------------------------------------* 1757 * Hook to gadget drivers 1758 * Called by initialization code of gadget drivers 1759*----------------------------------------------------------------*/ 1760int usb_gadget_probe_driver(struct usb_gadget_driver *driver, 1761 int (*bind)(struct usb_gadget *)) 1762{ 1763 int retval = -ENODEV; 1764 unsigned long flags = 0; 1765 1766 if (!udc_controller) 1767 return -ENODEV; 1768 1769 if (!driver || (driver->speed != USB_SPEED_FULL 1770 && driver->speed != USB_SPEED_HIGH) 1771 || !bind || !driver->disconnect || !driver->setup) 1772 return -EINVAL; 1773 1774 if (udc_controller->driver) 1775 return -EBUSY; 1776 1777 /* lock is needed but whether should use this lock or another */ 1778 spin_lock_irqsave(&udc_controller->lock, flags); 1779 1780 driver->driver.bus = NULL; 1781 /* hook up the driver */ 1782 udc_controller->driver = driver; 1783 udc_controller->gadget.dev.driver = &driver->driver; 1784 spin_unlock_irqrestore(&udc_controller->lock, flags); 1785 1786 /* bind udc driver to gadget driver */ 1787 retval = bind(&udc_controller->gadget); 1788 if (retval) { 1789 VDBG("bind to %s --> %d", driver->driver.name, retval); 1790 udc_controller->gadget.dev.driver = NULL; 1791 udc_controller->driver = NULL; 1792 goto out; 1793 } 1794 1795 /* Enable DR IRQ reg and Set usbcmd reg Run bit */ 1796 dr_controller_run(udc_controller); 1797 udc_controller->usb_state = USB_STATE_ATTACHED; 1798 udc_controller->ep0_state = WAIT_FOR_SETUP; 1799 udc_controller->ep0_dir = 0; 1800 printk(KERN_INFO "%s: bind to driver %s\n", 1801 udc_controller->gadget.name, driver->driver.name); 1802 1803out: 1804 if (retval) 1805 printk(KERN_WARNING "gadget driver register failed %d\n", 1806 retval); 1807 return retval; 1808} 1809EXPORT_SYMBOL(usb_gadget_probe_driver); 1810 1811/* Disconnect from gadget driver */ 1812int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 1813{ 1814 struct fsl_ep *loop_ep; 1815 unsigned long flags; 1816 1817 if (!udc_controller) 1818 return -ENODEV; 1819 1820 if (!driver || driver != udc_controller->driver || !driver->unbind) 1821 return -EINVAL; 1822 1823 if (udc_controller->transceiver) 1824 otg_set_peripheral(udc_controller->transceiver, NULL); 1825 1826 /* stop DR, disable intr */ 1827 dr_controller_stop(udc_controller); 1828 1829 /* in fact, no needed */ 1830 udc_controller->usb_state = USB_STATE_ATTACHED; 1831 udc_controller->ep0_state = WAIT_FOR_SETUP; 1832 udc_controller->ep0_dir = 0; 1833 1834 /* stand operation */ 1835 spin_lock_irqsave(&udc_controller->lock, flags); 1836 udc_controller->gadget.speed = USB_SPEED_UNKNOWN; 1837 nuke(&udc_controller->eps[0], -ESHUTDOWN); 1838 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list, 1839 ep.ep_list) 1840 nuke(loop_ep, -ESHUTDOWN); 1841 spin_unlock_irqrestore(&udc_controller->lock, flags); 1842 1843 /* report disconnect; the controller is already quiesced */ 1844 driver->disconnect(&udc_controller->gadget); 1845 1846 /* unbind gadget and unhook driver. */ 1847 driver->unbind(&udc_controller->gadget); 1848 udc_controller->gadget.dev.driver = NULL; 1849 udc_controller->driver = NULL; 1850 1851 printk(KERN_WARNING "unregistered gadget driver '%s'\n", 1852 driver->driver.name); 1853 return 0; 1854} 1855EXPORT_SYMBOL(usb_gadget_unregister_driver); 1856 1857/*------------------------------------------------------------------------- 1858 PROC File System Support 1859-------------------------------------------------------------------------*/ 1860#ifdef CONFIG_USB_GADGET_DEBUG_FILES 1861 1862#include <linux/seq_file.h> 1863 1864static const char proc_filename[] = "driver/fsl_usb2_udc"; 1865 1866static int fsl_proc_read(char *page, char **start, off_t off, int count, 1867 int *eof, void *_dev) 1868{ 1869 char *buf = page; 1870 char *next = buf; 1871 unsigned size = count; 1872 unsigned long flags; 1873 int t, i; 1874 u32 tmp_reg; 1875 struct fsl_ep *ep = NULL; 1876 struct fsl_req *req; 1877 1878 struct fsl_udc *udc = udc_controller; 1879 if (off != 0) 1880 return 0; 1881 1882 spin_lock_irqsave(&udc->lock, flags); 1883 1884 /* ------basic driver information ---- */ 1885 t = scnprintf(next, size, 1886 DRIVER_DESC "\n" 1887 "%s version: %s\n" 1888 "Gadget driver: %s\n\n", 1889 driver_name, DRIVER_VERSION, 1890 udc->driver ? udc->driver->driver.name : "(none)"); 1891 size -= t; 1892 next += t; 1893 1894 /* ------ DR Registers ----- */ 1895 tmp_reg = fsl_readl(&dr_regs->usbcmd); 1896 t = scnprintf(next, size, 1897 "USBCMD reg:\n" 1898 "SetupTW: %d\n" 1899 "Run/Stop: %s\n\n", 1900 (tmp_reg & USB_CMD_SUTW) ? 1 : 0, 1901 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop"); 1902 size -= t; 1903 next += t; 1904 1905 tmp_reg = fsl_readl(&dr_regs->usbsts); 1906 t = scnprintf(next, size, 1907 "USB Status Reg:\n" 1908 "Dr Suspend: %d Reset Received: %d System Error: %s " 1909 "USB Error Interrupt: %s\n\n", 1910 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0, 1911 (tmp_reg & USB_STS_RESET) ? 1 : 0, 1912 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal", 1913 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err"); 1914 size -= t; 1915 next += t; 1916 1917 tmp_reg = fsl_readl(&dr_regs->usbintr); 1918 t = scnprintf(next, size, 1919 "USB Intrrupt Enable Reg:\n" 1920 "Sleep Enable: %d SOF Received Enable: %d " 1921 "Reset Enable: %d\n" 1922 "System Error Enable: %d " 1923 "Port Change Dectected Enable: %d\n" 1924 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n", 1925 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0, 1926 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0, 1927 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0, 1928 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0, 1929 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0, 1930 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0, 1931 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0); 1932 size -= t; 1933 next += t; 1934 1935 tmp_reg = fsl_readl(&dr_regs->frindex); 1936 t = scnprintf(next, size, 1937 "USB Frame Index Reg: Frame Number is 0x%x\n\n", 1938 (tmp_reg & USB_FRINDEX_MASKS)); 1939 size -= t; 1940 next += t; 1941 1942 tmp_reg = fsl_readl(&dr_regs->deviceaddr); 1943 t = scnprintf(next, size, 1944 "USB Device Address Reg: Device Addr is 0x%x\n\n", 1945 (tmp_reg & USB_DEVICE_ADDRESS_MASK)); 1946 size -= t; 1947 next += t; 1948 1949 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr); 1950 t = scnprintf(next, size, 1951 "USB Endpoint List Address Reg: " 1952 "Device Addr is 0x%x\n\n", 1953 (tmp_reg & USB_EP_LIST_ADDRESS_MASK)); 1954 size -= t; 1955 next += t; 1956 1957 tmp_reg = fsl_readl(&dr_regs->portsc1); 1958 t = scnprintf(next, size, 1959 "USB Port Status&Control Reg:\n" 1960 "Port Transceiver Type : %s Port Speed: %s\n" 1961 "PHY Low Power Suspend: %s Port Reset: %s " 1962 "Port Suspend Mode: %s\n" 1963 "Over-current Change: %s " 1964 "Port Enable/Disable Change: %s\n" 1965 "Port Enabled/Disabled: %s " 1966 "Current Connect Status: %s\n\n", ( { 1967 char *s; 1968 switch (tmp_reg & PORTSCX_PTS_FSLS) { 1969 case PORTSCX_PTS_UTMI: 1970 s = "UTMI"; break; 1971 case PORTSCX_PTS_ULPI: 1972 s = "ULPI "; break; 1973 case PORTSCX_PTS_FSLS: 1974 s = "FS/LS Serial"; break; 1975 default: 1976 s = "None"; break; 1977 } 1978 s;} ), ( { 1979 char *s; 1980 switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) { 1981 case PORTSCX_PORT_SPEED_FULL: 1982 s = "Full Speed"; break; 1983 case PORTSCX_PORT_SPEED_LOW: 1984 s = "Low Speed"; break; 1985 case PORTSCX_PORT_SPEED_HIGH: 1986 s = "High Speed"; break; 1987 default: 1988 s = "Undefined"; break; 1989 } 1990 s; 1991 } ), 1992 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? 1993 "Normal PHY mode" : "Low power mode", 1994 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : 1995 "Not in Reset", 1996 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in", 1997 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" : 1998 "No", 1999 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" : 2000 "Not change", 2001 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" : 2002 "Not correct", 2003 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ? 2004 "Attached" : "Not-Att"); 2005 size -= t; 2006 next += t; 2007 2008 tmp_reg = fsl_readl(&dr_regs->usbmode); 2009 t = scnprintf(next, size, 2010 "USB Mode Reg: Controller Mode is: %s\n\n", ( { 2011 char *s; 2012 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) { 2013 case USB_MODE_CTRL_MODE_IDLE: 2014 s = "Idle"; break; 2015 case USB_MODE_CTRL_MODE_DEVICE: 2016 s = "Device Controller"; break; 2017 case USB_MODE_CTRL_MODE_HOST: 2018 s = "Host Controller"; break; 2019 default: 2020 s = "None"; break; 2021 } 2022 s; 2023 } )); 2024 size -= t; 2025 next += t; 2026 2027 tmp_reg = fsl_readl(&dr_regs->endptsetupstat); 2028 t = scnprintf(next, size, 2029 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n", 2030 (tmp_reg & EP_SETUP_STATUS_MASK)); 2031 size -= t; 2032 next += t; 2033 2034 for (i = 0; i < udc->max_ep / 2; i++) { 2035 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]); 2036 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n", 2037 i, tmp_reg); 2038 size -= t; 2039 next += t; 2040 } 2041 tmp_reg = fsl_readl(&dr_regs->endpointprime); 2042 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg); 2043 size -= t; 2044 next += t; 2045 2046#ifndef CONFIG_ARCH_MXC 2047 tmp_reg = usb_sys_regs->snoop1; 2048 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg); 2049 size -= t; 2050 next += t; 2051 2052 tmp_reg = usb_sys_regs->control; 2053 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n", 2054 tmp_reg); 2055 size -= t; 2056 next += t; 2057#endif 2058 2059 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ 2060 ep = &udc->eps[0]; 2061 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n", 2062 ep->ep.name, ep_maxpacket(ep), ep_index(ep)); 2063 size -= t; 2064 next += t; 2065 2066 if (list_empty(&ep->queue)) { 2067 t = scnprintf(next, size, "its req queue is empty\n\n"); 2068 size -= t; 2069 next += t; 2070 } else { 2071 list_for_each_entry(req, &ep->queue, queue) { 2072 t = scnprintf(next, size, 2073 "req %p actual 0x%x length 0x%x buf %p\n", 2074 &req->req, req->req.actual, 2075 req->req.length, req->req.buf); 2076 size -= t; 2077 next += t; 2078 } 2079 } 2080 /* other gadget->eplist ep */ 2081 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2082 if (ep->desc) { 2083 t = scnprintf(next, size, 2084 "\nFor %s Maxpkt is 0x%x " 2085 "index is 0x%x\n", 2086 ep->ep.name, ep_maxpacket(ep), 2087 ep_index(ep)); 2088 size -= t; 2089 next += t; 2090 2091 if (list_empty(&ep->queue)) { 2092 t = scnprintf(next, size, 2093 "its req queue is empty\n\n"); 2094 size -= t; 2095 next += t; 2096 } else { 2097 list_for_each_entry(req, &ep->queue, queue) { 2098 t = scnprintf(next, size, 2099 "req %p actual 0x%x length " 2100 "0x%x buf %p\n", 2101 &req->req, req->req.actual, 2102 req->req.length, req->req.buf); 2103 size -= t; 2104 next += t; 2105 } /* end for each_entry of ep req */ 2106 } /* end for else */ 2107 } /* end for if(ep->queue) */ 2108 } /* end (ep->desc) */ 2109 2110 spin_unlock_irqrestore(&udc->lock, flags); 2111 2112 *eof = 1; 2113 return count - size; 2114} 2115 2116#define create_proc_file() create_proc_read_entry(proc_filename, \ 2117 0, NULL, fsl_proc_read, NULL) 2118 2119#define remove_proc_file() remove_proc_entry(proc_filename, NULL) 2120 2121#else /* !CONFIG_USB_GADGET_DEBUG_FILES */ 2122 2123#define create_proc_file() do {} while (0) 2124#define remove_proc_file() do {} while (0) 2125 2126#endif /* CONFIG_USB_GADGET_DEBUG_FILES */ 2127 2128/*-------------------------------------------------------------------------*/ 2129 2130/* Release udc structures */ 2131static void fsl_udc_release(struct device *dev) 2132{ 2133 complete(udc_controller->done); 2134 dma_free_coherent(dev->parent, udc_controller->ep_qh_size, 2135 udc_controller->ep_qh, udc_controller->ep_qh_dma); 2136 kfree(udc_controller); 2137} 2138 2139/****************************************************************** 2140 Internal structure setup functions 2141*******************************************************************/ 2142/*------------------------------------------------------------------ 2143 * init resource for globle controller 2144 * Return the udc handle on success or NULL on failure 2145 ------------------------------------------------------------------*/ 2146static int __init struct_udc_setup(struct fsl_udc *udc, 2147 struct platform_device *pdev) 2148{ 2149 struct fsl_usb2_platform_data *pdata; 2150 size_t size; 2151 2152 pdata = pdev->dev.platform_data; 2153 udc->phy_mode = pdata->phy_mode; 2154 2155 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL); 2156 if (!udc->eps) { 2157 ERR("malloc fsl_ep failed\n"); 2158 return -1; 2159 } 2160 2161 /* initialized QHs, take care of alignment */ 2162 size = udc->max_ep * sizeof(struct ep_queue_head); 2163 if (size < QH_ALIGNMENT) 2164 size = QH_ALIGNMENT; 2165 else if ((size % QH_ALIGNMENT) != 0) { 2166 size += QH_ALIGNMENT + 1; 2167 size &= ~(QH_ALIGNMENT - 1); 2168 } 2169 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size, 2170 &udc->ep_qh_dma, GFP_KERNEL); 2171 if (!udc->ep_qh) { 2172 ERR("malloc QHs for udc failed\n"); 2173 kfree(udc->eps); 2174 return -1; 2175 } 2176 2177 udc->ep_qh_size = size; 2178 2179 /* Initialize ep0 status request structure */ 2180 /* FIXME: fsl_alloc_request() ignores ep argument */ 2181 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), 2182 struct fsl_req, req); 2183 /* allocate a small amount of memory to get valid address */ 2184 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL); 2185 udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf); 2186 2187 udc->resume_state = USB_STATE_NOTATTACHED; 2188 udc->usb_state = USB_STATE_POWERED; 2189 udc->ep0_dir = 0; 2190 udc->remote_wakeup = 0; /* default to 0 on reset */ 2191 2192 return 0; 2193} 2194 2195/*---------------------------------------------------------------- 2196 * Setup the fsl_ep struct for eps 2197 * Link fsl_ep->ep to gadget->ep_list 2198 * ep0out is not used so do nothing here 2199 * ep0in should be taken care 2200 *--------------------------------------------------------------*/ 2201static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index, 2202 char *name, int link) 2203{ 2204 struct fsl_ep *ep = &udc->eps[index]; 2205 2206 ep->udc = udc; 2207 strcpy(ep->name, name); 2208 ep->ep.name = ep->name; 2209 2210 ep->ep.ops = &fsl_ep_ops; 2211 ep->stopped = 0; 2212 2213 /* for ep0: maxP defined in desc 2214 * for other eps, maxP is set by epautoconfig() called by gadget layer 2215 */ 2216 ep->ep.maxpacket = (unsigned short) ~0; 2217 2218 /* the queue lists any req for this ep */ 2219 INIT_LIST_HEAD(&ep->queue); 2220 2221 /* gagdet.ep_list used for ep_autoconfig so no ep0 */ 2222 if (link) 2223 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 2224 ep->gadget = &udc->gadget; 2225 ep->qh = &udc->ep_qh[index]; 2226 2227 return 0; 2228} 2229 2230/* Driver probe function 2231 * all intialization operations implemented here except enabling usb_intr reg 2232 * board setup should have been done in the platform code 2233 */ 2234static int __init fsl_udc_probe(struct platform_device *pdev) 2235{ 2236 struct resource *res; 2237 int ret = -ENODEV; 2238 unsigned int i; 2239 u32 dccparams; 2240 2241 if (strcmp(pdev->name, driver_name)) { 2242 VDBG("Wrong device"); 2243 return -ENODEV; 2244 } 2245 2246 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); 2247 if (udc_controller == NULL) { 2248 ERR("malloc udc failed\n"); 2249 return -ENOMEM; 2250 } 2251 2252 spin_lock_init(&udc_controller->lock); 2253 udc_controller->stopped = 1; 2254 2255 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2256 if (!res) { 2257 ret = -ENXIO; 2258 goto err_kfree; 2259 } 2260 2261 if (!request_mem_region(res->start, res->end - res->start + 1, 2262 driver_name)) { 2263 ERR("request mem region for %s failed\n", pdev->name); 2264 ret = -EBUSY; 2265 goto err_kfree; 2266 } 2267 2268 dr_regs = ioremap(res->start, resource_size(res)); 2269 if (!dr_regs) { 2270 ret = -ENOMEM; 2271 goto err_release_mem_region; 2272 } 2273 2274#ifndef CONFIG_ARCH_MXC 2275 usb_sys_regs = (struct usb_sys_interface *) 2276 ((u32)dr_regs + USB_DR_SYS_OFFSET); 2277#endif 2278 2279 /* Initialize USB clocks */ 2280 ret = fsl_udc_clk_init(pdev); 2281 if (ret < 0) 2282 goto err_iounmap_noclk; 2283 2284 /* Read Device Controller Capability Parameters register */ 2285 dccparams = fsl_readl(&dr_regs->dccparams); 2286 if (!(dccparams & DCCPARAMS_DC)) { 2287 ERR("This SOC doesn't support device role\n"); 2288 ret = -ENODEV; 2289 goto err_iounmap; 2290 } 2291 /* Get max device endpoints */ 2292 /* DEN is bidirectional ep number, max_ep doubles the number */ 2293 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2; 2294 2295 udc_controller->irq = platform_get_irq(pdev, 0); 2296 if (!udc_controller->irq) { 2297 ret = -ENODEV; 2298 goto err_iounmap; 2299 } 2300 2301 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED, 2302 driver_name, udc_controller); 2303 if (ret != 0) { 2304 ERR("cannot request irq %d err %d\n", 2305 udc_controller->irq, ret); 2306 goto err_iounmap; 2307 } 2308 2309 /* Initialize the udc structure including QH member and other member */ 2310 if (struct_udc_setup(udc_controller, pdev)) { 2311 ERR("Can't initialize udc data structure\n"); 2312 ret = -ENOMEM; 2313 goto err_free_irq; 2314 } 2315 2316 /* initialize usb hw reg except for regs for EP, 2317 * leave usbintr reg untouched */ 2318 dr_controller_setup(udc_controller); 2319 2320 fsl_udc_clk_finalize(pdev); 2321 2322 /* Setup gadget structure */ 2323 udc_controller->gadget.ops = &fsl_gadget_ops; 2324 udc_controller->gadget.is_dualspeed = 1; 2325 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; 2326 INIT_LIST_HEAD(&udc_controller->gadget.ep_list); 2327 udc_controller->gadget.speed = USB_SPEED_UNKNOWN; 2328 udc_controller->gadget.name = driver_name; 2329 2330 /* Setup gadget.dev and register with kernel */ 2331 dev_set_name(&udc_controller->gadget.dev, "gadget"); 2332 udc_controller->gadget.dev.release = fsl_udc_release; 2333 udc_controller->gadget.dev.parent = &pdev->dev; 2334 ret = device_register(&udc_controller->gadget.dev); 2335 if (ret < 0) 2336 goto err_free_irq; 2337 2338 /* setup QH and epctrl for ep0 */ 2339 ep0_setup(udc_controller); 2340 2341 /* setup udc->eps[] for ep0 */ 2342 struct_ep_setup(udc_controller, 0, "ep0", 0); 2343 /* for ep0: the desc defined here; 2344 * for other eps, gadget layer called ep_enable with defined desc 2345 */ 2346 udc_controller->eps[0].desc = &fsl_ep0_desc; 2347 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD; 2348 2349 /* setup the udc->eps[] for non-control endpoints and link 2350 * to gadget.ep_list */ 2351 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) { 2352 char name[14]; 2353 2354 sprintf(name, "ep%dout", i); 2355 struct_ep_setup(udc_controller, i * 2, name, 1); 2356 sprintf(name, "ep%din", i); 2357 struct_ep_setup(udc_controller, i * 2 + 1, name, 1); 2358 } 2359 2360 /* use dma_pool for TD management */ 2361 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev, 2362 sizeof(struct ep_td_struct), 2363 DTD_ALIGNMENT, UDC_DMA_BOUNDARY); 2364 if (udc_controller->td_pool == NULL) { 2365 ret = -ENOMEM; 2366 goto err_unregister; 2367 } 2368 create_proc_file(); 2369 return 0; 2370 2371err_unregister: 2372 device_unregister(&udc_controller->gadget.dev); 2373err_free_irq: 2374 free_irq(udc_controller->irq, udc_controller); 2375err_iounmap: 2376 fsl_udc_clk_release(); 2377err_iounmap_noclk: 2378 iounmap(dr_regs); 2379err_release_mem_region: 2380 release_mem_region(res->start, res->end - res->start + 1); 2381err_kfree: 2382 kfree(udc_controller); 2383 udc_controller = NULL; 2384 return ret; 2385} 2386 2387/* Driver removal function 2388 * Free resources and finish pending transactions 2389 */ 2390static int __exit fsl_udc_remove(struct platform_device *pdev) 2391{ 2392 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2393 2394 DECLARE_COMPLETION(done); 2395 2396 if (!udc_controller) 2397 return -ENODEV; 2398 udc_controller->done = &done; 2399 2400 fsl_udc_clk_release(); 2401 2402 /* DR has been stopped in usb_gadget_unregister_driver() */ 2403 remove_proc_file(); 2404 2405 /* Free allocated memory */ 2406 kfree(udc_controller->status_req->req.buf); 2407 kfree(udc_controller->status_req); 2408 kfree(udc_controller->eps); 2409 2410 dma_pool_destroy(udc_controller->td_pool); 2411 free_irq(udc_controller->irq, udc_controller); 2412 iounmap(dr_regs); 2413 release_mem_region(res->start, res->end - res->start + 1); 2414 2415 device_unregister(&udc_controller->gadget.dev); 2416 /* free udc --wait for the release() finished */ 2417 wait_for_completion(&done); 2418 2419 return 0; 2420} 2421 2422/*----------------------------------------------------------------- 2423 * Modify Power management attributes 2424 * Used by OTG statemachine to disable gadget temporarily 2425 -----------------------------------------------------------------*/ 2426static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) 2427{ 2428 dr_controller_stop(udc_controller); 2429 return 0; 2430} 2431 2432/*----------------------------------------------------------------- 2433 * Invoked on USB resume. May be called in_interrupt. 2434 * Here we start the DR controller and enable the irq 2435 *-----------------------------------------------------------------*/ 2436static int fsl_udc_resume(struct platform_device *pdev) 2437{ 2438 /* Enable DR irq reg and set controller Run */ 2439 if (udc_controller->stopped) { 2440 dr_controller_setup(udc_controller); 2441 dr_controller_run(udc_controller); 2442 } 2443 udc_controller->usb_state = USB_STATE_ATTACHED; 2444 udc_controller->ep0_state = WAIT_FOR_SETUP; 2445 udc_controller->ep0_dir = 0; 2446 return 0; 2447} 2448 2449/*------------------------------------------------------------------------- 2450 Register entry point for the peripheral controller driver 2451--------------------------------------------------------------------------*/ 2452 2453static struct platform_driver udc_driver = { 2454 .remove = __exit_p(fsl_udc_remove), 2455 /* these suspend and resume are not usb suspend and resume */ 2456 .suspend = fsl_udc_suspend, 2457 .resume = fsl_udc_resume, 2458 .driver = { 2459 .name = (char *)driver_name, 2460 .owner = THIS_MODULE, 2461 }, 2462}; 2463 2464static int __init udc_init(void) 2465{ 2466 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION); 2467 return platform_driver_probe(&udc_driver, fsl_udc_probe); 2468} 2469 2470module_init(udc_init); 2471 2472static void __exit udc_exit(void) 2473{ 2474 platform_driver_unregister(&udc_driver); 2475 printk(KERN_WARNING "%s unregistered\n", driver_desc); 2476} 2477 2478module_exit(udc_exit); 2479 2480MODULE_DESCRIPTION(DRIVER_DESC); 2481MODULE_AUTHOR(DRIVER_AUTHOR); 2482MODULE_LICENSE("GPL"); 2483MODULE_ALIAS("platform:fsl-usb2-udc"); 2484