atyfb_base.c revision 50c839c7b5e7d7cc3443176f5d5458e134b0b189
1/* 2 * ATI Frame Buffer Device Driver Core 3 * 4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de> 5 * Copyright (C) 1997-2001 Geert Uytterhoeven 6 * Copyright (C) 1998 Bernd Harries 7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 8 * 9 * This driver supports the following ATI graphics chips: 10 * - ATI Mach64 11 * 12 * To do: add support for 13 * - ATI Rage128 (from aty128fb.c) 14 * - ATI Radeon (from radeonfb.c) 15 * 16 * This driver is partly based on the PowerMac console driver: 17 * 18 * Copyright (C) 1996 Paul Mackerras 19 * 20 * and on the PowerMac ATI/mach64 display driver: 21 * 22 * Copyright (C) 1997 Michael AK Tesch 23 * 24 * with work by Jon Howell 25 * Harry AC Eaton 26 * Anthony Tong <atong@uiuc.edu> 27 * 28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern 29 * Many Thanks to Ville Syrj�l� for patches and fixing nasting 16 bit color bug. 30 * 31 * This file is subject to the terms and conditions of the GNU General Public 32 * License. See the file COPYING in the main directory of this archive for 33 * more details. 34 * 35 * Many thanks to Nitya from ATI devrel for support and patience ! 36 */ 37 38/****************************************************************************** 39 40 TODO: 41 42 - cursor support on all cards and all ramdacs. 43 - cursor parameters controlable via ioctl()s. 44 - guess PLL and MCLK based on the original PLL register values initialized 45 by Open Firmware (if they are initialized). BIOS is done 46 47 (Anyone with Mac to help with this?) 48 49******************************************************************************/ 50 51 52#include <linux/config.h> 53#include <linux/module.h> 54#include <linux/moduleparam.h> 55#include <linux/kernel.h> 56#include <linux/errno.h> 57#include <linux/string.h> 58#include <linux/mm.h> 59#include <linux/slab.h> 60#include <linux/vmalloc.h> 61#include <linux/delay.h> 62#include <linux/console.h> 63#include <linux/fb.h> 64#include <linux/init.h> 65#include <linux/pci.h> 66#include <linux/interrupt.h> 67#include <linux/spinlock.h> 68#include <linux/wait.h> 69 70#include <asm/io.h> 71#include <asm/uaccess.h> 72 73#include <video/mach64.h> 74#include "atyfb.h" 75#include "ati_ids.h" 76 77#ifdef __powerpc__ 78#include <asm/prom.h> 79#include "../macmodes.h" 80#endif 81#ifdef __sparc__ 82#include <asm/pbm.h> 83#include <asm/fbio.h> 84#endif 85 86#ifdef CONFIG_ADB_PMU 87#include <linux/adb.h> 88#include <linux/pmu.h> 89#endif 90#ifdef CONFIG_BOOTX_TEXT 91#include <asm/btext.h> 92#endif 93#ifdef CONFIG_PMAC_BACKLIGHT 94#include <asm/backlight.h> 95#endif 96#ifdef CONFIG_MTRR 97#include <asm/mtrr.h> 98#endif 99 100/* 101 * Debug flags. 102 */ 103#undef DEBUG 104/*#define DEBUG*/ 105 106/* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */ 107/* - must be large enough to catch all GUI-Regs */ 108/* - must be aligned to a PAGE boundary */ 109#define GUI_RESERVE (1 * PAGE_SIZE) 110 111/* FIXME: remove the FAIL definition */ 112#define FAIL(msg) do { \ 113 if (!(var->activate & FB_ACTIVATE_TEST)) \ 114 printk(KERN_CRIT "atyfb: " msg "\n"); \ 115 return -EINVAL; \ 116} while (0) 117#define FAIL_MAX(msg, x, _max_) do { \ 118 if (x > _max_) { \ 119 if (!(var->activate & FB_ACTIVATE_TEST)) \ 120 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \ 121 return -EINVAL; \ 122 } \ 123} while (0) 124#ifdef DEBUG 125#define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args) 126#else 127#define DPRINTK(fmt, args...) 128#endif 129 130#define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args) 131#define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args) 132 133#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) 134static const u32 lt_lcd_regs[] = { 135 CONFIG_PANEL_LG, 136 LCD_GEN_CNTL_LG, 137 DSTN_CONTROL_LG, 138 HFB_PITCH_ADDR_LG, 139 HORZ_STRETCHING_LG, 140 VERT_STRETCHING_LG, 141 0, /* EXT_VERT_STRETCH */ 142 LT_GIO_LG, 143 POWER_MANAGEMENT_LG 144}; 145 146void aty_st_lcd(int index, u32 val, const struct atyfb_par *par) 147{ 148 if (M64_HAS(LT_LCD_REGS)) { 149 aty_st_le32(lt_lcd_regs[index], val, par); 150 } else { 151 unsigned long temp; 152 153 /* write addr byte */ 154 temp = aty_ld_le32(LCD_INDEX, par); 155 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); 156 /* write the register value */ 157 aty_st_le32(LCD_DATA, val, par); 158 } 159} 160 161u32 aty_ld_lcd(int index, const struct atyfb_par *par) 162{ 163 if (M64_HAS(LT_LCD_REGS)) { 164 return aty_ld_le32(lt_lcd_regs[index], par); 165 } else { 166 unsigned long temp; 167 168 /* write addr byte */ 169 temp = aty_ld_le32(LCD_INDEX, par); 170 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); 171 /* read the register value */ 172 return aty_ld_le32(LCD_DATA, par); 173 } 174} 175#endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */ 176 177#ifdef CONFIG_FB_ATY_GENERIC_LCD 178/* 179 * ATIReduceRatio -- 180 * 181 * Reduce a fraction by factoring out the largest common divider of the 182 * fraction's numerator and denominator. 183 */ 184static void ATIReduceRatio(int *Numerator, int *Denominator) 185{ 186 int Multiplier, Divider, Remainder; 187 188 Multiplier = *Numerator; 189 Divider = *Denominator; 190 191 while ((Remainder = Multiplier % Divider)) 192 { 193 Multiplier = Divider; 194 Divider = Remainder; 195 } 196 197 *Numerator /= Divider; 198 *Denominator /= Divider; 199} 200#endif 201 /* 202 * The Hardware parameters for each card 203 */ 204 205struct aty_cmap_regs { 206 u8 windex; 207 u8 lut; 208 u8 mask; 209 u8 rindex; 210 u8 cntl; 211}; 212 213struct pci_mmap_map { 214 unsigned long voff; 215 unsigned long poff; 216 unsigned long size; 217 unsigned long prot_flag; 218 unsigned long prot_mask; 219}; 220 221static struct fb_fix_screeninfo atyfb_fix __devinitdata = { 222 .id = "ATY Mach64", 223 .type = FB_TYPE_PACKED_PIXELS, 224 .visual = FB_VISUAL_PSEUDOCOLOR, 225 .xpanstep = 8, 226 .ypanstep = 1, 227}; 228 229 /* 230 * Frame buffer device API 231 */ 232 233static int atyfb_open(struct fb_info *info, int user); 234static int atyfb_release(struct fb_info *info, int user); 235static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info); 236static int atyfb_set_par(struct fb_info *info); 237static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 238 u_int transp, struct fb_info *info); 239static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); 240static int atyfb_blank(int blank, struct fb_info *info); 241static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd, 242 u_long arg, struct fb_info *info); 243extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect); 244extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 245extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image); 246#ifdef __sparc__ 247static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma); 248#endif 249static int atyfb_sync(struct fb_info *info); 250 251 /* 252 * Internal routines 253 */ 254 255static int aty_init(struct fb_info *info, const char *name); 256#ifdef CONFIG_ATARI 257static int store_video_par(char *videopar, unsigned char m64_num); 258#endif 259 260static struct crtc saved_crtc; 261static union aty_pll saved_pll; 262static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc); 263 264static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc); 265static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc); 266static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var); 267static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info); 268#ifdef CONFIG_PPC 269static int read_aty_sense(const struct atyfb_par *par); 270#endif 271 272 273 /* 274 * Interface used by the world 275 */ 276 277static struct fb_var_screeninfo default_var = { 278 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 279 640, 480, 640, 480, 0, 0, 8, 0, 280 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 281 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 282 0, FB_VMODE_NONINTERLACED 283}; 284 285static struct fb_videomode defmode = { 286 /* 640x480 @ 60 Hz, 31.5 kHz hsync */ 287 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 288 0, FB_VMODE_NONINTERLACED 289}; 290 291static struct fb_ops atyfb_ops = { 292 .owner = THIS_MODULE, 293 .fb_open = atyfb_open, 294 .fb_release = atyfb_release, 295 .fb_check_var = atyfb_check_var, 296 .fb_set_par = atyfb_set_par, 297 .fb_setcolreg = atyfb_setcolreg, 298 .fb_pan_display = atyfb_pan_display, 299 .fb_blank = atyfb_blank, 300 .fb_ioctl = atyfb_ioctl, 301 .fb_fillrect = atyfb_fillrect, 302 .fb_copyarea = atyfb_copyarea, 303 .fb_imageblit = atyfb_imageblit, 304#ifdef __sparc__ 305 .fb_mmap = atyfb_mmap, 306#endif 307 .fb_sync = atyfb_sync, 308}; 309 310static int noaccel; 311#ifdef CONFIG_MTRR 312static int nomtrr; 313#endif 314static int vram; 315static int pll; 316static int mclk; 317static int xclk; 318static int comp_sync __initdata = -1; 319static char *mode; 320 321#ifdef CONFIG_PPC 322static int default_vmode __initdata = VMODE_CHOOSE; 323static int default_cmode __initdata = CMODE_CHOOSE; 324 325module_param_named(vmode, default_vmode, int, 0); 326MODULE_PARM_DESC(vmode, "int: video mode for mac"); 327module_param_named(cmode, default_cmode, int, 0); 328MODULE_PARM_DESC(cmode, "int: color mode for mac"); 329#endif 330 331#ifdef CONFIG_ATARI 332static unsigned int mach64_count __initdata = 0; 333static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, }; 334static unsigned long phys_size[FB_MAX] __initdata = { 0, }; 335static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, }; 336#endif 337 338/* top -> down is an evolution of mach64 chipset, any corrections? */ 339#define ATI_CHIP_88800GX (M64F_GX) 340#define ATI_CHIP_88800CX (M64F_GX) 341 342#define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO) 343#define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO) 344 345#define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO) 346#define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT) 347 348#define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP) 349#define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL) 350#define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP) 351 352#define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP) 353 354/* make sets shorter */ 355#define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT) 356 357#define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL) 358/*#define ATI_CHIP_264GTDVD ?*/ 359#define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL) 360 361#define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE) 362#define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D) 363#define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D) 364 365#define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4) 366#define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS) 367 368static struct { 369 u16 pci_id; 370 const char *name; 371 int pll, mclk, xclk; 372 u32 features; 373} aty_chips[] __devinitdata = { 374#ifdef CONFIG_FB_ATY_GX 375 /* Mach64 GX */ 376 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX }, 377 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX }, 378#endif /* CONFIG_FB_ATY_GX */ 379 380#ifdef CONFIG_FB_ATY_CT 381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT }, 382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET }, 383 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT }, 384 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT }, 385 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */ 386 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB }, 387 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 }, 388 389 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT }, 390 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */ 391 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 }, 392 393 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 }, 394 395 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C }, 396 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C }, 397 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C }, 398 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C }, 399 400 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO }, 401 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO }, 402 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE }, 403 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO }, 404 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO }, 405 406 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO }, 407 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO }, 408 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 }, 409 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO }, 410 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO }, 411 412 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL }, 413 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL }, 414 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL }, 415 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 235, 83, 63, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL }, 416 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL }, 417 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL }, 418 419 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY }, 420 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY }, 421 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY }, 422 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY }, 423#endif /* CONFIG_FB_ATY_CT */ 424}; 425 426/* can not fail */ 427static int __devinit correct_chipset(struct atyfb_par *par) 428{ 429 u8 rev; 430 u16 type; 431 u32 chip_id; 432 const char *name; 433 int i; 434 435 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--) 436 if (par->pci_id == aty_chips[i].pci_id) 437 break; 438 439 name = aty_chips[i].name; 440 par->pll_limits.pll_max = aty_chips[i].pll; 441 par->pll_limits.mclk = aty_chips[i].mclk; 442 par->pll_limits.xclk = aty_chips[i].xclk; 443 par->features = aty_chips[i].features; 444 445 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par); 446 type = chip_id & CFG_CHIP_TYPE; 447 rev = (chip_id & CFG_CHIP_REV) >> 24; 448 449 switch(par->pci_id) { 450#ifdef CONFIG_FB_ATY_GX 451 case PCI_CHIP_MACH64GX: 452 if(type != 0x00d7) 453 return -ENODEV; 454 break; 455 case PCI_CHIP_MACH64CX: 456 if(type != 0x0057) 457 return -ENODEV; 458 break; 459#endif 460#ifdef CONFIG_FB_ATY_CT 461 case PCI_CHIP_MACH64VT: 462 rev &= 0xc7; 463 if(rev == 0x00) { 464 name = "ATI264VTA3 (Mach64 VT)"; 465 par->pll_limits.pll_max = 170; 466 par->pll_limits.mclk = 67; 467 par->pll_limits.xclk = 67; 468 par->features = ATI_CHIP_264VT; 469 } else if(rev == 0x40) { 470 name = "ATI264VTA4 (Mach64 VT)"; 471 par->pll_limits.pll_max = 200; 472 par->pll_limits.mclk = 67; 473 par->pll_limits.xclk = 67; 474 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV; 475 } else { 476 name = "ATI264VTB (Mach64 VT)"; 477 par->pll_limits.pll_max = 200; 478 par->pll_limits.mclk = 67; 479 par->pll_limits.xclk = 67; 480 par->features = ATI_CHIP_264VTB; 481 } 482 break; 483 case PCI_CHIP_MACH64GT: 484 rev &= 0x07; 485 if(rev == 0x01) { 486 par->pll_limits.pll_max = 170; 487 par->pll_limits.mclk = 67; 488 par->pll_limits.xclk = 67; 489 par->features = ATI_CHIP_264GTB; 490 } else if(rev == 0x02) { 491 par->pll_limits.pll_max = 200; 492 par->pll_limits.mclk = 67; 493 par->pll_limits.xclk = 67; 494 par->features = ATI_CHIP_264GTB; 495 } 496 break; 497#endif 498 } 499 500 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev); 501 return 0; 502} 503 504static char ram_dram[] __devinitdata = "DRAM"; 505static char ram_resv[] __devinitdata = "RESV"; 506#ifdef CONFIG_FB_ATY_GX 507static char ram_vram[] __devinitdata = "VRAM"; 508#endif /* CONFIG_FB_ATY_GX */ 509#ifdef CONFIG_FB_ATY_CT 510static char ram_edo[] __devinitdata = "EDO"; 511static char ram_sdram[] __devinitdata = "SDRAM (1:1)"; 512static char ram_sgram[] __devinitdata = "SGRAM (1:1)"; 513static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)"; 514static char ram_off[] __devinitdata = "OFF"; 515#endif /* CONFIG_FB_ATY_CT */ 516 517 518static u32 pseudo_palette[17]; 519 520#ifdef CONFIG_FB_ATY_GX 521static char *aty_gx_ram[8] __devinitdata = { 522 ram_dram, ram_vram, ram_vram, ram_dram, 523 ram_dram, ram_vram, ram_vram, ram_resv 524}; 525#endif /* CONFIG_FB_ATY_GX */ 526 527#ifdef CONFIG_FB_ATY_CT 528static char *aty_ct_ram[8] __devinitdata = { 529 ram_off, ram_dram, ram_edo, ram_edo, 530 ram_sdram, ram_sgram, ram_sdram32, ram_resv 531}; 532#endif /* CONFIG_FB_ATY_CT */ 533 534static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par) 535{ 536 u32 pixclock = var->pixclock; 537#ifdef CONFIG_FB_ATY_GENERIC_LCD 538 u32 lcd_on_off; 539 par->pll.ct.xres = 0; 540 if (par->lcd_table != 0) { 541 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par); 542 if(lcd_on_off & LCD_ON) { 543 par->pll.ct.xres = var->xres; 544 pixclock = par->lcd_pixclock; 545 } 546 } 547#endif 548 return pixclock; 549} 550 551#if defined(CONFIG_PPC) 552 553/* 554 * Apple monitor sense 555 */ 556 557static int __init read_aty_sense(const struct atyfb_par *par) 558{ 559 int sense, i; 560 561 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */ 562 __delay(200); 563 aty_st_le32(GP_IO, 0, par); /* turn off outputs */ 564 __delay(2000); 565 i = aty_ld_le32(GP_IO, par); /* get primary sense value */ 566 sense = ((i & 0x3000) >> 3) | (i & 0x100); 567 568 /* drive each sense line low in turn and collect the other 2 */ 569 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */ 570 __delay(2000); 571 i = aty_ld_le32(GP_IO, par); 572 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4); 573 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */ 574 __delay(200); 575 576 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */ 577 __delay(2000); 578 i = aty_ld_le32(GP_IO, par); 579 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6); 580 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */ 581 __delay(200); 582 583 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */ 584 __delay(2000); 585 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12; 586 aty_st_le32(GP_IO, 0, par); /* turn off outputs */ 587 return sense; 588} 589 590#endif /* defined(CONFIG_PPC) */ 591 592/* ------------------------------------------------------------------------- */ 593 594/* 595 * CRTC programming 596 */ 597 598static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc) 599{ 600#ifdef CONFIG_FB_ATY_GENERIC_LCD 601 if (par->lcd_table != 0) { 602 if(!M64_HAS(LT_LCD_REGS)) { 603 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par); 604 aty_st_le32(LCD_INDEX, crtc->lcd_index, par); 605 } 606 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par); 607 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par); 608 609 610 /* switch to non shadow registers */ 611 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl & 612 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par); 613 614 /* save stretching */ 615 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par); 616 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par); 617 if (!M64_HAS(LT_LCD_REGS)) 618 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par); 619 } 620#endif 621 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par); 622 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par); 623 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par); 624 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par); 625 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par); 626 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par); 627 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); 628 629#ifdef CONFIG_FB_ATY_GENERIC_LCD 630 if (par->lcd_table != 0) { 631 /* switch to shadow registers */ 632 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) | 633 SHADOW_EN | SHADOW_RW_EN, par); 634 635 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par); 636 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par); 637 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par); 638 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par); 639 640 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par); 641 } 642#endif /* CONFIG_FB_ATY_GENERIC_LCD */ 643} 644 645static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc) 646{ 647#ifdef CONFIG_FB_ATY_GENERIC_LCD 648 if (par->lcd_table != 0) { 649 /* stop CRTC */ 650 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par); 651 652 /* update non-shadow registers first */ 653 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par); 654 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl & 655 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par); 656 657 /* temporarily disable stretching */ 658 aty_st_lcd(HORZ_STRETCHING, 659 crtc->horz_stretching & 660 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par); 661 aty_st_lcd(VERT_STRETCHING, 662 crtc->vert_stretching & 663 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 | 664 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par); 665 } 666#endif 667 /* turn off CRT */ 668 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par); 669 670 DPRINTK("setting up CRTC\n"); 671 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n", 672 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1), 673 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P', 674 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N'); 675 676 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp); 677 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid); 678 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp); 679 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid); 680 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch); 681 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline); 682 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl); 683 684 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par); 685 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par); 686 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par); 687 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par); 688 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par); 689 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par); 690 691 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par); 692#if 0 693 FIXME 694 if (par->accel_flags & FB_ACCELF_TEXT) 695 aty_init_engine(par, info); 696#endif 697#ifdef CONFIG_FB_ATY_GENERIC_LCD 698 /* after setting the CRTC registers we should set the LCD registers. */ 699 if (par->lcd_table != 0) { 700 /* switch to shadow registers */ 701 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) | 702 (SHADOW_EN | SHADOW_RW_EN), par); 703 704 DPRINTK("set shadow CRT to %ix%i %c%c\n", 705 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1), 706 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P'); 707 708 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp); 709 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid); 710 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp); 711 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid); 712 713 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par); 714 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par); 715 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par); 716 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par); 717 718 /* restore CRTC selection & shadow state and enable stretching */ 719 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl); 720 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching); 721 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching); 722 if(!M64_HAS(LT_LCD_REGS)) 723 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch); 724 725 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par); 726 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par); 727 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par); 728 if(!M64_HAS(LT_LCD_REGS)) { 729 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par); 730 aty_ld_le32(LCD_INDEX, par); 731 aty_st_le32(LCD_INDEX, crtc->lcd_index, par); 732 } 733 } 734#endif /* CONFIG_FB_ATY_GENERIC_LCD */ 735} 736 737static int aty_var_to_crtc(const struct fb_info *info, 738 const struct fb_var_screeninfo *var, struct crtc *crtc) 739{ 740 struct atyfb_par *par = (struct atyfb_par *) info->par; 741 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp; 742 u32 sync, vmode, vdisplay; 743 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol; 744 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync; 745 u32 pix_width, dp_pix_width, dp_chain_mask; 746 747 /* input */ 748 xres = var->xres; 749 yres = var->yres; 750 vxres = var->xres_virtual; 751 vyres = var->yres_virtual; 752 xoffset = var->xoffset; 753 yoffset = var->yoffset; 754 bpp = var->bits_per_pixel; 755 if (bpp == 16) 756 bpp = (var->green.length == 5) ? 15 : 16; 757 sync = var->sync; 758 vmode = var->vmode; 759 760 /* convert (and round up) and validate */ 761 if (vxres < xres + xoffset) 762 vxres = xres + xoffset; 763 h_disp = xres; 764 765 if (vyres < yres + yoffset) 766 vyres = yres + yoffset; 767 v_disp = yres; 768 769 if (bpp <= 8) { 770 bpp = 8; 771 pix_width = CRTC_PIX_WIDTH_8BPP; 772 dp_pix_width = 773 HOST_8BPP | SRC_8BPP | DST_8BPP | 774 BYTE_ORDER_LSB_TO_MSB; 775 dp_chain_mask = DP_CHAIN_8BPP; 776 } else if (bpp <= 15) { 777 bpp = 16; 778 pix_width = CRTC_PIX_WIDTH_15BPP; 779 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP | 780 BYTE_ORDER_LSB_TO_MSB; 781 dp_chain_mask = DP_CHAIN_15BPP; 782 } else if (bpp <= 16) { 783 bpp = 16; 784 pix_width = CRTC_PIX_WIDTH_16BPP; 785 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP | 786 BYTE_ORDER_LSB_TO_MSB; 787 dp_chain_mask = DP_CHAIN_16BPP; 788 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) { 789 bpp = 24; 790 pix_width = CRTC_PIX_WIDTH_24BPP; 791 dp_pix_width = 792 HOST_8BPP | SRC_8BPP | DST_8BPP | 793 BYTE_ORDER_LSB_TO_MSB; 794 dp_chain_mask = DP_CHAIN_24BPP; 795 } else if (bpp <= 32) { 796 bpp = 32; 797 pix_width = CRTC_PIX_WIDTH_32BPP; 798 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP | 799 BYTE_ORDER_LSB_TO_MSB; 800 dp_chain_mask = DP_CHAIN_32BPP; 801 } else 802 FAIL("invalid bpp"); 803 804 if (vxres * vyres * bpp / 8 > info->fix.smem_len) 805 FAIL("not enough video RAM"); 806 807 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 808 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 809 810 if((xres > 1600) || (yres > 1200)) { 811 FAIL("MACH64 chips are designed for max 1600x1200\n" 812 "select anoter resolution."); 813 } 814 h_sync_strt = h_disp + var->right_margin; 815 h_sync_end = h_sync_strt + var->hsync_len; 816 h_sync_dly = var->right_margin & 7; 817 h_total = h_sync_end + h_sync_dly + var->left_margin; 818 819 v_sync_strt = v_disp + var->lower_margin; 820 v_sync_end = v_sync_strt + var->vsync_len; 821 v_total = v_sync_end + var->upper_margin; 822 823#ifdef CONFIG_FB_ATY_GENERIC_LCD 824 if (par->lcd_table != 0) { 825 if(!M64_HAS(LT_LCD_REGS)) { 826 u32 lcd_index = aty_ld_le32(LCD_INDEX, par); 827 crtc->lcd_index = lcd_index & 828 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS); 829 aty_st_le32(LCD_INDEX, lcd_index, par); 830 } 831 832 if (!M64_HAS(MOBIL_BUS)) 833 crtc->lcd_index |= CRTC2_DISPLAY_DIS; 834 835 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000; 836 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT; 837 838 crtc->lcd_gen_cntl &= 839 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN | 840 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/ 841 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN); 842 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT; 843 844 if((crtc->lcd_gen_cntl & LCD_ON) && 845 ((xres > par->lcd_width) || (yres > par->lcd_height))) { 846 /* We cannot display the mode on the LCD. If the CRT is enabled 847 we can turn off the LCD. 848 If the CRT is off, it isn't a good idea to switch it on; we don't 849 know if one is connected. So it's better to fail then. 850 */ 851 if (crtc->lcd_gen_cntl & CRT_ON) { 852 if (!(var->activate & FB_ACTIVATE_TEST)) 853 PRINTKI("Disable LCD panel, because video mode does not fit.\n"); 854 crtc->lcd_gen_cntl &= ~LCD_ON; 855 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/ 856 } else { 857 if (!(var->activate & FB_ACTIVATE_TEST)) 858 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n"); 859 return -EINVAL; 860 } 861 } 862 } 863 864 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) { 865 int VScan = 1; 866 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5 867 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 }; 868 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */ 869 870 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED); 871 872 /* This is horror! When we simulate, say 640x480 on an 800x600 873 LCD monitor, the CRTC should be programmed 800x600 values for 874 the non visible part, but 640x480 for the visible part. 875 This code has been tested on a laptop with it's 1400x1050 LCD 876 monitor and a conventional monitor both switched on. 877 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600, 878 works with little glitches also with DOUBLESCAN modes 879 */ 880 if (yres < par->lcd_height) { 881 VScan = par->lcd_height / yres; 882 if(VScan > 1) { 883 VScan = 2; 884 vmode |= FB_VMODE_DOUBLE; 885 } 886 } 887 888 h_sync_strt = h_disp + par->lcd_right_margin; 889 h_sync_end = h_sync_strt + par->lcd_hsync_len; 890 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly; 891 h_total = h_disp + par->lcd_hblank_len; 892 893 v_sync_strt = v_disp + par->lcd_lower_margin / VScan; 894 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan; 895 v_total = v_disp + par->lcd_vblank_len / VScan; 896 } 897#endif /* CONFIG_FB_ATY_GENERIC_LCD */ 898 899 h_disp = (h_disp >> 3) - 1; 900 h_sync_strt = (h_sync_strt >> 3) - 1; 901 h_sync_end = (h_sync_end >> 3) - 1; 902 h_total = (h_total >> 3) - 1; 903 h_sync_wid = h_sync_end - h_sync_strt; 904 905 FAIL_MAX("h_disp too large", h_disp, 0xff); 906 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff); 907 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/ 908 if(h_sync_wid > 0x1f) 909 h_sync_wid = 0x1f; 910 FAIL_MAX("h_total too large", h_total, 0x1ff); 911 912 if (vmode & FB_VMODE_DOUBLE) { 913 v_disp <<= 1; 914 v_sync_strt <<= 1; 915 v_sync_end <<= 1; 916 v_total <<= 1; 917 } 918 919 vdisplay = yres; 920#ifdef CONFIG_FB_ATY_GENERIC_LCD 921 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) 922 vdisplay = par->lcd_height; 923#endif 924 925 v_disp--; 926 v_sync_strt--; 927 v_sync_end--; 928 v_total--; 929 v_sync_wid = v_sync_end - v_sync_strt; 930 931 FAIL_MAX("v_disp too large", v_disp, 0x7ff); 932 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff); 933 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/ 934 if(v_sync_wid > 0x1f) 935 v_sync_wid = 0x1f; 936 FAIL_MAX("v_total too large", v_total, 0x7ff); 937 938 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0; 939 940 /* output */ 941 crtc->vxres = vxres; 942 crtc->vyres = vyres; 943 crtc->xoffset = xoffset; 944 crtc->yoffset = yoffset; 945 crtc->bpp = bpp; 946 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19); 947 crtc->vline_crnt_vline = 0; 948 949 crtc->h_tot_disp = h_total | (h_disp<<16); 950 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) | 951 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21); 952 crtc->v_tot_disp = v_total | (v_disp<<16); 953 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21); 954 955 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */ 956 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync; 957 crtc->gen_cntl |= CRTC_VGA_LINEAR; 958 959 /* Enable doublescan mode if requested */ 960 if (vmode & FB_VMODE_DOUBLE) 961 crtc->gen_cntl |= CRTC_DBL_SCAN_EN; 962 /* Enable interlaced mode if requested */ 963 if (vmode & FB_VMODE_INTERLACED) 964 crtc->gen_cntl |= CRTC_INTERLACE_EN; 965#ifdef CONFIG_FB_ATY_GENERIC_LCD 966 if (par->lcd_table != 0) { 967 vdisplay = yres; 968 if(vmode & FB_VMODE_DOUBLE) 969 vdisplay <<= 1; 970 if(vmode & FB_VMODE_INTERLACED) { 971 vdisplay >>= 1; 972 973 /* The prefered mode for the LCD is not interlaced, so disable it if 974 it was enabled. For doublescan there is no problem, because we can 975 compensate for it in the hardware stretching (we stretch half as much) 976 */ 977 vmode &= ~FB_VMODE_INTERLACED; 978 /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/ 979 } 980 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH); 981 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | 982 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/ 983 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN); 984 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/); 985 986 /* MOBILITY M1 tested, FIXME: LT */ 987 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par); 988 if (!M64_HAS(LT_LCD_REGS)) 989 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) & 990 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3); 991 992 crtc->horz_stretching &= 993 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO | 994 HORZ_STRETCH_MODE | HORZ_STRETCH_EN); 995 if (xres < par->lcd_width) { 996 do { 997 /* 998 * The horizontal blender misbehaves when HDisplay is less than a 999 * a certain threshold (440 for a 1024-wide panel). It doesn't 1000 * stretch such modes enough. Use pixel replication instead of 1001 * blending to stretch modes that can be made to exactly fit the 1002 * panel width. The undocumented "NoLCDBlend" option allows the 1003 * pixel-replicated mode to be slightly wider or narrower than the 1004 * panel width. It also causes a mode that is exactly half as wide 1005 * as the panel to be pixel-replicated, rather than blended. 1006 */ 1007 int HDisplay = xres & ~7; 1008 int nStretch = par->lcd_width / HDisplay; 1009 int Remainder = par->lcd_width % HDisplay; 1010 1011 if ((!Remainder && ((nStretch > 2))) || 1012 (((HDisplay * 16) / par->lcd_width) < 7)) { 1013 static const char StretchLoops[] = {10, 12, 13, 15, 16}; 1014 int horz_stretch_loop = -1, BestRemainder; 1015 int Numerator = HDisplay, Denominator = par->lcd_width; 1016 int Index = 5; 1017 ATIReduceRatio(&Numerator, &Denominator); 1018 1019 BestRemainder = (Numerator * 16) / Denominator; 1020 while (--Index >= 0) { 1021 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) % 1022 Denominator; 1023 if (Remainder < BestRemainder) { 1024 horz_stretch_loop = Index; 1025 if (!(BestRemainder = Remainder)) 1026 break; 1027 } 1028 } 1029 1030 if ((horz_stretch_loop >= 0) && !BestRemainder) { 1031 int horz_stretch_ratio = 0, Accumulator = 0; 1032 int reuse_previous = 1; 1033 1034 Index = StretchLoops[horz_stretch_loop]; 1035 1036 while (--Index >= 0) { 1037 if (Accumulator > 0) 1038 horz_stretch_ratio |= reuse_previous; 1039 else 1040 Accumulator += Denominator; 1041 Accumulator -= Numerator; 1042 reuse_previous <<= 1; 1043 } 1044 1045 crtc->horz_stretching |= (HORZ_STRETCH_EN | 1046 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) | 1047 (horz_stretch_ratio & HORZ_STRETCH_RATIO)); 1048 break; /* Out of the do { ... } while (0) */ 1049 } 1050 } 1051 1052 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN | 1053 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND)); 1054 } while (0); 1055 } 1056 1057 if (vdisplay < par->lcd_height) { 1058 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN | 1059 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0)); 1060 1061 if (!M64_HAS(LT_LCD_REGS) && 1062 xres <= (M64_HAS(MOBIL_BUS)?1024:800)) 1063 crtc->ext_vert_stretch |= VERT_STRETCH_MODE; 1064 } else { 1065 /* 1066 * Don't use vertical blending if the mode is too wide or not 1067 * vertically stretched. 1068 */ 1069 crtc->vert_stretching = 0; 1070 } 1071 /* copy to shadow crtc */ 1072 crtc->shadow_h_tot_disp = crtc->h_tot_disp; 1073 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid; 1074 crtc->shadow_v_tot_disp = crtc->v_tot_disp; 1075 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid; 1076 } 1077#endif /* CONFIG_FB_ATY_GENERIC_LCD */ 1078 1079 if (M64_HAS(MAGIC_FIFO)) { 1080 /* FIXME: display FIFO low watermark values */ 1081 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM); 1082 } 1083 crtc->dp_pix_width = dp_pix_width; 1084 crtc->dp_chain_mask = dp_chain_mask; 1085 1086 return 0; 1087} 1088 1089static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var) 1090{ 1091 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync; 1092 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, 1093 h_sync_pol; 1094 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1095 u32 pix_width; 1096 u32 double_scan, interlace; 1097 1098 /* input */ 1099 h_total = crtc->h_tot_disp & 0x1ff; 1100 h_disp = (crtc->h_tot_disp >> 16) & 0xff; 1101 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100); 1102 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7; 1103 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f; 1104 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1; 1105 v_total = crtc->v_tot_disp & 0x7ff; 1106 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff; 1107 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1108 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1109 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1; 1110 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1111 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1112 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN; 1113 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN; 1114 1115 /* convert */ 1116 xres = (h_disp + 1) * 8; 1117 yres = v_disp + 1; 1118 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly; 1119 right = (h_sync_strt - h_disp) * 8 + h_sync_dly; 1120 hslen = h_sync_wid * 8; 1121 upper = v_total - v_sync_strt - v_sync_wid; 1122 lower = v_sync_strt - v_disp; 1123 vslen = v_sync_wid; 1124 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1125 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1126 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1127 1128 switch (pix_width) { 1129#if 0 1130 case CRTC_PIX_WIDTH_4BPP: 1131 bpp = 4; 1132 var->red.offset = 0; 1133 var->red.length = 8; 1134 var->green.offset = 0; 1135 var->green.length = 8; 1136 var->blue.offset = 0; 1137 var->blue.length = 8; 1138 var->transp.offset = 0; 1139 var->transp.length = 0; 1140 break; 1141#endif 1142 case CRTC_PIX_WIDTH_8BPP: 1143 bpp = 8; 1144 var->red.offset = 0; 1145 var->red.length = 8; 1146 var->green.offset = 0; 1147 var->green.length = 8; 1148 var->blue.offset = 0; 1149 var->blue.length = 8; 1150 var->transp.offset = 0; 1151 var->transp.length = 0; 1152 break; 1153 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */ 1154 bpp = 16; 1155 var->red.offset = 10; 1156 var->red.length = 5; 1157 var->green.offset = 5; 1158 var->green.length = 5; 1159 var->blue.offset = 0; 1160 var->blue.length = 5; 1161 var->transp.offset = 0; 1162 var->transp.length = 0; 1163 break; 1164 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */ 1165 bpp = 16; 1166 var->red.offset = 11; 1167 var->red.length = 5; 1168 var->green.offset = 5; 1169 var->green.length = 6; 1170 var->blue.offset = 0; 1171 var->blue.length = 5; 1172 var->transp.offset = 0; 1173 var->transp.length = 0; 1174 break; 1175 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */ 1176 bpp = 24; 1177 var->red.offset = 16; 1178 var->red.length = 8; 1179 var->green.offset = 8; 1180 var->green.length = 8; 1181 var->blue.offset = 0; 1182 var->blue.length = 8; 1183 var->transp.offset = 0; 1184 var->transp.length = 0; 1185 break; 1186 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */ 1187 bpp = 32; 1188 var->red.offset = 16; 1189 var->red.length = 8; 1190 var->green.offset = 8; 1191 var->green.length = 8; 1192 var->blue.offset = 0; 1193 var->blue.length = 8; 1194 var->transp.offset = 24; 1195 var->transp.length = 8; 1196 break; 1197 default: 1198 PRINTKE("Invalid pixel width\n"); 1199 return -EINVAL; 1200 } 1201 1202 /* output */ 1203 var->xres = xres; 1204 var->yres = yres; 1205 var->xres_virtual = crtc->vxres; 1206 var->yres_virtual = crtc->vyres; 1207 var->bits_per_pixel = bpp; 1208 var->left_margin = left; 1209 var->right_margin = right; 1210 var->upper_margin = upper; 1211 var->lower_margin = lower; 1212 var->hsync_len = hslen; 1213 var->vsync_len = vslen; 1214 var->sync = sync; 1215 var->vmode = FB_VMODE_NONINTERLACED; 1216 /* In double scan mode, the vertical parameters are doubled, so we need to 1217 half them to get the right values. 1218 In interlaced mode the values are already correct, so no correction is 1219 necessary. 1220 */ 1221 if (interlace) 1222 var->vmode = FB_VMODE_INTERLACED; 1223 1224 if (double_scan) { 1225 var->vmode = FB_VMODE_DOUBLE; 1226 var->yres>>=1; 1227 var->upper_margin>>=1; 1228 var->lower_margin>>=1; 1229 var->vsync_len>>=1; 1230 } 1231 1232 return 0; 1233} 1234 1235/* ------------------------------------------------------------------------- */ 1236 1237static int atyfb_set_par(struct fb_info *info) 1238{ 1239 struct atyfb_par *par = (struct atyfb_par *) info->par; 1240 struct fb_var_screeninfo *var = &info->var; 1241 u32 tmp, pixclock; 1242 int err; 1243#ifdef DEBUG 1244 struct fb_var_screeninfo debug; 1245 u32 pixclock_in_ps; 1246#endif 1247 if (par->asleep) 1248 return 0; 1249 1250 if ((err = aty_var_to_crtc(info, var, &par->crtc))) 1251 return err; 1252 1253 pixclock = atyfb_get_pixclock(var, par); 1254 1255 if (pixclock == 0) { 1256 PRINTKE("Invalid pixclock\n"); 1257 return -EINVAL; 1258 } else { 1259 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll))) 1260 return err; 1261 } 1262 1263 par->accel_flags = var->accel_flags; /* hack */ 1264 1265 if (par->blitter_may_be_busy) 1266 wait_for_idle(par); 1267 1268 aty_set_crtc(par, &par->crtc); 1269 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags); 1270 par->pll_ops->set_pll(info, &par->pll); 1271 1272#ifdef DEBUG 1273 if(par->pll_ops && par->pll_ops->pll_to_var) 1274 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll)); 1275 else 1276 pixclock_in_ps = 0; 1277 1278 if(0 == pixclock_in_ps) { 1279 PRINTKE("ALERT ops->pll_to_var get 0\n"); 1280 pixclock_in_ps = pixclock; 1281 } 1282 1283 memset(&debug, 0, sizeof(debug)); 1284 if(!aty_crtc_to_var(&(par->crtc), &debug)) { 1285 u32 hSync, vRefresh; 1286 u32 h_disp, h_sync_strt, h_sync_end, h_total; 1287 u32 v_disp, v_sync_strt, v_sync_end, v_total; 1288 1289 h_disp = debug.xres; 1290 h_sync_strt = h_disp + debug.right_margin; 1291 h_sync_end = h_sync_strt + debug.hsync_len; 1292 h_total = h_sync_end + debug.left_margin; 1293 v_disp = debug.yres; 1294 v_sync_strt = v_disp + debug.lower_margin; 1295 v_sync_end = v_sync_strt + debug.vsync_len; 1296 v_total = v_sync_end + debug.upper_margin; 1297 1298 hSync = 1000000000 / (pixclock_in_ps * h_total); 1299 vRefresh = (hSync * 1000) / v_total; 1300 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN) 1301 vRefresh *= 2; 1302 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN) 1303 vRefresh /= 2; 1304 1305 DPRINTK("atyfb_set_par\n"); 1306 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel); 1307 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n", 1308 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps); 1309 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps); 1310 DPRINTK(" Horizontal sync: %i kHz\n", hSync); 1311 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh); 1312 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n", 1313 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps, 1314 h_disp, h_sync_strt, h_sync_end, h_total, 1315 v_disp, v_sync_strt, v_sync_end, v_total); 1316 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n", 1317 pixclock_in_ps, 1318 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len, 1319 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len); 1320 } 1321#endif /* DEBUG */ 1322 1323 if (!M64_HAS(INTEGRATED)) { 1324 /* Don't forget MEM_CNTL */ 1325 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff; 1326 switch (var->bits_per_pixel) { 1327 case 8: 1328 tmp |= 0x02000000; 1329 break; 1330 case 16: 1331 tmp |= 0x03000000; 1332 break; 1333 case 32: 1334 tmp |= 0x06000000; 1335 break; 1336 } 1337 aty_st_le32(MEM_CNTL, tmp, par); 1338 } else { 1339 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff; 1340 if (!M64_HAS(MAGIC_POSTDIV)) 1341 tmp |= par->mem_refresh_rate << 20; 1342 switch (var->bits_per_pixel) { 1343 case 8: 1344 case 24: 1345 tmp |= 0x00000000; 1346 break; 1347 case 16: 1348 tmp |= 0x04000000; 1349 break; 1350 case 32: 1351 tmp |= 0x08000000; 1352 break; 1353 } 1354 if (M64_HAS(CT_BUS)) { 1355 aty_st_le32(DAC_CNTL, 0x87010184, par); 1356 aty_st_le32(BUS_CNTL, 0x680000f9, par); 1357 } else if (M64_HAS(VT_BUS)) { 1358 aty_st_le32(DAC_CNTL, 0x87010184, par); 1359 aty_st_le32(BUS_CNTL, 0x680000f9, par); 1360 } else if (M64_HAS(MOBIL_BUS)) { 1361 aty_st_le32(DAC_CNTL, 0x80010102, par); 1362 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par); 1363 } else { 1364 /* GT */ 1365 aty_st_le32(DAC_CNTL, 0x86010102, par); 1366 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par); 1367 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par); 1368 } 1369 aty_st_le32(MEM_CNTL, tmp, par); 1370 } 1371 aty_st_8(DAC_MASK, 0xff, par); 1372 1373 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8; 1374 info->fix.visual = var->bits_per_pixel <= 8 ? 1375 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1376 1377 /* Initialize the graphics engine */ 1378 if (par->accel_flags & FB_ACCELF_TEXT) 1379 aty_init_engine(par, info); 1380 1381#ifdef CONFIG_BOOTX_TEXT 1382 btext_update_display(info->fix.smem_start, 1383 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8, 1384 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1, 1385 var->bits_per_pixel, 1386 par->crtc.vxres * var->bits_per_pixel / 8); 1387#endif /* CONFIG_BOOTX_TEXT */ 1388#if 0 1389 /* switch to accelerator mode */ 1390 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN)) 1391 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par); 1392#endif 1393#ifdef DEBUG 1394{ 1395 /* dump non shadow CRTC, pll, LCD registers */ 1396 int i; u32 base; 1397 1398 /* CRTC registers */ 1399 base = 0x2000; 1400 printk("debug atyfb: Mach64 non-shadow register values:"); 1401 for (i = 0; i < 256; i = i+4) { 1402 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i); 1403 printk(" %08X", aty_ld_le32(i, par)); 1404 } 1405 printk("\n\n"); 1406 1407#ifdef CONFIG_FB_ATY_CT 1408 /* PLL registers */ 1409 base = 0x00; 1410 printk("debug atyfb: Mach64 PLL register values:"); 1411 for (i = 0; i < 64; i++) { 1412 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i); 1413 if(i%4 == 0) printk(" "); 1414 printk("%02X", aty_ld_pll_ct(i, par)); 1415 } 1416 printk("\n\n"); 1417#endif /* CONFIG_FB_ATY_CT */ 1418 1419#ifdef CONFIG_FB_ATY_GENERIC_LCD 1420 if (par->lcd_table != 0) { 1421 /* LCD registers */ 1422 base = 0x00; 1423 printk("debug atyfb: LCD register values:"); 1424 if(M64_HAS(LT_LCD_REGS)) { 1425 for(i = 0; i <= POWER_MANAGEMENT; i++) { 1426 if(i == EXT_VERT_STRETCH) 1427 continue; 1428 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]); 1429 printk(" %08X", aty_ld_lcd(i, par)); 1430 } 1431 1432 } else { 1433 for (i = 0; i < 64; i++) { 1434 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i); 1435 printk(" %08X", aty_ld_lcd(i, par)); 1436 } 1437 } 1438 printk("\n\n"); 1439 } 1440#endif /* CONFIG_FB_ATY_GENERIC_LCD */ 1441} 1442#endif /* DEBUG */ 1443 return 0; 1444} 1445 1446static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1447{ 1448 struct atyfb_par *par = (struct atyfb_par *) info->par; 1449 int err; 1450 struct crtc crtc; 1451 union aty_pll pll; 1452 u32 pixclock; 1453 1454 memcpy(&pll, &(par->pll), sizeof(pll)); 1455 1456 if((err = aty_var_to_crtc(info, var, &crtc))) 1457 return err; 1458 1459 pixclock = atyfb_get_pixclock(var, par); 1460 1461 if (pixclock == 0) { 1462 if (!(var->activate & FB_ACTIVATE_TEST)) 1463 PRINTKE("Invalid pixclock\n"); 1464 return -EINVAL; 1465 } else { 1466 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll))) 1467 return err; 1468 } 1469 1470 if (var->accel_flags & FB_ACCELF_TEXT) 1471 info->var.accel_flags = FB_ACCELF_TEXT; 1472 else 1473 info->var.accel_flags = 0; 1474 1475#if 0 /* fbmon is not done. uncomment for 2.5.x -brad */ 1476 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info)) 1477 return -EINVAL; 1478#endif 1479 aty_crtc_to_var(&crtc, var); 1480 var->pixclock = par->pll_ops->pll_to_var(info, &pll); 1481 return 0; 1482} 1483 1484static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info) 1485{ 1486 u32 xoffset = info->var.xoffset; 1487 u32 yoffset = info->var.yoffset; 1488 u32 vxres = par->crtc.vxres; 1489 u32 bpp = info->var.bits_per_pixel; 1490 1491 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19); 1492} 1493 1494 1495 /* 1496 * Open/Release the frame buffer device 1497 */ 1498 1499static int atyfb_open(struct fb_info *info, int user) 1500{ 1501 struct atyfb_par *par = (struct atyfb_par *) info->par; 1502 1503 if (user) { 1504 par->open++; 1505#ifdef __sparc__ 1506 par->mmaped = 0; 1507#endif 1508 } 1509 return (0); 1510} 1511 1512static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp) 1513{ 1514 struct atyfb_par *par = dev_id; 1515 int handled = 0; 1516 u32 int_cntl; 1517 1518 spin_lock(&par->int_lock); 1519 1520 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par); 1521 1522 if (int_cntl & CRTC_VBLANK_INT) { 1523 /* clear interrupt */ 1524 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par); 1525 par->vblank.count++; 1526 if (par->vblank.pan_display) { 1527 par->vblank.pan_display = 0; 1528 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par); 1529 } 1530 wake_up_interruptible(&par->vblank.wait); 1531 handled = 1; 1532 } 1533 1534 spin_unlock(&par->int_lock); 1535 1536 return IRQ_RETVAL(handled); 1537} 1538 1539static int aty_enable_irq(struct atyfb_par *par, int reenable) 1540{ 1541 u32 int_cntl; 1542 1543 if (!test_and_set_bit(0, &par->irq_flags)) { 1544 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) { 1545 clear_bit(0, &par->irq_flags); 1546 return -EINVAL; 1547 } 1548 spin_lock_irq(&par->int_lock); 1549 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK; 1550 /* clear interrupt */ 1551 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par); 1552 /* enable interrupt */ 1553 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par); 1554 spin_unlock_irq(&par->int_lock); 1555 } else if (reenable) { 1556 spin_lock_irq(&par->int_lock); 1557 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK; 1558 if (!(int_cntl & CRTC_VBLANK_INT_EN)) { 1559 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl); 1560 /* re-enable interrupt */ 1561 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par ); 1562 } 1563 spin_unlock_irq(&par->int_lock); 1564 } 1565 1566 return 0; 1567} 1568 1569static int aty_disable_irq(struct atyfb_par *par) 1570{ 1571 u32 int_cntl; 1572 1573 if (test_and_clear_bit(0, &par->irq_flags)) { 1574 if (par->vblank.pan_display) { 1575 par->vblank.pan_display = 0; 1576 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par); 1577 } 1578 spin_lock_irq(&par->int_lock); 1579 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK; 1580 /* disable interrupt */ 1581 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par ); 1582 spin_unlock_irq(&par->int_lock); 1583 free_irq(par->irq, par); 1584 } 1585 1586 return 0; 1587} 1588 1589static int atyfb_release(struct fb_info *info, int user) 1590{ 1591 struct atyfb_par *par = (struct atyfb_par *) info->par; 1592 if (user) { 1593 par->open--; 1594 mdelay(1); 1595 wait_for_idle(par); 1596 if (!par->open) { 1597#ifdef __sparc__ 1598 int was_mmaped = par->mmaped; 1599 1600 par->mmaped = 0; 1601 1602 if (was_mmaped) { 1603 struct fb_var_screeninfo var; 1604 1605 /* Now reset the default display config, we have no 1606 * idea what the program(s) which mmap'd the chip did 1607 * to the configuration, nor whether it restored it 1608 * correctly. 1609 */ 1610 var = default_var; 1611 if (noaccel) 1612 var.accel_flags &= ~FB_ACCELF_TEXT; 1613 else 1614 var.accel_flags |= FB_ACCELF_TEXT; 1615 if (var.yres == var.yres_virtual) { 1616 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2)); 1617 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual; 1618 if (var.yres_virtual < var.yres) 1619 var.yres_virtual = var.yres; 1620 } 1621 } 1622#endif 1623 aty_disable_irq(par); 1624 } 1625 } 1626 return (0); 1627} 1628 1629 /* 1630 * Pan or Wrap the Display 1631 * 1632 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1633 */ 1634 1635static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 1636{ 1637 struct atyfb_par *par = (struct atyfb_par *) info->par; 1638 u32 xres, yres, xoffset, yoffset; 1639 1640 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8; 1641 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1; 1642 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN) 1643 yres >>= 1; 1644 xoffset = (var->xoffset + 7) & ~7; 1645 yoffset = var->yoffset; 1646 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres) 1647 return -EINVAL; 1648 info->var.xoffset = xoffset; 1649 info->var.yoffset = yoffset; 1650 if (par->asleep) 1651 return 0; 1652 1653 set_off_pitch(par, info); 1654 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) { 1655 par->vblank.pan_display = 1; 1656 } else { 1657 par->vblank.pan_display = 0; 1658 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par); 1659 } 1660 1661 return 0; 1662} 1663 1664static int aty_waitforvblank(struct atyfb_par *par, u32 crtc) 1665{ 1666 struct aty_interrupt *vbl; 1667 unsigned int count; 1668 int ret; 1669 1670 switch (crtc) { 1671 case 0: 1672 vbl = &par->vblank; 1673 break; 1674 default: 1675 return -ENODEV; 1676 } 1677 1678 ret = aty_enable_irq(par, 0); 1679 if (ret) 1680 return ret; 1681 1682 count = vbl->count; 1683 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10); 1684 if (ret < 0) { 1685 return ret; 1686 } 1687 if (ret == 0) { 1688 aty_enable_irq(par, 1); 1689 return -ETIMEDOUT; 1690 } 1691 1692 return 0; 1693} 1694 1695 1696#ifdef DEBUG 1697#define ATYIO_CLKR 0x41545900 /* ATY\00 */ 1698#define ATYIO_CLKW 0x41545901 /* ATY\01 */ 1699 1700struct atyclk { 1701 u32 ref_clk_per; 1702 u8 pll_ref_div; 1703 u8 mclk_fb_div; 1704 u8 mclk_post_div; /* 1,2,3,4,8 */ 1705 u8 mclk_fb_mult; /* 2 or 4 */ 1706 u8 xclk_post_div; /* 1,2,3,4,8 */ 1707 u8 vclk_fb_div; 1708 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */ 1709 u32 dsp_xclks_per_row; /* 0-16383 */ 1710 u32 dsp_loop_latency; /* 0-15 */ 1711 u32 dsp_precision; /* 0-7 */ 1712 u32 dsp_on; /* 0-2047 */ 1713 u32 dsp_off; /* 0-2047 */ 1714}; 1715 1716#define ATYIO_FEATR 0x41545902 /* ATY\02 */ 1717#define ATYIO_FEATW 0x41545903 /* ATY\03 */ 1718#endif 1719 1720#ifndef FBIO_WAITFORVSYNC 1721#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) 1722#endif 1723 1724static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd, 1725 u_long arg, struct fb_info *info) 1726{ 1727 struct atyfb_par *par = (struct atyfb_par *) info->par; 1728#ifdef __sparc__ 1729 struct fbtype fbtyp; 1730#endif 1731 1732 switch (cmd) { 1733#ifdef __sparc__ 1734 case FBIOGTYPE: 1735 fbtyp.fb_type = FBTYPE_PCI_GENERIC; 1736 fbtyp.fb_width = par->crtc.vxres; 1737 fbtyp.fb_height = par->crtc.vyres; 1738 fbtyp.fb_depth = info->var.bits_per_pixel; 1739 fbtyp.fb_cmsize = info->cmap.len; 1740 fbtyp.fb_size = info->fix.smem_len; 1741 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp))) 1742 return -EFAULT; 1743 break; 1744#endif /* __sparc__ */ 1745 1746 case FBIO_WAITFORVSYNC: 1747 { 1748 u32 crtc; 1749 1750 if (get_user(crtc, (__u32 __user *) arg)) 1751 return -EFAULT; 1752 1753 return aty_waitforvblank(par, crtc); 1754 } 1755 break; 1756 1757#if defined(DEBUG) && defined(CONFIG_FB_ATY_CT) 1758 case ATYIO_CLKR: 1759 if (M64_HAS(INTEGRATED)) { 1760 struct atyclk clk; 1761 union aty_pll *pll = &(par->pll); 1762 u32 dsp_config = pll->ct.dsp_config; 1763 u32 dsp_on_off = pll->ct.dsp_on_off; 1764 clk.ref_clk_per = par->ref_clk_per; 1765 clk.pll_ref_div = pll->ct.pll_ref_div; 1766 clk.mclk_fb_div = pll->ct.mclk_fb_div; 1767 clk.mclk_post_div = pll->ct.mclk_post_div_real; 1768 clk.mclk_fb_mult = pll->ct.mclk_fb_mult; 1769 clk.xclk_post_div = pll->ct.xclk_post_div_real; 1770 clk.vclk_fb_div = pll->ct.vclk_fb_div; 1771 clk.vclk_post_div = pll->ct.vclk_post_div_real; 1772 clk.dsp_xclks_per_row = dsp_config & 0x3fff; 1773 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf; 1774 clk.dsp_precision = (dsp_config >> 20) & 7; 1775 clk.dsp_off = dsp_on_off & 0x7ff; 1776 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff; 1777 if (copy_to_user((struct atyclk __user *) arg, &clk, 1778 sizeof(clk))) 1779 return -EFAULT; 1780 } else 1781 return -EINVAL; 1782 break; 1783 case ATYIO_CLKW: 1784 if (M64_HAS(INTEGRATED)) { 1785 struct atyclk clk; 1786 union aty_pll *pll = &(par->pll); 1787 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk))) 1788 return -EFAULT; 1789 par->ref_clk_per = clk.ref_clk_per; 1790 pll->ct.pll_ref_div = clk.pll_ref_div; 1791 pll->ct.mclk_fb_div = clk.mclk_fb_div; 1792 pll->ct.mclk_post_div_real = clk.mclk_post_div; 1793 pll->ct.mclk_fb_mult = clk.mclk_fb_mult; 1794 pll->ct.xclk_post_div_real = clk.xclk_post_div; 1795 pll->ct.vclk_fb_div = clk.vclk_fb_div; 1796 pll->ct.vclk_post_div_real = clk.vclk_post_div; 1797 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) | 1798 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20); 1799 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16); 1800 /*aty_calc_pll_ct(info, &pll->ct);*/ 1801 aty_set_pll_ct(info, pll); 1802 } else 1803 return -EINVAL; 1804 break; 1805 case ATYIO_FEATR: 1806 if (get_user(par->features, (u32 __user *) arg)) 1807 return -EFAULT; 1808 break; 1809 case ATYIO_FEATW: 1810 if (put_user(par->features, (u32 __user *) arg)) 1811 return -EFAULT; 1812 break; 1813#endif /* DEBUG && CONFIG_FB_ATY_CT */ 1814 default: 1815 return -EINVAL; 1816 } 1817 return 0; 1818} 1819 1820static int atyfb_sync(struct fb_info *info) 1821{ 1822 struct atyfb_par *par = (struct atyfb_par *) info->par; 1823 1824 if (par->blitter_may_be_busy) 1825 wait_for_idle(par); 1826 return 0; 1827} 1828 1829#ifdef __sparc__ 1830static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma) 1831{ 1832 struct atyfb_par *par = (struct atyfb_par *) info->par; 1833 unsigned int size, page, map_size = 0; 1834 unsigned long map_offset = 0; 1835 unsigned long off; 1836 int i; 1837 1838 if (!par->mmap_map) 1839 return -ENXIO; 1840 1841 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) 1842 return -EINVAL; 1843 1844 off = vma->vm_pgoff << PAGE_SHIFT; 1845 size = vma->vm_end - vma->vm_start; 1846 1847 /* To stop the swapper from even considering these pages. */ 1848 vma->vm_flags |= (VM_IO | VM_RESERVED); 1849 1850 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) || 1851 ((off == info->fix.smem_len) && (size == PAGE_SIZE))) 1852 off += 0x8000000000000000UL; 1853 1854 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */ 1855 1856 /* Each page, see which map applies */ 1857 for (page = 0; page < size;) { 1858 map_size = 0; 1859 for (i = 0; par->mmap_map[i].size; i++) { 1860 unsigned long start = par->mmap_map[i].voff; 1861 unsigned long end = start + par->mmap_map[i].size; 1862 unsigned long offset = off + page; 1863 1864 if (start > offset) 1865 continue; 1866 if (offset >= end) 1867 continue; 1868 1869 map_size = par->mmap_map[i].size - (offset - start); 1870 map_offset = 1871 par->mmap_map[i].poff + (offset - start); 1872 break; 1873 } 1874 if (!map_size) { 1875 page += PAGE_SIZE; 1876 continue; 1877 } 1878 if (page + map_size > size) 1879 map_size = size - page; 1880 1881 pgprot_val(vma->vm_page_prot) &= 1882 ~(par->mmap_map[i].prot_mask); 1883 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag; 1884 1885 if (remap_pfn_range(vma, vma->vm_start + page, 1886 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot)) 1887 return -EAGAIN; 1888 1889 page += map_size; 1890 } 1891 1892 if (!map_size) 1893 return -EINVAL; 1894 1895 if (!par->mmaped) 1896 par->mmaped = 1; 1897 return 0; 1898} 1899 1900static struct { 1901 u32 yoffset; 1902 u8 r[2][256]; 1903 u8 g[2][256]; 1904 u8 b[2][256]; 1905} atyfb_save; 1906 1907static void atyfb_save_palette(struct atyfb_par *par, int enter) 1908{ 1909 int i, tmp; 1910 1911 for (i = 0; i < 256; i++) { 1912 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc; 1913 if (M64_HAS(EXTRA_BRIGHT)) 1914 tmp |= 0x2; 1915 aty_st_8(DAC_CNTL, tmp, par); 1916 aty_st_8(DAC_MASK, 0xff, par); 1917 1918 writeb(i, &par->aty_cmap_regs->rindex); 1919 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut); 1920 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut); 1921 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut); 1922 writeb(i, &par->aty_cmap_regs->windex); 1923 writeb(atyfb_save.r[1 - enter][i], 1924 &par->aty_cmap_regs->lut); 1925 writeb(atyfb_save.g[1 - enter][i], 1926 &par->aty_cmap_regs->lut); 1927 writeb(atyfb_save.b[1 - enter][i], 1928 &par->aty_cmap_regs->lut); 1929 } 1930} 1931 1932static void atyfb_palette(int enter) 1933{ 1934 struct atyfb_par *par; 1935 struct fb_info *info; 1936 int i; 1937 1938 for (i = 0; i < FB_MAX; i++) { 1939 info = registered_fb[i]; 1940 if (info && info->fbops == &atyfb_ops) { 1941 par = (struct atyfb_par *) info->par; 1942 1943 atyfb_save_palette(par, enter); 1944 if (enter) { 1945 atyfb_save.yoffset = info->var.yoffset; 1946 info->var.yoffset = 0; 1947 set_off_pitch(par, info); 1948 } else { 1949 info->var.yoffset = atyfb_save.yoffset; 1950 set_off_pitch(par, info); 1951 } 1952 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par); 1953 break; 1954 } 1955 } 1956} 1957#endif /* __sparc__ */ 1958 1959 1960 1961#if defined(CONFIG_PM) && defined(CONFIG_PCI) 1962 1963/* Power management routines. Those are used for PowerBook sleep. 1964 */ 1965static int aty_power_mgmt(int sleep, struct atyfb_par *par) 1966{ 1967 u32 pm; 1968 int timeout; 1969 1970 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 1971 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG; 1972 aty_st_lcd(POWER_MANAGEMENT, pm, par); 1973 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 1974 1975 timeout = 2000; 1976 if (sleep) { 1977 /* Sleep */ 1978 pm &= ~PWR_MGT_ON; 1979 aty_st_lcd(POWER_MANAGEMENT, pm, par); 1980 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 1981 udelay(10); 1982 pm &= ~(PWR_BLON | AUTO_PWR_UP); 1983 pm |= SUSPEND_NOW; 1984 aty_st_lcd(POWER_MANAGEMENT, pm, par); 1985 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 1986 udelay(10); 1987 pm |= PWR_MGT_ON; 1988 aty_st_lcd(POWER_MANAGEMENT, pm, par); 1989 do { 1990 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 1991 mdelay(1); 1992 if ((--timeout) == 0) 1993 break; 1994 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND); 1995 } else { 1996 /* Wakeup */ 1997 pm &= ~PWR_MGT_ON; 1998 aty_st_lcd(POWER_MANAGEMENT, pm, par); 1999 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 2000 udelay(10); 2001 pm &= ~SUSPEND_NOW; 2002 pm |= (PWR_BLON | AUTO_PWR_UP); 2003 aty_st_lcd(POWER_MANAGEMENT, pm, par); 2004 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 2005 udelay(10); 2006 pm |= PWR_MGT_ON; 2007 aty_st_lcd(POWER_MANAGEMENT, pm, par); 2008 do { 2009 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 2010 mdelay(1); 2011 if ((--timeout) == 0) 2012 break; 2013 } while ((pm & PWR_MGT_STATUS_MASK) != 0); 2014 } 2015 mdelay(500); 2016 2017 return timeout ? 0 : -EIO; 2018} 2019 2020static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state) 2021{ 2022 struct fb_info *info = pci_get_drvdata(pdev); 2023 struct atyfb_par *par = (struct atyfb_par *) info->par; 2024 2025#ifndef CONFIG_PPC_PMAC 2026 /* HACK ALERT ! Once I find a proper way to say to each driver 2027 * individually what will happen with it's PCI slot, I'll change 2028 * that. On laptops, the AGP slot is just unclocked, so D2 is 2029 * expected, while on desktops, the card is powered off 2030 */ 2031 return 0; 2032#endif /* CONFIG_PPC_PMAC */ 2033 2034 if (state.event == pdev->dev.power.power_state.event) 2035 return 0; 2036 2037 acquire_console_sem(); 2038 2039 fb_set_suspend(info, 1); 2040 2041 /* Idle & reset engine */ 2042 wait_for_idle(par); 2043 aty_reset_engine(par); 2044 2045 /* Blank display and LCD */ 2046 atyfb_blank(FB_BLANK_POWERDOWN, info); 2047 2048 par->asleep = 1; 2049 par->lock_blank = 1; 2050 2051 /* Set chip to "suspend" mode */ 2052 if (aty_power_mgmt(1, par)) { 2053 par->asleep = 0; 2054 par->lock_blank = 0; 2055 atyfb_blank(FB_BLANK_UNBLANK, info); 2056 fb_set_suspend(info, 0); 2057 release_console_sem(); 2058 return -EIO; 2059 } 2060 2061 release_console_sem(); 2062 2063 pdev->dev.power.power_state = state; 2064 2065 return 0; 2066} 2067 2068static int atyfb_pci_resume(struct pci_dev *pdev) 2069{ 2070 struct fb_info *info = pci_get_drvdata(pdev); 2071 struct atyfb_par *par = (struct atyfb_par *) info->par; 2072 2073 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2074 return 0; 2075 2076 acquire_console_sem(); 2077 2078 if (pdev->dev.power.power_state.event == 2) 2079 aty_power_mgmt(0, par); 2080 par->asleep = 0; 2081 2082 /* Restore display */ 2083 atyfb_set_par(info); 2084 2085 /* Refresh */ 2086 fb_set_suspend(info, 0); 2087 2088 /* Unblank */ 2089 par->lock_blank = 0; 2090 atyfb_blank(FB_BLANK_UNBLANK, info); 2091 2092 release_console_sem(); 2093 2094 pdev->dev.power.power_state = PMSG_ON; 2095 2096 return 0; 2097} 2098 2099#endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */ 2100 2101#ifdef CONFIG_PMAC_BACKLIGHT 2102 2103 /* 2104 * LCD backlight control 2105 */ 2106 2107static int backlight_conv[] = { 2108 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d, 2109 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff 2110}; 2111 2112static int aty_set_backlight_enable(int on, int level, void *data) 2113{ 2114 struct fb_info *info = (struct fb_info *) data; 2115 struct atyfb_par *par = (struct atyfb_par *) info->par; 2116 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par); 2117 2118 reg |= (BLMOD_EN | BIASMOD_EN); 2119 if (on && level > BACKLIGHT_OFF) { 2120 reg &= ~BIAS_MOD_LEVEL_MASK; 2121 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT); 2122 } else { 2123 reg &= ~BIAS_MOD_LEVEL_MASK; 2124 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT); 2125 } 2126 aty_st_lcd(LCD_MISC_CNTL, reg, par); 2127 return 0; 2128} 2129 2130static int aty_set_backlight_level(int level, void *data) 2131{ 2132 return aty_set_backlight_enable(1, level, data); 2133} 2134 2135static struct backlight_controller aty_backlight_controller = { 2136 aty_set_backlight_enable, 2137 aty_set_backlight_level 2138}; 2139#endif /* CONFIG_PMAC_BACKLIGHT */ 2140 2141static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk) 2142{ 2143 const int ragepro_tbl[] = { 2144 44, 50, 55, 66, 75, 80, 100 2145 }; 2146 const int ragexl_tbl[] = { 2147 50, 66, 75, 83, 90, 95, 100, 105, 2148 110, 115, 120, 125, 133, 143, 166 2149 }; 2150 const int *refresh_tbl; 2151 int i, size; 2152 2153 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) { 2154 refresh_tbl = ragexl_tbl; 2155 size = sizeof(ragexl_tbl)/sizeof(int); 2156 } else { 2157 refresh_tbl = ragepro_tbl; 2158 size = sizeof(ragepro_tbl)/sizeof(int); 2159 } 2160 2161 for (i=0; i < size; i++) { 2162 if (xclk < refresh_tbl[i]) 2163 break; 2164 } 2165 par->mem_refresh_rate = i; 2166} 2167 2168 /* 2169 * Initialisation 2170 */ 2171 2172static struct fb_info *fb_list = NULL; 2173 2174#if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) 2175static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par, 2176 struct fb_var_screeninfo *var) 2177{ 2178 int ret = -EINVAL; 2179 2180 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) { 2181 *var = default_var; 2182 var->xres = var->xres_virtual = par->lcd_hdisp; 2183 var->right_margin = par->lcd_right_margin; 2184 var->left_margin = par->lcd_hblank_len - 2185 (par->lcd_right_margin + par->lcd_hsync_dly + 2186 par->lcd_hsync_len); 2187 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly; 2188 var->yres = var->yres_virtual = par->lcd_vdisp; 2189 var->lower_margin = par->lcd_lower_margin; 2190 var->upper_margin = par->lcd_vblank_len - 2191 (par->lcd_lower_margin + par->lcd_vsync_len); 2192 var->vsync_len = par->lcd_vsync_len; 2193 var->pixclock = par->lcd_pixclock; 2194 ret = 0; 2195 } 2196 2197 return ret; 2198} 2199#endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */ 2200 2201static int __init aty_init(struct fb_info *info, const char *name) 2202{ 2203 struct atyfb_par *par = (struct atyfb_par *) info->par; 2204 const char *ramname = NULL, *xtal; 2205 int gtb_memsize, has_var = 0; 2206 struct fb_var_screeninfo var; 2207 u8 pll_ref_div; 2208 u32 i; 2209#if defined(CONFIG_PPC) 2210 int sense; 2211#endif 2212 2213 init_waitqueue_head(&par->vblank.wait); 2214 spin_lock_init(&par->int_lock); 2215 2216 par->aty_cmap_regs = 2217 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0); 2218 2219#ifdef CONFIG_PPC_PMAC 2220 /* The Apple iBook1 uses non-standard memory frequencies. We detect it 2221 * and set the frequency manually. */ 2222 if (machine_is_compatible("PowerBook2,1")) { 2223 par->pll_limits.mclk = 70; 2224 par->pll_limits.xclk = 53; 2225 } 2226#endif 2227 if (pll) 2228 par->pll_limits.pll_max = pll; 2229 if (mclk) 2230 par->pll_limits.mclk = mclk; 2231 if (xclk) 2232 par->pll_limits.xclk = xclk; 2233 2234 aty_calc_mem_refresh(par, par->pll_limits.xclk); 2235 par->pll_per = 1000000/par->pll_limits.pll_max; 2236 par->mclk_per = 1000000/par->pll_limits.mclk; 2237 par->xclk_per = 1000000/par->pll_limits.xclk; 2238 2239 par->ref_clk_per = 1000000000000ULL / 14318180; 2240 xtal = "14.31818"; 2241 2242#ifdef CONFIG_FB_ATY_GX 2243 if (!M64_HAS(INTEGRATED)) { 2244 u32 stat0; 2245 u8 dac_type, dac_subtype, clk_type; 2246 stat0 = aty_ld_le32(CONFIG_STAT0, par); 2247 par->bus_type = (stat0 >> 0) & 0x07; 2248 par->ram_type = (stat0 >> 3) & 0x07; 2249 ramname = aty_gx_ram[par->ram_type]; 2250 /* FIXME: clockchip/RAMDAC probing? */ 2251 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07; 2252#ifdef CONFIG_ATARI 2253 clk_type = CLK_ATI18818_1; 2254 dac_type = (stat0 >> 9) & 0x07; 2255 if (dac_type == 0x07) 2256 dac_subtype = DAC_ATT20C408; 2257 else 2258 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type; 2259#else 2260 dac_type = DAC_IBMRGB514; 2261 dac_subtype = DAC_IBMRGB514; 2262 clk_type = CLK_IBMRGB514; 2263#endif 2264 switch (dac_subtype) { 2265 case DAC_IBMRGB514: 2266 par->dac_ops = &aty_dac_ibm514; 2267 break; 2268 case DAC_ATI68860_B: 2269 case DAC_ATI68860_C: 2270 par->dac_ops = &aty_dac_ati68860b; 2271 break; 2272 case DAC_ATT20C408: 2273 case DAC_ATT21C498: 2274 par->dac_ops = &aty_dac_att21c498; 2275 break; 2276 default: 2277 PRINTKI("aty_init: DAC type not implemented yet!\n"); 2278 par->dac_ops = &aty_dac_unsupported; 2279 break; 2280 } 2281 switch (clk_type) { 2282 case CLK_ATI18818_1: 2283 par->pll_ops = &aty_pll_ati18818_1; 2284 break; 2285 case CLK_STG1703: 2286 par->pll_ops = &aty_pll_stg1703; 2287 break; 2288 case CLK_CH8398: 2289 par->pll_ops = &aty_pll_ch8398; 2290 break; 2291 case CLK_ATT20C408: 2292 par->pll_ops = &aty_pll_att20c408; 2293 break; 2294 case CLK_IBMRGB514: 2295 par->pll_ops = &aty_pll_ibm514; 2296 break; 2297 default: 2298 PRINTKI("aty_init: CLK type not implemented yet!"); 2299 par->pll_ops = &aty_pll_unsupported; 2300 break; 2301 } 2302 } 2303#endif /* CONFIG_FB_ATY_GX */ 2304#ifdef CONFIG_FB_ATY_CT 2305 if (M64_HAS(INTEGRATED)) { 2306 par->dac_ops = &aty_dac_ct; 2307 par->pll_ops = &aty_pll_ct; 2308 par->bus_type = PCI; 2309 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07); 2310 ramname = aty_ct_ram[par->ram_type]; 2311 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ 2312 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM) 2313 par->pll_limits.mclk = 63; 2314 } 2315 2316 if (M64_HAS(GTB_DSP) 2317 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) { 2318 int diff1, diff2; 2319 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max; 2320 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max; 2321 if (diff1 < 0) 2322 diff1 = -diff1; 2323 if (diff2 < 0) 2324 diff2 = -diff2; 2325 if (diff2 < diff1) { 2326 par->ref_clk_per = 1000000000000ULL / 29498928; 2327 xtal = "29.498928"; 2328 } 2329 } 2330#endif /* CONFIG_FB_ATY_CT */ 2331 2332 /* save previous video mode */ 2333 aty_get_crtc(par, &saved_crtc); 2334 if(par->pll_ops->get_pll) 2335 par->pll_ops->get_pll(info, &saved_pll); 2336 2337 i = aty_ld_le32(MEM_CNTL, par); 2338 gtb_memsize = M64_HAS(GTB_DSP); 2339 if (gtb_memsize) 2340 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */ 2341 case MEM_SIZE_512K: 2342 info->fix.smem_len = 0x80000; 2343 break; 2344 case MEM_SIZE_1M: 2345 info->fix.smem_len = 0x100000; 2346 break; 2347 case MEM_SIZE_2M_GTB: 2348 info->fix.smem_len = 0x200000; 2349 break; 2350 case MEM_SIZE_4M_GTB: 2351 info->fix.smem_len = 0x400000; 2352 break; 2353 case MEM_SIZE_6M_GTB: 2354 info->fix.smem_len = 0x600000; 2355 break; 2356 case MEM_SIZE_8M_GTB: 2357 info->fix.smem_len = 0x800000; 2358 break; 2359 default: 2360 info->fix.smem_len = 0x80000; 2361 } else 2362 switch (i & MEM_SIZE_ALIAS) { 2363 case MEM_SIZE_512K: 2364 info->fix.smem_len = 0x80000; 2365 break; 2366 case MEM_SIZE_1M: 2367 info->fix.smem_len = 0x100000; 2368 break; 2369 case MEM_SIZE_2M: 2370 info->fix.smem_len = 0x200000; 2371 break; 2372 case MEM_SIZE_4M: 2373 info->fix.smem_len = 0x400000; 2374 break; 2375 case MEM_SIZE_6M: 2376 info->fix.smem_len = 0x600000; 2377 break; 2378 case MEM_SIZE_8M: 2379 info->fix.smem_len = 0x800000; 2380 break; 2381 default: 2382 info->fix.smem_len = 0x80000; 2383 } 2384 2385 if (M64_HAS(MAGIC_VRAM_SIZE)) { 2386 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000) 2387 info->fix.smem_len += 0x400000; 2388 } 2389 2390 if (vram) { 2391 info->fix.smem_len = vram * 1024; 2392 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS); 2393 if (info->fix.smem_len <= 0x80000) 2394 i |= MEM_SIZE_512K; 2395 else if (info->fix.smem_len <= 0x100000) 2396 i |= MEM_SIZE_1M; 2397 else if (info->fix.smem_len <= 0x200000) 2398 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M; 2399 else if (info->fix.smem_len <= 0x400000) 2400 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M; 2401 else if (info->fix.smem_len <= 0x600000) 2402 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M; 2403 else 2404 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M; 2405 aty_st_le32(MEM_CNTL, i, par); 2406 } 2407 2408 /* 2409 * Reg Block 0 (CT-compatible block) is at mmio_start 2410 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400 2411 */ 2412 if (M64_HAS(GX)) { 2413 info->fix.mmio_len = 0x400; 2414 info->fix.accel = FB_ACCEL_ATI_MACH64GX; 2415 } else if (M64_HAS(CT)) { 2416 info->fix.mmio_len = 0x400; 2417 info->fix.accel = FB_ACCEL_ATI_MACH64CT; 2418 } else if (M64_HAS(VT)) { 2419 info->fix.mmio_start -= 0x400; 2420 info->fix.mmio_len = 0x800; 2421 info->fix.accel = FB_ACCEL_ATI_MACH64VT; 2422 } else {/* GT */ 2423 info->fix.mmio_start -= 0x400; 2424 info->fix.mmio_len = 0x800; 2425 info->fix.accel = FB_ACCEL_ATI_MACH64GT; 2426 } 2427 2428 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n", 2429 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20), 2430 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max, 2431 par->pll_limits.mclk, par->pll_limits.xclk); 2432 2433#if defined(DEBUG) && defined(CONFIG_ATY_CT) 2434 if (M64_HAS(INTEGRATED)) { 2435 int i; 2436 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL " 2437 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n" 2438 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n" 2439 "debug atyfb: PLL", 2440 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par), 2441 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par), 2442 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par), 2443 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par)); 2444 for (i = 0; i < 40; i++) 2445 printk(" %02x", aty_ld_pll_ct(i, par)); 2446 printk("\n"); 2447 } 2448#endif 2449 if(par->pll_ops->init_pll) 2450 par->pll_ops->init_pll(info, &par->pll); 2451 2452 /* 2453 * Last page of 8 MB (4 MB on ISA) aperture is MMIO 2454 * FIXME: we should use the auxiliary aperture instead so we can access 2455 * the full 8 MB of video RAM on 8 MB boards 2456 */ 2457 2458 if (!par->aux_start && 2459 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000))) 2460 info->fix.smem_len -= GUI_RESERVE; 2461 2462 /* 2463 * Disable register access through the linear aperture 2464 * if the auxiliary aperture is used so we can access 2465 * the full 8 MB of video RAM on 8 MB boards. 2466 */ 2467 if (par->aux_start) 2468 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par); 2469 2470#ifdef CONFIG_MTRR 2471 par->mtrr_aper = -1; 2472 par->mtrr_reg = -1; 2473 if (!nomtrr) { 2474 /* Cover the whole resource. */ 2475 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1); 2476 if (par->mtrr_aper >= 0 && !par->aux_start) { 2477 /* Make a hole for mmio. */ 2478 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE, 2479 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1); 2480 if (par->mtrr_reg < 0) { 2481 mtrr_del(par->mtrr_aper, 0, 0); 2482 par->mtrr_aper = -1; 2483 } 2484 } 2485 } 2486#endif 2487 2488 info->fbops = &atyfb_ops; 2489 info->pseudo_palette = pseudo_palette; 2490 info->flags = FBINFO_FLAG_DEFAULT; 2491 2492#ifdef CONFIG_PMAC_BACKLIGHT 2493 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) { 2494 /* these bits let the 101 powerbook wake up from sleep -- paulus */ 2495 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par) 2496 | (USE_F32KHZ | TRISTATE_MEM_EN), par); 2497 } else if (M64_HAS(MOBIL_BUS)) 2498 register_backlight_controller(&aty_backlight_controller, info, "ati"); 2499#endif /* CONFIG_PMAC_BACKLIGHT */ 2500 2501 memset(&var, 0, sizeof(var)); 2502#ifdef CONFIG_PPC 2503 if (_machine == _MACH_Pmac) { 2504 /* 2505 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it 2506 * applies to all Mac video cards 2507 */ 2508 if (mode) { 2509 if (mac_find_mode(&var, info, mode, 8)) 2510 has_var = 1; 2511 } else { 2512 if (default_vmode == VMODE_CHOOSE) { 2513 if (M64_HAS(G3_PB_1024x768)) 2514 /* G3 PowerBook with 1024x768 LCD */ 2515 default_vmode = VMODE_1024_768_60; 2516 else if (machine_is_compatible("iMac")) 2517 default_vmode = VMODE_1024_768_75; 2518 else if (machine_is_compatible 2519 ("PowerBook2,1")) 2520 /* iBook with 800x600 LCD */ 2521 default_vmode = VMODE_800_600_60; 2522 else 2523 default_vmode = VMODE_640_480_67; 2524 sense = read_aty_sense(par); 2525 PRINTKI("monitor sense=%x, mode %d\n", 2526 sense, mac_map_monitor_sense(sense)); 2527 } 2528 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 2529 default_vmode = VMODE_640_480_60; 2530 if (default_cmode < CMODE_8 || default_cmode > CMODE_32) 2531 default_cmode = CMODE_8; 2532 if (!mac_vmode_to_var(default_vmode, default_cmode, 2533 &var)) 2534 has_var = 1; 2535 } 2536 } 2537 2538#endif /* !CONFIG_PPC */ 2539 2540#if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) 2541 if (!atyfb_get_timings_from_lcd(par, &var)) 2542 has_var = 1; 2543#endif 2544 2545 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8)) 2546 has_var = 1; 2547 2548 if (!has_var) 2549 var = default_var; 2550 2551 if (noaccel) 2552 var.accel_flags &= ~FB_ACCELF_TEXT; 2553 else 2554 var.accel_flags |= FB_ACCELF_TEXT; 2555 2556 if (comp_sync != -1) { 2557 if (!comp_sync) 2558 var.sync &= ~FB_SYNC_COMP_HIGH_ACT; 2559 else 2560 var.sync |= FB_SYNC_COMP_HIGH_ACT; 2561 } 2562 2563 if (var.yres == var.yres_virtual) { 2564 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2)); 2565 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual; 2566 if (var.yres_virtual < var.yres) 2567 var.yres_virtual = var.yres; 2568 } 2569 2570 if (atyfb_check_var(&var, info)) { 2571 PRINTKE("can't set default video mode\n"); 2572 goto aty_init_exit; 2573 } 2574 2575#ifdef __sparc__ 2576 atyfb_save_palette(par, 0); 2577#endif 2578 2579#ifdef CONFIG_FB_ATY_CT 2580 if (!noaccel && M64_HAS(INTEGRATED)) 2581 aty_init_cursor(info); 2582#endif /* CONFIG_FB_ATY_CT */ 2583 info->var = var; 2584 2585 fb_alloc_cmap(&info->cmap, 256, 0); 2586 2587 if (register_framebuffer(info) < 0) 2588 goto aty_init_exit; 2589 2590 fb_list = info; 2591 2592 PRINTKI("fb%d: %s frame buffer device on %s\n", 2593 info->node, info->fix.id, name); 2594 return 0; 2595 2596aty_init_exit: 2597 /* restore video mode */ 2598 aty_set_crtc(par, &saved_crtc); 2599 par->pll_ops->set_pll(info, &saved_pll); 2600 2601#ifdef CONFIG_MTRR 2602 if (par->mtrr_reg >= 0) { 2603 mtrr_del(par->mtrr_reg, 0, 0); 2604 par->mtrr_reg = -1; 2605 } 2606 if (par->mtrr_aper >= 0) { 2607 mtrr_del(par->mtrr_aper, 0, 0); 2608 par->mtrr_aper = -1; 2609 } 2610#endif 2611 return -1; 2612} 2613 2614#ifdef CONFIG_ATARI 2615static int __init store_video_par(char *video_str, unsigned char m64_num) 2616{ 2617 char *p; 2618 unsigned long vmembase, size, guiregbase; 2619 2620 PRINTKI("store_video_par() '%s' \n", video_str); 2621 2622 if (!(p = strsep(&video_str, ";")) || !*p) 2623 goto mach64_invalid; 2624 vmembase = simple_strtoul(p, NULL, 0); 2625 if (!(p = strsep(&video_str, ";")) || !*p) 2626 goto mach64_invalid; 2627 size = simple_strtoul(p, NULL, 0); 2628 if (!(p = strsep(&video_str, ";")) || !*p) 2629 goto mach64_invalid; 2630 guiregbase = simple_strtoul(p, NULL, 0); 2631 2632 phys_vmembase[m64_num] = vmembase; 2633 phys_size[m64_num] = size; 2634 phys_guiregbase[m64_num] = guiregbase; 2635 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size, 2636 guiregbase); 2637 return 0; 2638 2639 mach64_invalid: 2640 phys_vmembase[m64_num] = 0; 2641 return -1; 2642} 2643#endif /* CONFIG_ATARI */ 2644 2645 /* 2646 * Blank the display. 2647 */ 2648 2649static int atyfb_blank(int blank, struct fb_info *info) 2650{ 2651 struct atyfb_par *par = (struct atyfb_par *) info->par; 2652 u8 gen_cntl; 2653 2654 if (par->lock_blank || par->asleep) 2655 return 0; 2656 2657#ifdef CONFIG_PMAC_BACKLIGHT 2658 if ((_machine == _MACH_Pmac) && blank) 2659 set_backlight_enable(0); 2660#elif defined(CONFIG_FB_ATY_GENERIC_LCD) 2661 if (par->lcd_table && blank && 2662 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) { 2663 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 2664 pm &= ~PWR_BLON; 2665 aty_st_lcd(POWER_MANAGEMENT, pm, par); 2666 } 2667#endif 2668 2669 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par); 2670 switch (blank) { 2671 case FB_BLANK_UNBLANK: 2672 gen_cntl &= ~(0x4c); 2673 break; 2674 case FB_BLANK_NORMAL: 2675 gen_cntl |= 0x40; 2676 break; 2677 case FB_BLANK_VSYNC_SUSPEND: 2678 gen_cntl |= 0x8; 2679 break; 2680 case FB_BLANK_HSYNC_SUSPEND: 2681 gen_cntl |= 0x4; 2682 break; 2683 case FB_BLANK_POWERDOWN: 2684 gen_cntl |= 0x4c; 2685 break; 2686 } 2687 aty_st_8(CRTC_GEN_CNTL, gen_cntl, par); 2688 2689#ifdef CONFIG_PMAC_BACKLIGHT 2690 if ((_machine == _MACH_Pmac) && !blank) 2691 set_backlight_enable(1); 2692#elif defined(CONFIG_FB_ATY_GENERIC_LCD) 2693 if (par->lcd_table && !blank && 2694 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) { 2695 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par); 2696 pm |= PWR_BLON; 2697 aty_st_lcd(POWER_MANAGEMENT, pm, par); 2698 } 2699#endif 2700 2701 return 0; 2702} 2703 2704static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue, 2705 const struct atyfb_par *par) 2706{ 2707#ifdef CONFIG_ATARI 2708 out_8(&par->aty_cmap_regs->windex, regno); 2709 out_8(&par->aty_cmap_regs->lut, red); 2710 out_8(&par->aty_cmap_regs->lut, green); 2711 out_8(&par->aty_cmap_regs->lut, blue); 2712#else 2713 writeb(regno, &par->aty_cmap_regs->windex); 2714 writeb(red, &par->aty_cmap_regs->lut); 2715 writeb(green, &par->aty_cmap_regs->lut); 2716 writeb(blue, &par->aty_cmap_regs->lut); 2717#endif 2718} 2719 2720 /* 2721 * Set a single color register. The values supplied are already 2722 * rounded down to the hardware's capabilities (according to the 2723 * entries in the var structure). Return != 0 for invalid regno. 2724 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR 2725 */ 2726 2727static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2728 u_int transp, struct fb_info *info) 2729{ 2730 struct atyfb_par *par = (struct atyfb_par *) info->par; 2731 int i, depth; 2732 u32 *pal = info->pseudo_palette; 2733 2734 depth = info->var.bits_per_pixel; 2735 if (depth == 16) 2736 depth = (info->var.green.length == 5) ? 15 : 16; 2737 2738 if (par->asleep) 2739 return 0; 2740 2741 if (regno > 255 || 2742 (depth == 16 && regno > 63) || 2743 (depth == 15 && regno > 31)) 2744 return 1; 2745 2746 red >>= 8; 2747 green >>= 8; 2748 blue >>= 8; 2749 2750 par->palette[regno].red = red; 2751 par->palette[regno].green = green; 2752 par->palette[regno].blue = blue; 2753 2754 if (regno < 16) { 2755 switch (depth) { 2756 case 15: 2757 pal[regno] = (regno << 10) | (regno << 5) | regno; 2758 break; 2759 case 16: 2760 pal[regno] = (regno << 11) | (regno << 5) | regno; 2761 break; 2762 case 24: 2763 pal[regno] = (regno << 16) | (regno << 8) | regno; 2764 break; 2765 case 32: 2766 i = (regno << 8) | regno; 2767 pal[regno] = (i << 16) | i; 2768 break; 2769 } 2770 } 2771 2772 i = aty_ld_8(DAC_CNTL, par) & 0xfc; 2773 if (M64_HAS(EXTRA_BRIGHT)) 2774 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */ 2775 aty_st_8(DAC_CNTL, i, par); 2776 aty_st_8(DAC_MASK, 0xff, par); 2777 2778 if (M64_HAS(INTEGRATED)) { 2779 if (depth == 16) { 2780 if (regno < 32) 2781 aty_st_pal(regno << 3, red, 2782 par->palette[regno<<1].green, 2783 blue, par); 2784 red = par->palette[regno>>1].red; 2785 blue = par->palette[regno>>1].blue; 2786 regno <<= 2; 2787 } else if (depth == 15) { 2788 regno <<= 3; 2789 for(i = 0; i < 8; i++) { 2790 aty_st_pal(regno + i, red, green, blue, par); 2791 } 2792 } 2793 } 2794 aty_st_pal(regno, red, green, blue, par); 2795 2796 return 0; 2797} 2798 2799#ifdef CONFIG_PCI 2800 2801#ifdef __sparc__ 2802 2803extern void (*prom_palette) (int); 2804 2805static int __devinit atyfb_setup_sparc(struct pci_dev *pdev, 2806 struct fb_info *info, unsigned long addr) 2807{ 2808 extern int con_is_present(void); 2809 2810 struct atyfb_par *par = info->par; 2811 struct pcidev_cookie *pcp; 2812 char prop[128]; 2813 int node, len, i, j, ret; 2814 u32 mem, chip_id; 2815 2816 /* Do not attach when we have a serial console. */ 2817 if (!con_is_present()) 2818 return -ENXIO; 2819 2820 /* 2821 * Map memory-mapped registers. 2822 */ 2823 par->ati_regbase = (void *)addr + 0x7ffc00UL; 2824 info->fix.mmio_start = addr + 0x7ffc00UL; 2825 2826 /* 2827 * Map in big-endian aperture. 2828 */ 2829 info->screen_base = (char *) (addr + 0x800000UL); 2830 info->fix.smem_start = addr + 0x800000UL; 2831 2832 /* 2833 * Figure mmap addresses from PCI config space. 2834 * Split Framebuffer in big- and little-endian halfs. 2835 */ 2836 for (i = 0; i < 6 && pdev->resource[i].start; i++) 2837 /* nothing */ ; 2838 j = i + 4; 2839 2840 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC); 2841 if (!par->mmap_map) { 2842 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n"); 2843 return -ENOMEM; 2844 } 2845 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map)); 2846 2847 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) { 2848 struct resource *rp = &pdev->resource[i]; 2849 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2); 2850 unsigned long base; 2851 u32 size, pbase; 2852 2853 base = rp->start; 2854 2855 io = (rp->flags & IORESOURCE_IO); 2856 2857 size = rp->end - base + 1; 2858 2859 pci_read_config_dword(pdev, breg, &pbase); 2860 2861 if (io) 2862 size &= ~1; 2863 2864 /* 2865 * Map the framebuffer a second time, this time without 2866 * the braindead _PAGE_IE setting. This is used by the 2867 * fixed Xserver, but we need to maintain the old mapping 2868 * to stay compatible with older ones... 2869 */ 2870 if (base == addr) { 2871 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK; 2872 par->mmap_map[j].poff = base & PAGE_MASK; 2873 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK; 2874 par->mmap_map[j].prot_mask = _PAGE_CACHE; 2875 par->mmap_map[j].prot_flag = _PAGE_E; 2876 j++; 2877 } 2878 2879 /* 2880 * Here comes the old framebuffer mapping with _PAGE_IE 2881 * set for the big endian half of the framebuffer... 2882 */ 2883 if (base == addr) { 2884 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK; 2885 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK; 2886 par->mmap_map[j].size = 0x800000; 2887 par->mmap_map[j].prot_mask = _PAGE_CACHE; 2888 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE; 2889 size -= 0x800000; 2890 j++; 2891 } 2892 2893 par->mmap_map[j].voff = pbase & PAGE_MASK; 2894 par->mmap_map[j].poff = base & PAGE_MASK; 2895 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK; 2896 par->mmap_map[j].prot_mask = _PAGE_CACHE; 2897 par->mmap_map[j].prot_flag = _PAGE_E; 2898 j++; 2899 } 2900 2901 if((ret = correct_chipset(par))) 2902 return ret; 2903 2904 if (IS_XL(pdev->device)) { 2905 /* 2906 * Fix PROMs idea of MEM_CNTL settings... 2907 */ 2908 mem = aty_ld_le32(MEM_CNTL, par); 2909 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par); 2910 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) { 2911 switch (mem & 0x0f) { 2912 case 3: 2913 mem = (mem & ~(0x0f)) | 2; 2914 break; 2915 case 7: 2916 mem = (mem & ~(0x0f)) | 3; 2917 break; 2918 case 9: 2919 mem = (mem & ~(0x0f)) | 4; 2920 break; 2921 case 11: 2922 mem = (mem & ~(0x0f)) | 5; 2923 break; 2924 default: 2925 break; 2926 } 2927 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM) 2928 mem &= ~(0x00700000); 2929 } 2930 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */ 2931 aty_st_le32(MEM_CNTL, mem, par); 2932 } 2933 2934 /* 2935 * If this is the console device, we will set default video 2936 * settings to what the PROM left us with. 2937 */ 2938 node = prom_getchild(prom_root_node); 2939 node = prom_searchsiblings(node, "aliases"); 2940 if (node) { 2941 len = prom_getproperty(node, "screen", prop, sizeof(prop)); 2942 if (len > 0) { 2943 prop[len] = '\0'; 2944 node = prom_finddevice(prop); 2945 } else 2946 node = 0; 2947 } 2948 2949 pcp = pdev->sysdata; 2950 if (node == pcp->prom_node) { 2951 struct fb_var_screeninfo *var = &default_var; 2952 unsigned int N, P, Q, M, T, R; 2953 u32 v_total, h_total; 2954 struct crtc crtc; 2955 u8 pll_regs[16]; 2956 u8 clock_cntl; 2957 2958 crtc.vxres = prom_getintdefault(node, "width", 1024); 2959 crtc.vyres = prom_getintdefault(node, "height", 768); 2960 var->bits_per_pixel = prom_getintdefault(node, "depth", 8); 2961 var->xoffset = var->yoffset = 0; 2962 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par); 2963 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par); 2964 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par); 2965 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par); 2966 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); 2967 aty_crtc_to_var(&crtc, var); 2968 2969 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin; 2970 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin; 2971 2972 /* 2973 * Read the PLL to figure actual Refresh Rate. 2974 */ 2975 clock_cntl = aty_ld_8(CLOCK_CNTL, par); 2976 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */ 2977 for (i = 0; i < 16; i++) 2978 pll_regs[i] = aty_ld_pll_ct(i, par); 2979 2980 /* 2981 * PLL Reference Divider M: 2982 */ 2983 M = pll_regs[2]; 2984 2985 /* 2986 * PLL Feedback Divider N (Dependant on CLOCK_CNTL): 2987 */ 2988 N = pll_regs[7 + (clock_cntl & 3)]; 2989 2990 /* 2991 * PLL Post Divider P (Dependant on CLOCK_CNTL): 2992 */ 2993 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1)); 2994 2995 /* 2996 * PLL Divider Q: 2997 */ 2998 Q = N / P; 2999 3000 /* 3001 * Target Frequency: 3002 * 3003 * T * M 3004 * Q = ------- 3005 * 2 * R 3006 * 3007 * where R is XTALIN (= 14318 or 29498 kHz). 3008 */ 3009 if (IS_XL(pdev->device)) 3010 R = 29498; 3011 else 3012 R = 14318; 3013 3014 T = 2 * Q * R / M; 3015 3016 default_var.pixclock = 1000000000 / T; 3017 } 3018 3019 return 0; 3020} 3021 3022#else /* __sparc__ */ 3023 3024#ifdef __i386__ 3025#ifdef CONFIG_FB_ATY_GENERIC_LCD 3026static void aty_init_lcd(struct atyfb_par *par, u32 bios_base) 3027{ 3028 u32 driv_inf_tab, sig; 3029 u16 lcd_ofs; 3030 3031 /* To support an LCD panel, we should know it's dimensions and 3032 * it's desired pixel clock. 3033 * There are two ways to do it: 3034 * - Check the startup video mode and calculate the panel 3035 * size from it. This is unreliable. 3036 * - Read it from the driver information table in the video BIOS. 3037 */ 3038 /* Address of driver information table is at offset 0x78. */ 3039 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78)); 3040 3041 /* Check for the driver information table signature. */ 3042 sig = (*(u32 *)driv_inf_tab); 3043 if ((sig == 0x54504c24) || /* Rage LT pro */ 3044 (sig == 0x544d5224) || /* Rage mobility */ 3045 (sig == 0x54435824) || /* Rage XC */ 3046 (sig == 0x544c5824)) { /* Rage XL */ 3047 PRINTKI("BIOS contains driver information table.\n"); 3048 lcd_ofs = (*(u16 *)(driv_inf_tab + 10)); 3049 par->lcd_table = 0; 3050 if (lcd_ofs != 0) { 3051 par->lcd_table = bios_base + lcd_ofs; 3052 } 3053 } 3054 3055 if (par->lcd_table != 0) { 3056 char model[24]; 3057 char strbuf[16]; 3058 char refresh_rates_buf[100]; 3059 int id, tech, f, i, m, default_refresh_rate; 3060 char *txtcolour; 3061 char *txtmonitor; 3062 char *txtdual; 3063 char *txtformat; 3064 u16 width, height, panel_type, refresh_rates; 3065 u16 *lcdmodeptr; 3066 u32 format; 3067 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200}; 3068 /* The most important information is the panel size at 3069 * offset 25 and 27, but there's some other nice information 3070 * which we print to the screen. 3071 */ 3072 id = *(u8 *)par->lcd_table; 3073 strncpy(model,(char *)par->lcd_table+1,24); 3074 model[23]=0; 3075 3076 width = par->lcd_width = *(u16 *)(par->lcd_table+25); 3077 height = par->lcd_height = *(u16 *)(par->lcd_table+27); 3078 panel_type = *(u16 *)(par->lcd_table+29); 3079 if (panel_type & 1) 3080 txtcolour = "colour"; 3081 else 3082 txtcolour = "monochrome"; 3083 if (panel_type & 2) 3084 txtdual = "dual (split) "; 3085 else 3086 txtdual = ""; 3087 tech = (panel_type>>2) & 63; 3088 switch (tech) { 3089 case 0: 3090 txtmonitor = "passive matrix"; 3091 break; 3092 case 1: 3093 txtmonitor = "active matrix"; 3094 break; 3095 case 2: 3096 txtmonitor = "active addressed STN"; 3097 break; 3098 case 3: 3099 txtmonitor = "EL"; 3100 break; 3101 case 4: 3102 txtmonitor = "plasma"; 3103 break; 3104 default: 3105 txtmonitor = "unknown"; 3106 } 3107 format = *(u32 *)(par->lcd_table+57); 3108 if (tech == 0 || tech == 2) { 3109 switch (format & 7) { 3110 case 0: 3111 txtformat = "12 bit interface"; 3112 break; 3113 case 1: 3114 txtformat = "16 bit interface"; 3115 break; 3116 case 2: 3117 txtformat = "24 bit interface"; 3118 break; 3119 default: 3120 txtformat = "unkown format"; 3121 } 3122 } else { 3123 switch (format & 7) { 3124 case 0: 3125 txtformat = "8 colours"; 3126 break; 3127 case 1: 3128 txtformat = "512 colours"; 3129 break; 3130 case 2: 3131 txtformat = "4096 colours"; 3132 break; 3133 case 4: 3134 txtformat = "262144 colours (LT mode)"; 3135 break; 3136 case 5: 3137 txtformat = "16777216 colours"; 3138 break; 3139 case 6: 3140 txtformat = "262144 colours (FDPI-2 mode)"; 3141 break; 3142 default: 3143 txtformat = "unkown format"; 3144 } 3145 } 3146 PRINTKI("%s%s %s monitor detected: %s\n", 3147 txtdual ,txtcolour, txtmonitor, model); 3148 PRINTKI(" id=%d, %dx%d pixels, %s\n", 3149 id, width, height, txtformat); 3150 refresh_rates_buf[0] = 0; 3151 refresh_rates = *(u16 *)(par->lcd_table+62); 3152 m = 1; 3153 f = 0; 3154 for (i=0;i<16;i++) { 3155 if (refresh_rates & m) { 3156 if (f == 0) { 3157 sprintf(strbuf, "%d", lcd_refresh_rates[i]); 3158 f++; 3159 } else { 3160 sprintf(strbuf, ",%d", lcd_refresh_rates[i]); 3161 } 3162 strcat(refresh_rates_buf,strbuf); 3163 } 3164 m = m << 1; 3165 } 3166 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4; 3167 PRINTKI(" supports refresh rates [%s], default %d Hz\n", 3168 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]); 3169 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate]; 3170 /* We now need to determine the crtc parameters for the 3171 * LCD monitor. This is tricky, because they are not stored 3172 * individually in the BIOS. Instead, the BIOS contains a 3173 * table of display modes that work for this monitor. 3174 * 3175 * The idea is that we search for a mode of the same dimensions 3176 * as the dimensions of the LCD monitor. Say our LCD monitor 3177 * is 800x600 pixels, we search for a 800x600 monitor. 3178 * The CRTC parameters we find here are the ones that we need 3179 * to use to simulate other resolutions on the LCD screen. 3180 */ 3181 lcdmodeptr = (u16 *)(par->lcd_table + 64); 3182 while (*lcdmodeptr != 0) { 3183 u32 modeptr; 3184 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start; 3185 modeptr = bios_base + *lcdmodeptr; 3186 3187 mwidth = *((u16 *)(modeptr+0)); 3188 mheight = *((u16 *)(modeptr+2)); 3189 3190 if (mwidth == width && mheight == height) { 3191 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9)); 3192 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511; 3193 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511; 3194 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511; 3195 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7; 3196 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63; 3197 3198 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047; 3199 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047; 3200 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047; 3201 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31; 3202 3203 par->lcd_htotal = (par->lcd_htotal + 1) * 8; 3204 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8; 3205 lcd_hsync_start = (lcd_hsync_start + 1) * 8; 3206 par->lcd_hsync_len = par->lcd_hsync_len * 8; 3207 3208 par->lcd_vtotal++; 3209 par->lcd_vdisp++; 3210 lcd_vsync_start++; 3211 3212 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp; 3213 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp; 3214 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp; 3215 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp; 3216 break; 3217 } 3218 3219 lcdmodeptr++; 3220 } 3221 if (*lcdmodeptr == 0) { 3222 PRINTKE("LCD monitor CRTC parameters not found!!!\n"); 3223 /* To do: Switch to CRT if possible. */ 3224 } else { 3225 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n", 3226 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock, 3227 par->lcd_hdisp, 3228 par->lcd_hdisp + par->lcd_right_margin, 3229 par->lcd_hdisp + par->lcd_right_margin 3230 + par->lcd_hsync_dly + par->lcd_hsync_len, 3231 par->lcd_htotal, 3232 par->lcd_vdisp, 3233 par->lcd_vdisp + par->lcd_lower_margin, 3234 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len, 3235 par->lcd_vtotal); 3236 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n", 3237 par->lcd_pixclock, 3238 par->lcd_hblank_len - (par->lcd_right_margin + 3239 par->lcd_hsync_dly + par->lcd_hsync_len), 3240 par->lcd_hdisp, 3241 par->lcd_right_margin, 3242 par->lcd_hsync_len, 3243 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len), 3244 par->lcd_vdisp, 3245 par->lcd_lower_margin, 3246 par->lcd_vsync_len); 3247 } 3248 } 3249} 3250#endif /* CONFIG_FB_ATY_GENERIC_LCD */ 3251 3252static int __devinit init_from_bios(struct atyfb_par *par) 3253{ 3254 u32 bios_base, rom_addr; 3255 int ret; 3256 3257 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11); 3258 bios_base = (unsigned long)ioremap(rom_addr, 0x10000); 3259 3260 /* The BIOS starts with 0xaa55. */ 3261 if (*((u16 *)bios_base) == 0xaa55) { 3262 3263 u8 *bios_ptr; 3264 u16 rom_table_offset, freq_table_offset; 3265 PLL_BLOCK_MACH64 pll_block; 3266 3267 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base); 3268 3269 /* check for frequncy table */ 3270 bios_ptr = (u8*)bios_base; 3271 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8)); 3272 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8); 3273 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64)); 3274 3275 PRINTKI("BIOS frequency table:\n"); 3276 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n", 3277 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq, 3278 pll_block.ref_freq, pll_block.ref_divider); 3279 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n", 3280 pll_block.MCLK_pwd, pll_block.MCLK_max_freq, 3281 pll_block.XCLK_max_freq, pll_block.SCLK_freq); 3282 3283 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100; 3284 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100; 3285 par->pll_limits.ref_clk = pll_block.ref_freq/100; 3286 par->pll_limits.ref_div = pll_block.ref_divider; 3287 par->pll_limits.sclk = pll_block.SCLK_freq/100; 3288 par->pll_limits.mclk = pll_block.MCLK_max_freq/100; 3289 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100; 3290 par->pll_limits.xclk = pll_block.XCLK_max_freq/100; 3291#ifdef CONFIG_FB_ATY_GENERIC_LCD 3292 aty_init_lcd(par, bios_base); 3293#endif 3294 ret = 0; 3295 } else { 3296 PRINTKE("no BIOS frequency table found, use parameters\n"); 3297 ret = -ENXIO; 3298 } 3299 iounmap((void* __iomem )bios_base); 3300 3301 return ret; 3302} 3303#endif /* __i386__ */ 3304 3305static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr) 3306{ 3307 struct atyfb_par *par = info->par; 3308 u16 tmp; 3309 unsigned long raddr; 3310 struct resource *rrp; 3311 int ret = 0; 3312 3313 raddr = addr + 0x7ff000UL; 3314 rrp = &pdev->resource[2]; 3315 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) { 3316 par->aux_start = rrp->start; 3317 par->aux_size = rrp->end - rrp->start + 1; 3318 raddr = rrp->start; 3319 PRINTKI("using auxiliary register aperture\n"); 3320 } 3321 3322 info->fix.mmio_start = raddr; 3323 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000); 3324 if (par->ati_regbase == 0) 3325 return -ENOMEM; 3326 3327 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00; 3328 par->ati_regbase += par->aux_start ? 0x400 : 0xc00; 3329 3330 /* 3331 * Enable memory-space accesses using config-space 3332 * command register. 3333 */ 3334 pci_read_config_word(pdev, PCI_COMMAND, &tmp); 3335 if (!(tmp & PCI_COMMAND_MEMORY)) { 3336 tmp |= PCI_COMMAND_MEMORY; 3337 pci_write_config_word(pdev, PCI_COMMAND, tmp); 3338 } 3339#ifdef __BIG_ENDIAN 3340 /* Use the big-endian aperture */ 3341 addr += 0x800000; 3342#endif 3343 3344 /* Map in frame buffer */ 3345 info->fix.smem_start = addr; 3346 info->screen_base = ioremap(addr, 0x800000); 3347 if (info->screen_base == NULL) { 3348 ret = -ENOMEM; 3349 goto atyfb_setup_generic_fail; 3350 } 3351 3352 if((ret = correct_chipset(par))) 3353 goto atyfb_setup_generic_fail; 3354#ifdef __i386__ 3355 if((ret = init_from_bios(par))) 3356 goto atyfb_setup_generic_fail; 3357#endif 3358 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN)) 3359 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2; 3360 else 3361 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U; 3362 3363 /* according to ATI, we should use clock 3 for acelerated mode */ 3364 par->clk_wr_offset = 3; 3365 3366 return 0; 3367 3368atyfb_setup_generic_fail: 3369 iounmap(par->ati_regbase); 3370 par->ati_regbase = NULL; 3371 return ret; 3372} 3373 3374#endif /* !__sparc__ */ 3375 3376static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3377{ 3378 unsigned long addr, res_start, res_size; 3379 struct fb_info *info; 3380 struct resource *rp; 3381 struct atyfb_par *par; 3382 int i, rc = -ENOMEM; 3383 3384 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--) 3385 if (pdev->device == aty_chips[i].pci_id) 3386 break; 3387 3388 if (i < 0) 3389 return -ENODEV; 3390 3391 /* Enable device in PCI config */ 3392 if (pci_enable_device(pdev)) { 3393 PRINTKE("Cannot enable PCI device\n"); 3394 return -ENXIO; 3395 } 3396 3397 /* Find which resource to use */ 3398 rp = &pdev->resource[0]; 3399 if (rp->flags & IORESOURCE_IO) 3400 rp = &pdev->resource[1]; 3401 addr = rp->start; 3402 if (!addr) 3403 return -ENXIO; 3404 3405 /* Reserve space */ 3406 res_start = rp->start; 3407 res_size = rp->end - rp->start + 1; 3408 if (!request_mem_region (res_start, res_size, "atyfb")) 3409 return -EBUSY; 3410 3411 /* Allocate framebuffer */ 3412 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev); 3413 if (!info) { 3414 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n"); 3415 return -ENOMEM; 3416 } 3417 par = info->par; 3418 info->fix = atyfb_fix; 3419 info->device = &pdev->dev; 3420 par->pci_id = aty_chips[i].pci_id; 3421 par->res_start = res_start; 3422 par->res_size = res_size; 3423 par->irq = pdev->irq; 3424 3425 /* Setup "info" structure */ 3426#ifdef __sparc__ 3427 rc = atyfb_setup_sparc(pdev, info, addr); 3428#else 3429 rc = atyfb_setup_generic(pdev, info, addr); 3430#endif 3431 if (rc) 3432 goto err_release_mem; 3433 3434 pci_set_drvdata(pdev, info); 3435 3436 /* Init chip & register framebuffer */ 3437 if (aty_init(info, "PCI")) 3438 goto err_release_io; 3439 3440#ifdef __sparc__ 3441 if (!prom_palette) 3442 prom_palette = atyfb_palette; 3443 3444 /* 3445 * Add /dev/fb mmap values. 3446 */ 3447 par->mmap_map[0].voff = 0x8000000000000000UL; 3448 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK; 3449 par->mmap_map[0].size = info->fix.smem_len; 3450 par->mmap_map[0].prot_mask = _PAGE_CACHE; 3451 par->mmap_map[0].prot_flag = _PAGE_E; 3452 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len; 3453 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK; 3454 par->mmap_map[1].size = PAGE_SIZE; 3455 par->mmap_map[1].prot_mask = _PAGE_CACHE; 3456 par->mmap_map[1].prot_flag = _PAGE_E; 3457#endif /* __sparc__ */ 3458 3459 return 0; 3460 3461err_release_io: 3462#ifdef __sparc__ 3463 kfree(par->mmap_map); 3464#else 3465 if (par->ati_regbase) 3466 iounmap(par->ati_regbase); 3467 if (info->screen_base) 3468 iounmap(info->screen_base); 3469#endif 3470err_release_mem: 3471 if (par->aux_start) 3472 release_mem_region(par->aux_start, par->aux_size); 3473 3474 release_mem_region(par->res_start, par->res_size); 3475 framebuffer_release(info); 3476 3477 return rc; 3478} 3479 3480#endif /* CONFIG_PCI */ 3481 3482#ifdef CONFIG_ATARI 3483 3484static int __devinit atyfb_atari_probe(void) 3485{ 3486 struct aty_par *par; 3487 struct fb_info *info; 3488 int m64_num; 3489 u32 clock_r; 3490 3491 for (m64_num = 0; m64_num < mach64_count; m64_num++) { 3492 if (!phys_vmembase[m64_num] || !phys_size[m64_num] || 3493 !phys_guiregbase[m64_num]) { 3494 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num); 3495 continue; 3496 } 3497 3498 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL); 3499 if (!info) { 3500 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n"); 3501 return -ENOMEM; 3502 } 3503 par = info->par; 3504 3505 info->fix = atyfb_fix; 3506 3507 par->irq = (unsigned int) -1; /* something invalid */ 3508 3509 /* 3510 * Map the video memory (physical address given) to somewhere in the 3511 * kernel address space. 3512 */ 3513 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]); 3514 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */ 3515 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) + 3516 0xFC00ul; 3517 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */ 3518 3519 aty_st_le32(CLOCK_CNTL, 0x12345678, par); 3520 clock_r = aty_ld_le32(CLOCK_CNTL, par); 3521 3522 switch (clock_r & 0x003F) { 3523 case 0x12: 3524 par->clk_wr_offset = 3; /* */ 3525 break; 3526 case 0x34: 3527 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */ 3528 break; 3529 case 0x16: 3530 par->clk_wr_offset = 1; /* */ 3531 break; 3532 case 0x38: 3533 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */ 3534 break; 3535 } 3536 3537 if (aty_init(info, "ISA bus")) { 3538 framebuffer_release(info); 3539 /* This is insufficient! kernel_map has added two large chunks!! */ 3540 return -ENXIO; 3541 } 3542 } 3543} 3544 3545#endif /* CONFIG_ATARI */ 3546 3547static void __devexit atyfb_remove(struct fb_info *info) 3548{ 3549 struct atyfb_par *par = (struct atyfb_par *) info->par; 3550 3551 /* restore video mode */ 3552 aty_set_crtc(par, &saved_crtc); 3553 par->pll_ops->set_pll(info, &saved_pll); 3554 3555 unregister_framebuffer(info); 3556 3557#ifdef CONFIG_MTRR 3558 if (par->mtrr_reg >= 0) { 3559 mtrr_del(par->mtrr_reg, 0, 0); 3560 par->mtrr_reg = -1; 3561 } 3562 if (par->mtrr_aper >= 0) { 3563 mtrr_del(par->mtrr_aper, 0, 0); 3564 par->mtrr_aper = -1; 3565 } 3566#endif 3567#ifndef __sparc__ 3568 if (par->ati_regbase) 3569 iounmap(par->ati_regbase); 3570 if (info->screen_base) 3571 iounmap(info->screen_base); 3572#ifdef __BIG_ENDIAN 3573 if (info->sprite.addr) 3574 iounmap(info->sprite.addr); 3575#endif 3576#endif 3577#ifdef __sparc__ 3578 kfree(par->mmap_map); 3579#endif 3580 if (par->aux_start) 3581 release_mem_region(par->aux_start, par->aux_size); 3582 3583 if (par->res_start) 3584 release_mem_region(par->res_start, par->res_size); 3585 3586 framebuffer_release(info); 3587} 3588 3589#ifdef CONFIG_PCI 3590 3591static void __devexit atyfb_pci_remove(struct pci_dev *pdev) 3592{ 3593 struct fb_info *info = pci_get_drvdata(pdev); 3594 3595 atyfb_remove(info); 3596} 3597 3598/* 3599 * This driver uses its own matching table. That will be more difficult 3600 * to fix, so for now, we just match against any ATI ID and let the 3601 * probe() function find out what's up. That also mean we don't have 3602 * a module ID table though. 3603 */ 3604static struct pci_device_id atyfb_pci_tbl[] = { 3605 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 3606 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 }, 3607 { 0, } 3608}; 3609 3610static struct pci_driver atyfb_driver = { 3611 .name = "atyfb", 3612 .id_table = atyfb_pci_tbl, 3613 .probe = atyfb_pci_probe, 3614 .remove = __devexit_p(atyfb_pci_remove), 3615#ifdef CONFIG_PM 3616 .suspend = atyfb_pci_suspend, 3617 .resume = atyfb_pci_resume, 3618#endif /* CONFIG_PM */ 3619}; 3620 3621#endif /* CONFIG_PCI */ 3622 3623#ifndef MODULE 3624static int __init atyfb_setup(char *options) 3625{ 3626 char *this_opt; 3627 3628 if (!options || !*options) 3629 return 0; 3630 3631 while ((this_opt = strsep(&options, ",")) != NULL) { 3632 if (!strncmp(this_opt, "noaccel", 7)) { 3633 noaccel = 1; 3634#ifdef CONFIG_MTRR 3635 } else if (!strncmp(this_opt, "nomtrr", 6)) { 3636 nomtrr = 1; 3637#endif 3638 } else if (!strncmp(this_opt, "vram:", 5)) 3639 vram = simple_strtoul(this_opt + 5, NULL, 0); 3640 else if (!strncmp(this_opt, "pll:", 4)) 3641 pll = simple_strtoul(this_opt + 4, NULL, 0); 3642 else if (!strncmp(this_opt, "mclk:", 5)) 3643 mclk = simple_strtoul(this_opt + 5, NULL, 0); 3644 else if (!strncmp(this_opt, "xclk:", 5)) 3645 xclk = simple_strtoul(this_opt+5, NULL, 0); 3646 else if (!strncmp(this_opt, "comp_sync:", 10)) 3647 comp_sync = simple_strtoul(this_opt+10, NULL, 0); 3648#ifdef CONFIG_PPC 3649 else if (!strncmp(this_opt, "vmode:", 6)) { 3650 unsigned int vmode = 3651 simple_strtoul(this_opt + 6, NULL, 0); 3652 if (vmode > 0 && vmode <= VMODE_MAX) 3653 default_vmode = vmode; 3654 } else if (!strncmp(this_opt, "cmode:", 6)) { 3655 unsigned int cmode = 3656 simple_strtoul(this_opt + 6, NULL, 0); 3657 switch (cmode) { 3658 case 0: 3659 case 8: 3660 default_cmode = CMODE_8; 3661 break; 3662 case 15: 3663 case 16: 3664 default_cmode = CMODE_16; 3665 break; 3666 case 24: 3667 case 32: 3668 default_cmode = CMODE_32; 3669 break; 3670 } 3671 } 3672#endif 3673#ifdef CONFIG_ATARI 3674 /* 3675 * Why do we need this silly Mach64 argument? 3676 * We are already here because of mach64= so its redundant. 3677 */ 3678 else if (MACH_IS_ATARI 3679 && (!strncmp(this_opt, "Mach64:", 7))) { 3680 static unsigned char m64_num; 3681 static char mach64_str[80]; 3682 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str)); 3683 if (!store_video_par(mach64_str, m64_num)) { 3684 m64_num++; 3685 mach64_count = m64_num; 3686 } 3687 } 3688#endif 3689 else 3690 mode = this_opt; 3691 } 3692 return 0; 3693} 3694#endif /* MODULE */ 3695 3696static int __init atyfb_init(void) 3697{ 3698#ifndef MODULE 3699 char *option = NULL; 3700 3701 if (fb_get_options("atyfb", &option)) 3702 return -ENODEV; 3703 atyfb_setup(option); 3704#endif 3705 3706 pci_register_driver(&atyfb_driver); 3707#ifdef CONFIG_ATARI 3708 atyfb_atari_probe(); 3709#endif 3710 return 0; 3711} 3712 3713static void __exit atyfb_exit(void) 3714{ 3715 pci_unregister_driver(&atyfb_driver); 3716} 3717 3718module_init(atyfb_init); 3719module_exit(atyfb_exit); 3720 3721MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards"); 3722MODULE_LICENSE("GPL"); 3723module_param(noaccel, bool, 0); 3724MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 3725module_param(vram, int, 0); 3726MODULE_PARM_DESC(vram, "int: override size of video ram"); 3727module_param(pll, int, 0); 3728MODULE_PARM_DESC(pll, "int: override video clock"); 3729module_param(mclk, int, 0); 3730MODULE_PARM_DESC(mclk, "int: override memory clock"); 3731module_param(xclk, int, 0); 3732MODULE_PARM_DESC(xclk, "int: override accelerated engine clock"); 3733module_param(comp_sync, int, 0); 3734MODULE_PARM_DESC(comp_sync, 3735 "Set composite sync signal to low (0) or high (1)"); 3736module_param(mode, charp, 0); 3737MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 3738#ifdef CONFIG_MTRR 3739module_param(nomtrr, bool, 0); 3740MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); 3741#endif 3742