w1_io.c revision 12003375acd879e498c6c511faf27531296f9640
1/* 2 * w1_io.c 3 * 4 * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru> 5 * 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#include <asm/io.h> 23 24#include <linux/delay.h> 25#include <linux/moduleparam.h> 26 27#include "w1.h" 28#include "w1_log.h" 29 30static int w1_delay_parm = 1; 31module_param_named(delay_coef, w1_delay_parm, int, 0); 32 33static u8 w1_crc8_table[] = { 34 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65, 35 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220, 36 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98, 37 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255, 38 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7, 39 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154, 40 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36, 41 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185, 42 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205, 43 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80, 44 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238, 45 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115, 46 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139, 47 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22, 48 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168, 49 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53 50}; 51 52void w1_delay(unsigned long tm) 53{ 54 udelay(tm * w1_delay_parm); 55} 56 57static void w1_write_bit(struct w1_master *dev, int bit); 58static u8 w1_read_bit(struct w1_master *dev); 59 60/** 61 * Generates a write-0 or write-1 cycle and samples the level. 62 */ 63u8 w1_touch_bit(struct w1_master *dev, int bit) 64{ 65 if (dev->bus_master->touch_bit) 66 return dev->bus_master->touch_bit(dev->bus_master->data, bit); 67 else if (bit) 68 return w1_read_bit(dev); 69 else { 70 w1_write_bit(dev, 0); 71 return(0); 72 } 73} 74 75/** 76 * Generates a write-0 or write-1 cycle. 77 * Only call if dev->bus_master->touch_bit is NULL 78 */ 79static void w1_write_bit(struct w1_master *dev, int bit) 80{ 81 if (bit) { 82 dev->bus_master->write_bit(dev->bus_master->data, 0); 83 w1_delay(6); 84 dev->bus_master->write_bit(dev->bus_master->data, 1); 85 w1_delay(64); 86 } else { 87 dev->bus_master->write_bit(dev->bus_master->data, 0); 88 w1_delay(60); 89 dev->bus_master->write_bit(dev->bus_master->data, 1); 90 w1_delay(10); 91 } 92} 93 94/** 95 * Writes 8 bits. 96 * 97 * @param dev the master device 98 * @param byte the byte to write 99 */ 100void w1_write_8(struct w1_master *dev, u8 byte) 101{ 102 int i; 103 104 if (dev->bus_master->write_byte) 105 dev->bus_master->write_byte(dev->bus_master->data, byte); 106 else 107 for (i = 0; i < 8; ++i) 108 w1_touch_bit(dev, (byte >> i) & 0x1); 109} 110 111 112/** 113 * Generates a write-1 cycle and samples the level. 114 * Only call if dev->bus_master->touch_bit is NULL 115 */ 116static u8 w1_read_bit(struct w1_master *dev) 117{ 118 int result; 119 120 dev->bus_master->write_bit(dev->bus_master->data, 0); 121 w1_delay(6); 122 dev->bus_master->write_bit(dev->bus_master->data, 1); 123 w1_delay(9); 124 125 result = dev->bus_master->read_bit(dev->bus_master->data); 126 w1_delay(55); 127 128 return result & 0x1; 129} 130 131/** 132 * Does a triplet - used for searching ROM addresses. 133 * Return bits: 134 * bit 0 = id_bit 135 * bit 1 = comp_bit 136 * bit 2 = dir_taken 137 * If both bits 0 & 1 are set, the search should be restarted. 138 * 139 * @param dev the master device 140 * @param bdir the bit to write if both id_bit and comp_bit are 0 141 * @return bit fields - see above 142 */ 143u8 w1_triplet(struct w1_master *dev, int bdir) 144{ 145 if ( dev->bus_master->triplet ) 146 return(dev->bus_master->triplet(dev->bus_master->data, bdir)); 147 else { 148 u8 id_bit = w1_touch_bit(dev, 1); 149 u8 comp_bit = w1_touch_bit(dev, 1); 150 u8 retval; 151 152 if ( id_bit && comp_bit ) 153 return(0x03); /* error */ 154 155 if ( !id_bit && !comp_bit ) { 156 /* Both bits are valid, take the direction given */ 157 retval = bdir ? 0x04 : 0; 158 } else { 159 /* Only one bit is valid, take that direction */ 160 bdir = id_bit; 161 retval = id_bit ? 0x05 : 0x02; 162 } 163 164 if ( dev->bus_master->touch_bit ) 165 w1_touch_bit(dev, bdir); 166 else 167 w1_write_bit(dev, bdir); 168 return(retval); 169 } 170} 171 172/** 173 * Reads 8 bits. 174 * 175 * @param dev the master device 176 * @return the byte read 177 */ 178u8 w1_read_8(struct w1_master * dev) 179{ 180 int i; 181 u8 res = 0; 182 183 if (dev->bus_master->read_byte) 184 res = dev->bus_master->read_byte(dev->bus_master->data); 185 else 186 for (i = 0; i < 8; ++i) 187 res |= (w1_touch_bit(dev,1) << i); 188 189 return res; 190} 191 192/** 193 * Writes a series of bytes. 194 * 195 * @param dev the master device 196 * @param buf pointer to the data to write 197 * @param len the number of bytes to write 198 * @return the byte read 199 */ 200void w1_write_block(struct w1_master *dev, const u8 *buf, int len) 201{ 202 int i; 203 204 if (dev->bus_master->write_block) 205 dev->bus_master->write_block(dev->bus_master->data, buf, len); 206 else 207 for (i = 0; i < len; ++i) 208 w1_write_8(dev, buf[i]); 209} 210 211/** 212 * Reads a series of bytes. 213 * 214 * @param dev the master device 215 * @param buf pointer to the buffer to fill 216 * @param len the number of bytes to read 217 * @return the number of bytes read 218 */ 219u8 w1_read_block(struct w1_master *dev, u8 *buf, int len) 220{ 221 int i; 222 u8 ret; 223 224 if (dev->bus_master->read_block) 225 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len); 226 else { 227 for (i = 0; i < len; ++i) 228 buf[i] = w1_read_8(dev); 229 ret = len; 230 } 231 232 return ret; 233} 234 235/** 236 * Issues a reset bus sequence. 237 * 238 * @param dev The bus master pointer 239 * @return 0=Device present, 1=No device present or error 240 */ 241int w1_reset_bus(struct w1_master *dev) 242{ 243 int result; 244 245 if (dev->bus_master->reset_bus) 246 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; 247 else { 248 dev->bus_master->write_bit(dev->bus_master->data, 0); 249 w1_delay(480); 250 dev->bus_master->write_bit(dev->bus_master->data, 1); 251 w1_delay(70); 252 253 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; 254 w1_delay(410); 255 } 256 257 return result; 258} 259 260u8 w1_calc_crc8(u8 * data, int len) 261{ 262 u8 crc = 0; 263 264 while (len--) 265 crc = w1_crc8_table[crc ^ *data++]; 266 267 return crc; 268} 269 270void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb) 271{ 272 dev->attempts++; 273 if (dev->bus_master->search) 274 dev->bus_master->search(dev->bus_master->data, search_type, cb); 275 else 276 w1_search(dev, search_type, cb); 277} 278 279/** 280 * Resets the bus and then selects the slave by sending either a skip rom 281 * or a rom match. 282 * The w1 master lock must be held. 283 * 284 * @param sl the slave to select 285 * @return 0=success, anything else=error 286 */ 287int w1_reset_select_slave(struct w1_slave *sl) 288{ 289 if (w1_reset_bus(sl->master)) 290 return -1; 291 292 if (sl->master->slave_count == 1) 293 w1_write_8(sl->master, W1_SKIP_ROM); 294 else { 295 u8 match[9] = {W1_MATCH_ROM, }; 296 memcpy(&match[1], (u8 *)&sl->reg_num, 8); 297 w1_write_block(sl->master, match, 9); 298 } 299 return 0; 300} 301 302EXPORT_SYMBOL_GPL(w1_calc_crc8); 303