Lines Matching refs:end
178 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
184 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
190 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
209 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
215 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
221 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
227 .end = DA850_TPCC1_BASE + SZ_32K - 1,
233 .end = DA850_TPTC2_BASE + SZ_1K - 1,
298 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
303 .end = IRQ_DA8XX_I2CINT0,
318 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
323 .end = IRQ_DA8XX_I2CINT1,
354 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
379 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
384 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
389 .end = IRQ_DA8XX_C0_RX_PULSE,
394 .end = IRQ_DA8XX_C0_TX_PULSE,
399 .end = IRQ_DA8XX_C0_MISC_PULSE,
425 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
456 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
462 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
468 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
484 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
490 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
496 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
566 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
571 .end = IRQ_DA8XX_LCDINT,
592 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
597 .end = IRQ_DA8XX_MMCSDINT0,
602 .end = DA8XX_DMA_MMCSD0_RX,
607 .end = DA8XX_DMA_MMCSD0_TX,
629 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
634 .end = IRQ_DA850_MMCSDINT0_1,
639 .end = DA850_DMA_MMCSD1_RX,
644 .end = DA850_DMA_MMCSD1_TX,
666 .end = DA8XX_RTC_BASE + SZ_4K - 1,
671 .end = IRQ_DA8XX_RTC,
676 .end = IRQ_DA8XX_RTC,
727 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
757 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
762 .end = IRQ_DA8XX_SPINT0,
767 .end = DA8XX_DMA_SPI0_RX,
772 .end = DA8XX_DMA_SPI0_TX,
780 .end = DA830_SPI1_BASE + SZ_4K - 1,
785 .end = IRQ_DA8XX_SPINT1,
790 .end = DA8XX_DMA_SPI1_RX,
795 .end = DA8XX_DMA_SPI1_TX,
851 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
862 .end = DA850_SATA_BASE + 0x1fff,