Lines Matching refs:base
77 #define ATAPI_GET_CONTROL(base)\
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
87 #define ATAPI_GET_DEV_TXBUF(base)\
88 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
89 #define ATAPI_SET_DEV_TXBUF(base, val)\
90 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
91 #define ATAPI_GET_DEV_RXBUF(base)\
92 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
93 #define ATAPI_SET_DEV_RXBUF(base, val)\
94 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
95 #define ATAPI_GET_INT_MASK(base)\
96 bfin_read16(base + ATAPI_OFFSET_INT_MASK)
97 #define ATAPI_SET_INT_MASK(base, val)\
98 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
99 #define ATAPI_GET_INT_STATUS(base)\
100 bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
101 #define ATAPI_SET_INT_STATUS(base, val)\
102 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
103 #define ATAPI_GET_XFER_LEN(base)\
104 bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
105 #define ATAPI_SET_XFER_LEN(base, val)\
106 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
107 #define ATAPI_GET_LINE_STATUS(base)\
108 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
109 #define ATAPI_GET_SM_STATE(base)\
110 bfin_read16(base + ATAPI_OFFSET_SM_STATE)
111 #define ATAPI_GET_TERMINATE(base)\
112 bfin_read16(base + ATAPI_OFFSET_TERMINATE)
113 #define ATAPI_SET_TERMINATE(base, val)\
114 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
115 #define ATAPI_GET_PIO_TFRCNT(base)\
116 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
117 #define ATAPI_GET_DMA_TFRCNT(base)\
118 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
119 #define ATAPI_GET_UMAIN_TFRCNT(base)\
120 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
121 #define ATAPI_GET_UDMAOUT_TFRCNT(base)\
122 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
123 #define ATAPI_GET_REG_TIM_0(base)\
124 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
125 #define ATAPI_SET_REG_TIM_0(base, val)\
126 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
127 #define ATAPI_GET_PIO_TIM_0(base)\
128 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
129 #define ATAPI_SET_PIO_TIM_0(base, val)\
130 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
131 #define ATAPI_GET_PIO_TIM_1(base)\
132 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
133 #define ATAPI_SET_PIO_TIM_1(base, val)\
134 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
135 #define ATAPI_GET_MULTI_TIM_0(base)\
136 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
137 #define ATAPI_SET_MULTI_TIM_0(base, val)\
138 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
139 #define ATAPI_GET_MULTI_TIM_1(base)\
140 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
141 #define ATAPI_SET_MULTI_TIM_1(base, val)\
142 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
143 #define ATAPI_GET_MULTI_TIM_2(base)\
144 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
145 #define ATAPI_SET_MULTI_TIM_2(base, val)\
146 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
147 #define ATAPI_GET_ULTRA_TIM_0(base)\
148 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
149 #define ATAPI_SET_ULTRA_TIM_0(base, val)\
150 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
151 #define ATAPI_GET_ULTRA_TIM_1(base)\
152 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
153 #define ATAPI_SET_ULTRA_TIM_1(base, val)\
154 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
155 #define ATAPI_GET_ULTRA_TIM_2(base)\
156 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
157 #define ATAPI_SET_ULTRA_TIM_2(base, val)\
158 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
159 #define ATAPI_GET_ULTRA_TIM_3(base)\
160 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
161 #define ATAPI_SET_ULTRA_TIM_3(base, val)\
162 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
292 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
339 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
340 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
341 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
343 ATAPI_SET_CONTROL(base,
344 ATAPI_GET_CONTROL(base) | IORDY_EN);
346 ATAPI_SET_CONTROL(base,
347 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
351 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
371 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
418 ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack));
419 ATAPI_SET_ULTRA_TIM_1(base,
421 ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss));
422 ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah));
464 ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td));
465 ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw));
466 ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th));
480 static inline void wait_complete(void __iomem *base, unsigned short mask)
488 status = ATAPI_GET_INT_STATUS(base) & mask;
493 ATAPI_SET_INT_STATUS(base, mask);
504 static void write_atapi_register(void __iomem *base,
510 ATAPI_SET_DEV_TXBUF(base, value);
515 ATAPI_SET_DEV_ADDR(base, ata_reg);
519 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
522 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
525 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
530 wait_complete(base, PIO_DONE_INT);
541 static unsigned short read_atapi_register(void __iomem *base,
547 ATAPI_SET_DEV_ADDR(base, ata_reg);
551 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
554 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
557 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
563 wait_complete(base, PIO_DONE_INT);
568 return ATAPI_GET_DEV_RXBUF(base);
579 static void write_atapi_data(void __iomem *base,
585 ATAPI_SET_XFER_LEN(base, 1);
590 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
594 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
597 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
603 ATAPI_SET_DEV_TXBUF(base, buf[i]);
606 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
612 wait_complete(base, PIO_DONE_INT);
624 static void read_atapi_data(void __iomem *base,
630 ATAPI_SET_XFER_LEN(base, 1);
635 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
639 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
642 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
646 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
652 wait_complete(base, PIO_DONE_INT);
657 buf[i] = ATAPI_GET_DEV_RXBUF(base);
671 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
675 write_atapi_register(base, ATA_REG_CTRL, tf->ctl);
682 write_atapi_register(base, ATA_REG_FEATURE,
684 write_atapi_register(base, ATA_REG_NSECT,
686 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
687 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
688 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
698 write_atapi_register(base, ATA_REG_FEATURE, tf->feature);
699 write_atapi_register(base, ATA_REG_NSECT, tf->nsect);
700 write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
701 write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
702 write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
712 write_atapi_register(base, ATA_REG_DEVICE, tf->device);
728 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
729 return read_atapi_register(base, ATA_REG_STATUS);
742 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
745 tf->feature = read_atapi_register(base, ATA_REG_ERR);
746 tf->nsect = read_atapi_register(base, ATA_REG_NSECT);
747 tf->lbal = read_atapi_register(base, ATA_REG_LBAL);
748 tf->lbam = read_atapi_register(base, ATA_REG_LBAM);
749 tf->lbah = read_atapi_register(base, ATA_REG_LBAH);
750 tf->device = read_atapi_register(base, ATA_REG_DEVICE);
753 write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB);
754 tf->hob_feature = read_atapi_register(base, ATA_REG_ERR);
755 tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT);
756 tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL);
757 tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM);
758 tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH);
773 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
776 write_atapi_register(base, ATA_REG_CMD, tf->command);
787 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
788 return read_atapi_register(base, ATA_REG_ALTSTATUS);
801 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
809 write_atapi_register(base, ATA_REG_DEVICE, tmp);
821 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
822 write_atapi_register(base, ATA_REG_CTRL, ctl);
836 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
886 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
890 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
895 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
898 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
901 ATAPI_SET_XFER_LEN(base, size >> 1);
914 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
923 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
926 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
968 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
973 write_atapi_register(base, ATA_REG_NSECT, 0x55);
974 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
976 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
977 write_atapi_register(base, ATA_REG_LBAL, 0x55);
979 write_atapi_register(base, ATA_REG_NSECT, 0x55);
980 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
982 nsect = read_atapi_register(base, ATA_REG_NSECT);
983 lbal = read_atapi_register(base, ATA_REG_LBAL);
999 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1018 nsect = read_atapi_register(base, ATA_REG_NSECT);
1019 lbal = read_atapi_register(base, ATA_REG_LBAL);
1048 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1051 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1053 write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST);
1055 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1132 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1134 if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON))
1136 if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT)
1158 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1164 read_atapi_data(base, words, buf16);
1166 write_atapi_data(base, words, buf16);
1174 read_atapi_data(base, 1, align_buf);
1178 write_atapi_data(base, 1, align_buf);
1195 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1198 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
1228 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1245 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1464 void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr;
1469 ATAPI_SET_INT_MASK(base, 0);
1473 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
1477 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
1483 status = read_atapi_register(base, ATA_REG_STATUS);
1487 ATAPI_SET_INT_MASK(base, 1);
1560 * Get the register base first