Cross Reference: /drivers/char/mbcs.c

Lines Matching defs:mmr_base
203 	void *mmr_base;
208 	mmr_base = soft->mmr_base;
219 	mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
233 	cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
235 	MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
243 	void *mmr_base;
248 	mmr_base = soft->mmr_base;
259 	mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr),
273 	cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
275 	MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
284 	void *mmr_base = soft->mmr_base;
292 	mbcs_algo_set(mmr_base,
299 	cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
302 	MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
483 	uint64_t mmr_base;
485 	mmr_base = (uint64_t) (soft->mmr_base + offset);
487 	return mmr_base;
531 	void *mmr_base;
535 	mmr_base = soft->mmr_base;
536 	cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS);
541 		    MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
543 		MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
551 		    MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
553 		MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
561 		    MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
563 		MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
671 	void *mmr_base = soft->mmr_base;
677 	    MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT);
680 	MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT,
687 	err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT);
688 	MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat);
689 	MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1);
693 	MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL);
696 	cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
702 	MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
764 	soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid);