Cross Reference: /drivers/clocksource/dw_apb

Lines Matching refs:ctrl
65 	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
67 	ctrl |= APBTMR_CONTROL_INT;
68 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
106 	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
109 	ctrl &= ~APBTMR_CONTROL_INT;
110 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
116 	unsigned long ctrl;
126 		ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
127 		ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
128 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
133 		ctrl &= ~APBTMR_CONTROL_ENABLE;
134 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
138 		ctrl |= APBTMR_CONTROL_ENABLE;
139 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
143 		ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
149 		ctrl &= ~APBTMR_CONTROL_ENABLE;
150 		ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
152 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
154 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
161 		ctrl &= ~APBTMR_CONTROL_INT;
162 		ctrl |= APBTMR_CONTROL_ENABLE;
163 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
168 		ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
169 		ctrl &= ~APBTMR_CONTROL_ENABLE;
170 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
182 	unsigned long ctrl;
186 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
187 	ctrl &= ~APBTMR_CONTROL_ENABLE;
188 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
191 	ctrl |= APBTMR_CONTROL_ENABLE;
192 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
306 	unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
308 	ctrl &= ~APBTMR_CONTROL_ENABLE;
309 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
312 	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
313 	ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
314 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);