Cross Reference: /drivers/edac/i5100

Lines Matching refs:priv
347 	const struct i5100_priv *priv = mci->pvt_info;
352 		const int numrank = priv->dimm_numrank[chan][i];
355 			if (priv->dimm_csmap[i][j] == rank)
400 	const struct i5100_priv *priv = mci->pvt_info;
402 	return csrow % priv->ranksperchan;
408 	const struct i5100_priv *priv = mci->pvt_info;
410 	return csrow / priv->ranksperchan;
416 	const struct i5100_priv *priv = mci->pvt_info;
418 	return chan * priv->ranksperchan + rank;
467 	struct i5100_priv *priv = mci->pvt_info;
468 	struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
537 	struct i5100_priv *priv = mci->pvt_info;
540 	pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
543 		pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
549 		pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
551 	pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
565 	struct i5100_priv *priv = container_of(i5100_scrubbing,
570 	pci_read_config_dword(priv->mc, I5100_MC, &dw);
572 	if (priv->scrub_enable) {
574 		pci_read_config_dword(priv->mc, I5100_MC, &dw);
578 			pci_write_config_dword(priv->mc, I5100_MC, dw);
579 			pci_read_config_dword(priv->mc, I5100_MC, &dw);
582 		schedule_delayed_work(&(priv->i5100_scrubbing),
591 	struct i5100_priv *priv = mci->pvt_info;
594 	pci_read_config_dword(priv->mc, I5100_MC, &dw);
596 		priv->scrub_enable = 1;
598 		schedule_delayed_work(&(priv->i5100_scrubbing),
601 		priv->scrub_enable = 0;
603 		cancel_delayed_work(&(priv->i5100_scrubbing));
605 	pci_write_config_dword(priv->mc, I5100_MC, dw);
607 	pci_read_config_dword(priv->mc, I5100_MC, &dw);
616 	struct i5100_priv *priv = mci->pvt_info;
619 	pci_read_config_dword(priv->mc, I5100_MC, &dw);
646 	struct i5100_priv *priv = mci->pvt_info;
652 	if (!priv->mtr[chan][chan_rank].present)
657 		priv->mtr[chan][chan_rank].numcol +
658 		priv->mtr[chan][chan_rank].numrow +
659 		priv->mtr[chan][chan_rank].numbank;
667 	struct i5100_priv *priv = mci->pvt_info;
668 	struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
683 			priv->mtr[i][j].present = i5100_mtr_present(w);
684 			priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
685 			priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
686 			priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
687 			priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
688 			priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
700 	struct i5100_priv *priv = mci->pvt_info;
704 	pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
708 	pci_write_config_dword(priv->mc, I5100_SPDCMD,
716 		pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
739 	struct i5100_priv *priv = mci->pvt_info;
746 			priv->dimm_csmap[i][j] = -1; /* default NC */
750 	if (priv->ranksperchan == 4) {
751 		priv->dimm_csmap[0][0] = 0;
752 		priv->dimm_csmap[0][1] = 3;
753 		priv->dimm_csmap[1][0] = 1;
754 		priv->dimm_csmap[1][1] = 2;
755 		priv->dimm_csmap[2][0] = 2;
756 		priv->dimm_csmap[3][0] = 3;
758 		priv->dimm_csmap[0][0] = 0;
759 		priv->dimm_csmap[0][1] = 1;
760 		priv->dimm_csmap[1][0] = 2;
761 		priv->dimm_csmap[1][1] = 3;
762 		priv->dimm_csmap[2][0] = 4;
763 		priv->dimm_csmap[2][1] = 5;
770 	struct i5100_priv *priv = mci->pvt_info;
780 				priv->dimm_numrank[i][j] = 0;
782 				priv->dimm_numrank[i][j] = (rank & 3) + 1;
794 	struct i5100_priv *priv = mci->pvt_info;
795 	struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
799 	priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
802 	priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
803 	priv->mir[0].way[1] = i5100_mir_way1(w);
804 	priv->mir[0].way[0] = i5100_mir_way0(w);
807 	priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
808 	priv->mir[1].way[1] = i5100_mir_way1(w);
809 	priv->mir[1].way[0] = i5100_mir_way0(w);
812 	priv->amir[0] = w;
814 	priv->amir[1] = w;
824 			priv->dmir[i][j].limit =
827 				priv->dmir[i][j].rank[k] =
839 	struct i5100_priv *priv = mci->pvt_info;
861 			(priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8;
884 	struct i5100_priv *priv;
944 	mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0);
952 	priv = mci->pvt_info;
953 	priv->ranksperchan = ranksperch;
954 	priv->mc = pdev;
955 	priv->ch0mm = ch0mm;
956 	priv->ch1mm = ch1mm;
958 	INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
963 		priv->scrub_enable = 1;
964 		schedule_delayed_work(&(priv->i5100_scrubbing),
1004 	priv->scrub_enable = 0;
1005 	cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1030 	struct i5100_priv *priv;
1037 	priv = mci->pvt_info;
1039 	priv->scrub_enable = 0;
1040 	cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1043 	pci_disable_device(priv->ch0mm);
1044 	pci_disable_device(priv->ch1mm);
1045 	pci_dev_put(priv->ch0mm);
1046 	pci_dev_put(priv->ch1mm);