Cross Reference: /drivers/edac/mce

Lines Matching refs:ec
142 static bool f12h_dc_mce(u16 ec, u8 xec)
146 	if (MEM_ERROR(ec)) {
147 		u8 ll = LL(ec);
153 			pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
160 static bool f10h_dc_mce(u16 ec, u8 xec)
162 	if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
166 	return f12h_dc_mce(ec, xec);
169 static bool k8_dc_mce(u16 ec, u8 xec)
171 	if (BUS_ERROR(ec)) {
176 	return f10h_dc_mce(ec, xec);
179 static bool f14h_dc_mce(u16 ec, u8 xec)
181 	u8 r4	 = R4(ec);
184 	if (MEM_ERROR(ec)) {
186 		if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
204 	} else if (BUS_ERROR(ec)) {
206 		if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
231 static bool f15h_dc_mce(u16 ec, u8 xec)
235 	if (MEM_ERROR(ec)) {
266 	} else if (BUS_ERROR(ec)) {
280 	u16 ec = EC(m->status);
286 	if (TLB_ERROR(ec)) {
287 		if (TT(ec) == TT_DATA) {
288 			pr_cont("%s TLB %s.\n", LL_MSG(ec),
293 	} else if (fam_ops->dc_mce(ec, xec))
299 static bool k8_ic_mce(u16 ec, u8 xec)
301 	u8 ll	 = LL(ec);
304 	if (!MEM_ERROR(ec))
310 		switch (R4(ec)) {
333 static bool f14h_ic_mce(u16 ec, u8 xec)
335 	u8 r4    = R4(ec);
338 	if (MEM_ERROR(ec)) {
339 		if (TT(ec) != 0 || LL(ec) != 1)
352 static bool f15h_ic_mce(u16 ec, u8 xec)
356 	if (!MEM_ERROR(ec))
384 	u16 ec = EC(m->status);
389 	if (TLB_ERROR(ec))
390 		pr_cont("%s TLB %s.\n", LL_MSG(ec),
392 	else if (BUS_ERROR(ec)) {
396 	} else if (fam_ops->ic_mce(ec, xec))
404 	u16 ec = EC(m->status);
413 	else if (xec == 0x2 && MEM_ERROR(ec))
414 		pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
416 		if (TLB_ERROR(ec))
418 				"Guest TLB.\n", TT_MSG(ec));
419 		else if (BUS_ERROR(ec))
421 				R4_MSG(ec), PP_MSG(ec));
422 		else if (MEM_ERROR(ec)) {
423 			u8 r4 = R4(ec);
427 					R4_MSG(ec));
430 					"access from L2.\n", R4_MSG(ec));
446 	u16 ec = EC(m->status);
451 	if (TLB_ERROR(ec)) {
458 	} else if (BUS_ERROR(ec)) {
463 	} else if (MEM_ERROR(ec)) {
486 	u16 ec = EC(m->status);
498 		u8 r4 = R4(ec);
500 		if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
503 		pr_cont(" during %s.\n", R4_MSG(ec));
517 	u16 ec = EC(m->status);
541 		if (TLB_ERROR(ec))
543 		else if (BUS_ERROR(ec))
636 static inline void amd_decode_err_code(u16 ec)
639 	pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
641 	if (BUS_ERROR(ec))
642 		pr_cont(", mem/io: %s", II_MSG(ec));
644 		pr_cont(", tx: %s", TT_MSG(ec));
646 	if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
647 		pr_cont(", mem-tx: %s", R4_MSG(ec));
649 		if (BUS_ERROR(ec))
650 			pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));