Lines Matching refs:base
54 void __iomem *reg = chip->base + 0x08;
69 void __iomem *reg = chip->base + 0x08;
123 void __iomem *reg = chip->base + 0x08;
141 void __iomem *reg = chip->base + 0x08;
211 void __iomem *reg = chip->base;
246 con = __raw_readl(chip->base);
274 void __iomem *reg = chip->base;
309 void __iomem *reg = chip->base;
339 void __iomem *reg = chip->base;
379 con = __raw_readl(chip->base);
392 void __iomem *reg = chip->base;
522 * base + 0x00: Control register, 2 bits per gpio
525 * base + 0x04: Data register, 1 bit per gpio
532 void __iomem *base = ourchip->base;
538 con = __raw_readl(base + 0x00);
541 __raw_writel(con, base + 0x00);
551 void __iomem *base = ourchip->base;
558 dat = __raw_readl(base + 0x04);
562 __raw_writel(dat, base + 0x04);
564 con = __raw_readl(base + 0x00);
568 __raw_writel(con, base + 0x00);
569 __raw_writel(dat, base + 0x04);
580 * base + 0x00: Control register, 4 bits per gpio
583 * base + 0x04: Data register, 1 bit per gpio
586 * Note, since the data register is one bit per gpio and is at base + 0x4
595 void __iomem *base = ourchip->base;
598 con = __raw_readl(base + GPIOCON_OFF);
600 __raw_writel(con, base + GPIOCON_OFF);
602 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
611 void __iomem *base = ourchip->base;
615 con = __raw_readl(base + GPIOCON_OFF);
619 dat = __raw_readl(base + GPIODAT_OFF);
626 __raw_writel(dat, base + GPIODAT_OFF);
627 __raw_writel(con, base + GPIOCON_OFF);
628 __raw_writel(dat, base + GPIODAT_OFF);
630 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
643 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
646 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
649 * base + 0x08: Data register, 1 bit per gpio
653 * routines we store the 'base + 0x4' address so that these routines see
654 * the data register at ourchip->base + 0x04.
661 void __iomem *base = ourchip->base;
662 void __iomem *regcon = base;
674 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
683 void __iomem *base = ourchip->base;
684 void __iomem *regcon = base;
698 dat = __raw_readl(base + GPIODAT_OFF);
705 __raw_writel(dat, base + GPIODAT_OFF);
707 __raw_writel(dat, base + GPIODAT_OFF);
709 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
726 void __iomem *base = ourchip->base;
733 con = __raw_readl(base + 0x00);
734 dat = __raw_readl(base + 0x04);
740 __raw_writel(dat, base + 0x04);
744 __raw_writel(con, base + 0x00);
745 __raw_writel(dat, base + 0x04);
758 void __iomem *base = ourchip->base;
759 void __iomem *regcon = base;
794 void __iomem *base = ourchip->base;
795 void __iomem *regcon = base;
823 dat = __raw_readl(base + GPIODAT_OFF);
830 __raw_writel(dat, base + GPIODAT_OFF);
841 void __iomem *base = ourchip->base;
847 dat = __raw_readl(base + 0x04);
851 __raw_writel(dat, base + 0x04);
861 val = __raw_readl(ourchip->base + 0x04);
888 gpn = chip->chip.base;
911 BUG_ON(!chip->base);
942 int nr_chips, void __iomem *base)
949 if (chip->chip.base >= S3C_GPIO_END)
956 if ((base != NULL) && (chip->base == NULL))
957 chip->base = base + ((i) * 0x10);
969 int nr_chips, void __iomem *base,
982 if ((base != NULL) && (chip->base == NULL))
983 chip->base = base + ((i) * offset);
1006 int nr_chips, void __iomem *base)
1018 if ((base != NULL) && (chip->base == NULL))
1019 chip->base = base + ((i) * 0x20);
1092 .base = S3C2410_GPA(0),
1101 .base = S3C2410_GPB(0),
1108 .base = S3C2410_GPC(0),
1115 .base = S3C2410_GPD(0),
1122 .base = S3C2410_GPE(0),
1129 .base = S3C2410_GPF(0),
1138 .base = S3C2410_GPG(0),
1146 .base = S3C2410_GPH(0),
1154 .base = S3C2440_GPJCON,
1156 .base = S3C2410_GPJ(0),
1162 .base = S3C2443_GPKCON,
1164 .base = S3C2410_GPK(0),
1170 .base = S3C2443_GPLCON,
1172 .base = S3C2410_GPL(0),
1178 .base = S3C2443_GPMCON,
1180 .base = S3C2410_GPM(0),
1219 .base = S3C64XX_GPA(0),
1225 .base = S3C64XX_GPB(0),
1231 .base = S3C64XX_GPC(0),
1237 .base = S3C64XX_GPD(0),
1244 .base = S3C64XX_GPE(0),
1249 .base = S3C64XX_GPG_BASE,
1251 .base = S3C64XX_GPG(0),
1256 .base = S3C64XX_GPM_BASE,
1259 .base = S3C64XX_GPM(0),
1271 .base = S3C64XX_GPH_BASE + 0x4,
1273 .base = S3C64XX_GPH(0),
1278 .base = S3C64XX_GPK_BASE + 0x4,
1281 .base = S3C64XX_GPK(0),
1286 .base = S3C64XX_GPL_BASE + 0x4,
1289 .base = S3C64XX_GPL(0),
1301 .base = S3C64XX_GPF_BASE,
1304 .base = S3C64XX_GPF(0),
1311 .base = S3C64XX_GPI(0),
1318 .base = S3C64XX_GPJ(0),
1325 .base = S3C64XX_GPO(0),
1332 .base = S3C64XX_GPP(0),
1339 .base = S3C64XX_GPQ(0),
1344 .base = S3C64XX_GPN_BASE,
1348 .base = S3C64XX_GPN(0),
1378 .base = S5P6440_GPA(0),
1384 .base = S5P6440_GPB(0),
1390 .base = S5P6440_GPC(0),
1395 .base = S5P64X0_GPG_BASE,
1397 .base = S5P6440_GPG(0),
1408 .base = S5P64X0_GPH_BASE + 0x4,
1410 .base = S5P6440_GPH(0),
1421 .base = S5P64X0_GPR_BASE + 0x4,
1424 .base = S5P6440_GPR(0),
1435 .base = S5P64X0_GPF_BASE,
1438 .base = S5P6440_GPF(0),
1443 .base = S5P64X0_GPI_BASE,
1446 .base = S5P6440_GPI(0),
1451 .base = S5P64X0_GPJ_BASE,
1454 .base = S5P6440_GPJ(0),
1459 .base = S5P64X0_GPN_BASE,
1462 .base = S5P6440_GPN(0),
1467 .base = S5P64X0_GPP_BASE,
1470 .base = S5P6440_GPP(0),
1506 .base = S5P6450_GPA(0),
1512 .base = S5P6450_GPB(0),
1518 .base = S5P6450_GPC(0),
1524 .base = S5P6450_GPD(0),
1529 .base = S5P6450_GPK_BASE,
1531 .base = S5P6450_GPK(0),
1542 .base = S5P64X0_GPG_BASE + 0x4,
1544 .base = S5P6450_GPG(0),
1549 .base = S5P64X0_GPH_BASE + 0x4,
1551 .base = S5P6450_GPH(0),
1562 .base = S5P64X0_GPR_BASE + 0x4,
1565 .base = S5P6450_GPR(0),
1576 .base = S5P64X0_GPF_BASE,
1579 .base = S5P6450_GPF(0),
1584 .base = S5P64X0_GPI_BASE,
1587 .base = S5P6450_GPI(0),
1592 .base = S5P64X0_GPJ_BASE,
1595 .base = S5P6450_GPJ(0),
1600 .base = S5P64X0_GPN_BASE,
1603 .base = S5P6450_GPN(0),
1608 .base = S5P64X0_GPP_BASE,
1611 .base = S5P6450_GPP(0),
1616 .base = S5P6450_GPQ_BASE,
1619 .base = S5P6450_GPQ(0),
1624 .base = S5P6450_GPS_BASE,
1627 .base = S5P6450_GPS(0),
1678 .base = S5PC100_GPA0(0),
1684 .base = S5PC100_GPA1(0),
1690 .base = S5PC100_GPB(0),
1696 .base = S5PC100_GPC(0),
1702 .base = S5PC100_GPD(0),
1708 .base = S5PC100_GPE0(0),
1714 .base = S5PC100_GPE1(0),
1720 .base = S5PC100_GPF0(0),
1726 .base = S5PC100_GPF1(0),
1732 .base = S5PC100_GPF2(0),
1738 .base = S5PC100_GPF3(0),
1744 .base = S5PC100_GPG0(0),
1750 .base = S5PC100_GPG1(0),
1756 .base = S5PC100_GPG2(0),
1762 .base = S5PC100_GPG3(0),
1768 .base = S5PC100_GPI(0),
1774 .base = S5PC100_GPJ0(0),
1780 .base = S5PC100_GPJ1(0),
1786 .base = S5PC100_GPJ2(0),
1792 .base = S5PC100_GPJ3(0),
1798 .base = S5PC100_GPJ4(0),
1804 .base = S5PC100_GPK0(0),
1810 .base = S5PC100_GPK1(0),
1816 .base = S5PC100_GPK2(0),
1822 .base = S5PC100_GPK3(0),
1828 .base = S5PC100_GPL0(0),
1834 .base = S5PC100_GPL1(0),
1840 .base = S5PC100_GPL2(0),
1846 .base = S5PC100_GPL3(0),
1852 .base = S5PC100_GPL4(0),
1857 .base = (S5P_VA_GPIO + 0xC00),
1860 .base = S5PC100_GPH0(0),
1866 .base = (S5P_VA_GPIO + 0xC20),
1869 .base = S5PC100_GPH1(0),
1875 .base = (S5P_VA_GPIO + 0xC40),
1878 .base = S5PC100_GPH2(0),
1884 .base = (S5P_VA_GPIO + 0xC60),
1887 .base = S5PC100_GPH3(0),
1902 * The 'base' member is also initialized in the init function below.
1903 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1911 .base = S5PV210_GPA0(0),
1917 .base = S5PV210_GPA1(0),
1923 .base = S5PV210_GPB(0),
1929 .base = S5PV210_GPC0(0),
1935 .base = S5PV210_GPC1(0),
1941 .base = S5PV210_GPD0(0),
1947 .base = S5PV210_GPD1(0),
1953 .base = S5PV210_GPE0(0),
1959 .base = S5PV210_GPE1(0),
1965 .base = S5PV210_GPF0(0),
1971 .base = S5PV210_GPF1(0),
1977 .base = S5PV210_GPF2(0),
1983 .base = S5PV210_GPF3(0),
1989 .base = S5PV210_GPG0(0),
1995 .base = S5PV210_GPG1(0),
2001 .base = S5PV210_GPG2(0),
2007 .base = S5PV210_GPG3(0),
2013 .base = S5PV210_GPI(0),
2019 .base = S5PV210_GPJ0(0),
2025 .base = S5PV210_GPJ1(0),
2031 .base = S5PV210_GPJ2(0),
2037 .base = S5PV210_GPJ3(0),
2043 .base = S5PV210_GPJ4(0),
2049 .base = S5PV210_MP01(0),
2055 .base = S5PV210_MP02(0),
2061 .base = S5PV210_MP03(0),
2067 .base = S5PV210_MP04(0),
2073 .base = S5PV210_MP05(0),
2078 .base = (S5P_VA_GPIO + 0xC00),
2081 .base = S5PV210_GPH0(0),
2087 .base = (S5P_VA_GPIO + 0xC20),
2090 .base = S5PV210_GPH1(0),
2096 .base = (S5P_VA_GPIO + 0xC40),
2099 .base = S5PV210_GPH2(0),
2105 .base = (S5P_VA_GPIO + 0xC60),
2108 .base = S5PV210_GPH3(0),
2123 * The 'base' member is also initialized in the init function below.
2124 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2132 .base = EXYNOS4_GPA0(0),
2138 .base = EXYNOS4_GPA1(0),
2144 .base = EXYNOS4_GPB(0),
2150 .base = EXYNOS4_GPC0(0),
2156 .base = EXYNOS4_GPC1(0),
2162 .base = EXYNOS4_GPD0(0),
2168 .base = EXYNOS4_GPD1(0),
2174 .base = EXYNOS4_GPE0(0),
2180 .base = EXYNOS4_GPE1(0),
2186 .base = EXYNOS4_GPE2(0),
2192 .base = EXYNOS4_GPE3(0),
2198 .base = EXYNOS4_GPE4(0),
2204 .base = EXYNOS4_GPF0(0),
2210 .base = EXYNOS4_GPF1(0),
2216 .base = EXYNOS4_GPF2(0),
2222 .base = EXYNOS4_GPF3(0),
2234 .base = EXYNOS4_GPJ0(0),
2240 .base = EXYNOS4_GPJ1(0),
2246 .base = EXYNOS4_GPK0(0),
2252 .base = EXYNOS4_GPK1(0),
2258 .base = EXYNOS4_GPK2(0),
2264 .base = EXYNOS4_GPK3(0),
2270 .base = EXYNOS4_GPL0(0),
2276 .base = EXYNOS4_GPL1(0),
2282 .base = EXYNOS4_GPL2(0),
2289 .base = EXYNOS4_GPY0(0),
2296 .base = EXYNOS4_GPY1(0),
2303 .base = EXYNOS4_GPY2(0),
2310 .base = EXYNOS4_GPY3(0),
2317 .base = EXYNOS4_GPY4(0),
2324 .base = EXYNOS4_GPY5(0),
2331 .base = EXYNOS4_GPY6(0),
2339 .base = EXYNOS4_GPX0(0),
2348 .base = EXYNOS4_GPX1(0),
2357 .base = EXYNOS4_GPX2(0),
2366 .base = EXYNOS4_GPX3(0),
2379 .base = EXYNOS4_GPZ(0),
2391 .base = EXYNOS5_GPA0(0),
2397 .base = EXYNOS5_GPA1(0),
2403 .base = EXYNOS5_GPA2(0),
2409 .base = EXYNOS5_GPB0(0),
2415 .base = EXYNOS5_GPB1(0),
2421 .base = EXYNOS5_GPB2(0),
2427 .base = EXYNOS5_GPB3(0),
2433 .base = EXYNOS5_GPC0(0),
2439 .base = EXYNOS5_GPC1(0),
2445 .base = EXYNOS5_GPC2(0),
2451 .base = EXYNOS5_GPC3(0),
2457 .base = EXYNOS5_GPD0(0),
2463 .base = EXYNOS5_GPD1(0),
2469 .base = EXYNOS5_GPY0(0),
2475 .base = EXYNOS5_GPY1(0),
2481 .base = EXYNOS5_GPY2(0),
2487 .base = EXYNOS5_GPY3(0),
2493 .base = EXYNOS5_GPY4(0),
2499 .base = EXYNOS5_GPY5(0),
2505 .base = EXYNOS5_GPY6(0),
2513 .base = EXYNOS5_GPX0(0),
2522 .base = EXYNOS5_GPX1(0),
2531 .base = EXYNOS5_GPX2(0),
2540 .base = EXYNOS5_GPX3(0),
2553 .base = EXYNOS5_GPE0(0),
2559 .base = EXYNOS5_GPE1(0),
2565 .base = EXYNOS5_GPF0(0),
2571 .base = EXYNOS5_GPF1(0),
2577 .base = EXYNOS5_GPG0(0),
2583 .base = EXYNOS5_GPG1(0),
2589 .base = EXYNOS5_GPG2(0),
2595 .base = EXYNOS5_GPH0(0),
2601 .base = EXYNOS5_GPH1(0),
2614 .base = EXYNOS5_GPV0(0),
2620 .base = EXYNOS5_GPV1(0),
2626 .base = EXYNOS5_GPV2(0),
2632 .base = EXYNOS5_GPV3(0),
2638 .base = EXYNOS5_GPV4(0),
2650 .base = EXYNOS5_GPZ(0),
2674 pin = gc->base + gpiospec->args[0];
2692 u64 base, u64 offset)
2700 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2705 " with base address %08llx\n", address);
2713 u64 base, u64 offset)
2823 /* need to set base address for gpx */
2827 chip->base = gpx_base;
2881 /* need to set base address for gpx */
2885 chip->base = gpx_base;
2929 /* need to set base address for gpv */
2930 exynos5_gpios_3[0].base = gpio_base3;
2931 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2932 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2933 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2934 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
3001 offset = pin - chip->chip.base;
3050 offset = pin - chip->chip.base;
3070 offset = pin - chip->chip.base;
3088 offset = pin - chip->chip.base;
3133 unsigned long offs = pin - chip->chip.base;
3135 return __raw_readl(chip->base + 0x04) & (1 << offs);
3151 off = pin - chip->chip.base;
3153 reg = chip->base + 0x0C;
3174 off = pin - chip->chip.base;
3176 reg = chip->base + 0x0C;