Cross Reference: /drivers/gpu/drm/exynos/exynos_drm

Lines Matching refs:mode
47 convert_to_display_mode(struct drm_display_mode *mode,
53 	mode->clock = timing->pixclock / 1000;
54 	mode->vrefresh = timing->refresh;
56 	mode->hdisplay = timing->xres;
57 	mode->hsync_start = mode->hdisplay + timing->right_margin;
58 	mode->hsync_end = mode->hsync_start + timing->hsync_len;
59 	mode->htotal = mode->hsync_end + timing->left_margin;
61 	mode->vdisplay = timing->yres;
62 	mode->vsync_start = mode->vdisplay + timing->lower_margin;
63 	mode->vsync_end = mode->vsync_start + timing->vsync_len;
64 	mode->vtotal = mode->vsync_end + timing->upper_margin;
65 	mode->width_mm = panel->width_mm;
66 	mode->height_mm = panel->height_mm;
69 		mode->flags |= DRM_MODE_FLAG_INTERLACE;
72 		mode->flags |= DRM_MODE_FLAG_DBLSCAN;
78 			struct drm_display_mode *mode)
84 	timing->pixclock = mode->clock * 1000;
85 	timing->refresh = drm_mode_vrefresh(mode);
87 	timing->xres = mode->hdisplay;
88 	timing->right_margin = mode->hsync_start - mode->hdisplay;
89 	timing->hsync_len = mode->hsync_end - mode->hsync_start;
90 	timing->left_margin = mode->htotal - mode->hsync_end;
92 	timing->yres = mode->vdisplay;
93 	timing->lower_margin = mode->vsync_start - mode->vdisplay;
94 	timing->vsync_len = mode->vsync_end - mode->vsync_start;
95 	timing->upper_margin = mode->vtotal - mode->vsync_end;
97 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
102 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
127 	 * because lcd panel has only one mode.
154 		struct drm_display_mode *mode = drm_mode_create(connector->dev);
160 			drm_mode_destroy(connector->dev, mode);
164 		convert_to_display_mode(mode, panel);
165 		connector->display_info.width_mm = mode->width_mm;
166 		connector->display_info.height_mm = mode->height_mm;
168 		mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
169 		drm_mode_set_name(mode);
170 		drm_mode_probed_add(connector, mode);
179 					    struct drm_display_mode *mode)
190 	convert_to_video_timing(&timing, mode);