Lines Matching refs:mode
98 * This is used to select the color range of RBG outputs in HDMI mode.
99 * It is only valid when using TMDS encoding and 8 bit per color mode.
124 * have a valid fixed mode to use with the panel.
129 * This is sdvo fixed pannel mode pointer
533 static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
535 if (mode->clock >= 100000)
537 else if (mode->clock >= 50000)
606 int mode)
610 switch (mode) {
717 const struct drm_display_mode *mode)
723 width = mode->crtc_hdisplay;
724 height = mode->crtc_vdisplay;
726 /* do some mode translations */
727 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
728 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
730 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
731 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
733 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
734 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
736 dtd->part1.clock = mode->clock / 10;
755 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
757 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
765 static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
768 mode->hdisplay = dtd->part1.h_active;
769 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
770 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
771 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
772 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
773 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
774 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
775 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
777 mode->vdisplay = dtd->part1.v_active;
778 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
779 mode->vsync_start = mode->vdisplay;
780 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
781 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
782 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
783 mode->vsync_end = mode->vsync_start +
785 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
786 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
787 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
789 mode->clock = dtd->part1.clock * 10;
791 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
793 mode->flags |= DRM_MODE_FLAG_PHSYNC;
795 mode->flags |= DRM_MODE_FLAG_PVSYNC;
809 uint8_t mode)
811 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
815 uint8_t mode)
817 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
904 struct drm_display_mode *mode)
912 psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
921 struct drm_display_mode *mode,
929 mode->clock / 10,
930 mode->hdisplay,
931 mode->vdisplay))
945 struct drm_display_mode *mode,
957 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
961 mode,
969 mode,
983 struct drm_display_mode *mode,
996 if (!mode)
1085 static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1091 switch (mode) {
1099 DRM_DEBUG("DPMS: %d", mode);
1102 if (mode != DRM_MODE_DPMS_ON) {
1105 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
1107 if (mode == DRM_MODE_DPMS_OFF) {
1135 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
1142 struct drm_display_mode *mode)
1147 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1150 if (psb_intel_sdvo->pixel_clock_min > mode->clock)
1153 if (psb_intel_sdvo->pixel_clock_max < mode->clock)
1157 if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1160 if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1165 if ((ALIGN(mode->hdisplay * 4, 64) * mode->vdisplay) >
1574 * Attempt to get the mode list from DDC.
1587 /* Guarantee the mode is preferred */
1836 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2291 "mode", psb_intel_sdvo_connector->format_supported_num);