Cross Reference: /drivers/gpu/drm/mga/mga

Lines Matching refs:ctx
48 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
57 		DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
59 			  MGA_DWGCTL, ctx->dwgctl,
72 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
77 	DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
78 		  MGA_MACCESS, ctx->maccess,
79 		  MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
81 	DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
82 		  MGA_FOGCOL, ctx->fogcolor,
83 		  MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
85 	DMA_BLOCK(MGA_FCOL, ctx->fcol,
95 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
100 	DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
101 		  MGA_MACCESS, ctx->maccess,
102 		  MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
104 	DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
105 		  MGA_FOGCOL, ctx->fogcolor,
106 		  MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
108 	DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
109 		  MGA_TDUALSTAGE0, ctx->tdualstage0,
110 		  MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol);
112 	DMA_BLOCK(MGA_STENCIL, ctx->stencil,
113 		  MGA_STENCILCTL, ctx->stencilctl,
387 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
389 	if (ctx->dstorg != dev_priv->front_offset &&
390 	    ctx->dstorg != dev_priv->back_offset) {
392 			  ctx->dstorg, dev_priv->front_offset,
394 		ctx->dstorg = 0;
487 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
564 		  MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
575 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
615 		  MGA_PLNWT, ctx->plnwt,
616 		  MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl);
726 	drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
752 	DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
773 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
820 		  MGA_PLNWT, ctx->plnwt,
821 		  MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl);