Cross Reference: /drivers/gpu/drm/nouveau/nouveau

Lines Matching refs:head
35 void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
36 uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
37 void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
38 uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
40 void NVBlankScreen(struct drm_device *, int head, bool blank);
48 void nouveau_hw_save_state(struct drm_device *, int head,
50 void nouveau_hw_load_state(struct drm_device *, int head,
52 void nouveau_hw_load_state_palette(struct drm_device *, int head,
122 					int head, uint32_t reg)
125 	if (head)
128 	NV_REG_DEBUG(CRTC, dev, "head %d reg %08x val %08x\n", head, reg, val);
133 					int head, uint32_t reg, uint32_t val)
135 	if (head)
137 	NV_REG_DEBUG(CRTC, dev, "head %d reg %08x val %08x\n", head, reg, val);
142 					int head, uint32_t reg)
145 	if (head)
148 	NV_REG_DEBUG(RAMDAC, dev, "head %d reg %08x val %08x\n",
149 							head, reg, val);
154 					int head, uint32_t reg, uint32_t val)
156 	if (head)
158 	NV_REG_DEBUG(RAMDAC, dev, "head %d reg %08x val %08x\n",
159 							head, reg, val);
184 					int head, uint8_t index, uint8_t value)
186 	NV_REG_DEBUG(VGACRTC, dev, "head %d index 0x%02x data 0x%02x\n",
187 							head, index, value);
188 	nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
189 	nv_wr08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
193 					int head, uint8_t index)
196 	nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
197 	val = nv_rd08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
198 	NV_REG_DEBUG(VGACRTC, dev, "head %d index 0x%02x data 0x%02x\n",
199 							head, index, val);
205  * per-head variables around
218 NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value)
220 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
221 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value);
224 static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index)
226 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
227 	return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);
231 					int head, uint32_t reg)
237 	 * NVSetOwner for the relevant head to be programmed */
238 	if (head && dev_priv->card_type == NV_40)
242 	NV_REG_DEBUG(RMVIO, dev, "head %d reg %08x val %02x\n", head, reg, val);
247 					int head, uint32_t reg, uint8_t value)
252 	 * NVSetOwner for the relevant head to be programmed */
253 	if (head && dev_priv->card_type == NV_40)
256 	NV_REG_DEBUG(RMVIO, dev, "head %d reg %08x val %02x\n",
257 						head, reg, value);
261 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
263 	nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
264 	nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
267 static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
269 	nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
270 	return !(nv_rd08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
274 					int head, uint8_t index, uint8_t value)
276 	if (NVGetEnablePalette(dev, head))
281 	nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
282 	NV_REG_DEBUG(VGAATTR, dev, "head %d index 0x%02x data 0x%02x\n",
283 							head, index, value);
284 	nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
285 	nv_wr08(dev, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
289 					int head, uint8_t index)
292 	if (NVGetEnablePalette(dev, head))
297 	nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
298 	nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
299 	val = nv_rd08(dev, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
300 	NV_REG_DEBUG(VGAATTR, dev, "head %d index 0x%02x data 0x%02x\n",
301 							head, index, val);
305 static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start)
307 	NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
310 static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
312 	uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
315 		NVVgaSeqReset(dev, head, true);
316 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
319 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */
320 		NVVgaSeqReset(dev, head, false);
322 	NVSetEnablePalette(dev, head, protect);
336 /* makes cr0-7 on the specified head read-only */
338 nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)
340 	uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX);
347 	NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11);
353 nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)
369 		cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa;
371 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21);
407 nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
414 	uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS);
415 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos);
419 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
423 	NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
430 		int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);
432 		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
438 nv_show_cursor(struct drm_device *dev, int head, bool show)
442 		&dev_priv->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
448 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
451 		nv_fix_nv40_hw_cursor(dev, head);