Lines Matching refs:r2
201 mov $r2 2
202 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
213 mov $r2 0x2003 // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
214 iowr I[$r3 + 0x000] $r2
220 mov $r2 0x2004
221 iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
222 mov $r2 0x200b
223 iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
224 mov $r2 0x200c
225 iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
228 mov $r2 0xc24
229 shl b32 $r2 6
231 iowr I[$r2] $r3
234 mov $r2 -0x78fc // 0x8704
235 sethi $r2 0
236 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
240 mov $r2 4
241 iowr I[$r1] $r2
259 mov $r2 0x40c
260 shl b32 $r2 6
261 iowr I[$r2 + 0x000] $r1
262 iowr I[$r2 + 0x100] $r1
265 mov $r2 0x800
266 shl b32 $r2 6
267 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
272 cmpu b32 $r3 $r2
328 mov b32 $r15 $r2
355 mov $r2 0x800
356 shl b32 $r2 6
357 iowr I[$r2 + 0x100] $r1 // CC_SCRATCH[1] = context size
358 add b32 $r2 0x800
361 iowr I[$r2 + 0x000] $r1 // CC_SCRATCH[0] |= 0x80000000
380 iord $r2 I[$r1 + 0x100] // CHAN_NEXT
385 xbit $r3 $r2 31
387 push $r2
388 mov b32 $r2 $r1
394 pop $r2
401 push $r2
402 mov b32 $r2 $r1
406 pop $r2
409 iowr I[$r1] $r2
412 xbit $r3 $r2 31
422 mov $r2 1
423 iowr I[$r1 + 0x000] $r2 // 0x409b0c
431 mov b32 $r2 $r15
455 clear b32 $r2
456 bset $r2 31
457 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
602 // In: $r2 channel address
615 iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
619 iowr I[$r1 + 0x000] $r2 // MEM_CHAN
625 iowr I[$r3 + 0x000] $r2 // CHAN_CUR
629 bclr $r2 31
630 shl b32 $r2 4
631 add b32 $r2 2
636 iowr I[$r1 + 0x000] $r2 // MEM_BASE
639 mov $r2 0x0002
640 sethi $r2 0x80000000
641 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram
643 mov $r2 #xfer_data
644 sethi $r2 0x00020000 // 16 bytes
645 xdld $r1 $r2
652 ld b32 $r2 D[$r0 + #xfer_data + 0]
653 shr b32 $r2 8
654 or $r1 $r2
659 mov $r2 0xa04
660 shl b32 $r2 6
661 iowr I[$r2 + 0x000] $r1 // MEM_BASE
662 mov $r2 1
665 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm
680 // In: $r2 channel address
689 mov $r2 5
690 iowr I[$r1 + 0x000] $r2 // MEM_CMD = 5 (???)
692 iord $r2 I[$r1 + 0x000]
693 or $r2 $r2
710 mov $r2 0xa04
711 shl b32 $r2 6
712 iowr I[$r2 + 0x000] $r3 // MEM_BASE
738 iowr I[$r2 + 0x000] $r3 // MEM_BASE
750 // In: $r2 channel address
777 mov $r2 0x414
778 shl b32 $r2 6
779 iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
786 xbit $r2 $flags $p2
787 shl b32 $r2 1
788 or $r15 $r2
794 mov $r2 0xc
795 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
797 mov $r2 0x47fc
798 sethi $r2 0x20000
799 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
800 xbit $r2 $flags $p1
801 add b32 $r2 3
802 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
826 mov $r2 5
827 iowr I[$r1] $r2 // MEM_CMD
829 iord $r2 I[$r1]
830 or $r2 $r2