Lines Matching refs:tmp
344 u32 slice_tile_max, size, tmp;
423 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
428 tmp += track->cb_color_view[i] & 0xFF;
432 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
435 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
446 track->cb_color_bo_offset[i], tmp,
455 tmp = (height * pitch) >> 6;
456 if (tmp < slice_tile_max)
457 slice_tile_max = tmp;
458 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
460 ib[track->cb_color_size_idx[i]] = tmp;
467 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
504 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
505 tmp = (tmp / bpe) >> 6;
506 if (!tmp) {
512 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
569 tmp = ntiles * bpe * 64 * nviews;
570 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
573 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
604 tmp = track->htile_surface & 3;
610 switch (tmp) {
629 switch (tmp) {
648 switch (tmp) {
667 switch (tmp) {
712 u32 tmp;
748 tmp = track->cb_target_mask;
750 if ((tmp >> (i * 4)) & 0xF) {
1102 u32 m, i, tmp, *ib;
1137 tmp =radeon_get_ib_value(p, idx);
1198 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1199 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1201 track->vgt_strmout_bo[tmp] = reloc->robj;
1202 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1209 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1211 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1231 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1232 track->nsamples = 1 << tmp;
1250 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1251 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1254 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1257 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1260 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1261 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1273 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1274 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1285 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1286 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1287 track->cb_color_size_idx[tmp] = idx;
1307 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1309 if (!track->cb_color_base_last[tmp]) {
1313 ib[idx] = track->cb_color_base_last[tmp];
1314 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1322 track->cb_color_frag_bo[tmp] = reloc->robj;
1333 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1335 if (!track->cb_color_base_last[tmp]) {
1339 ib[idx] = track->cb_color_base_last[tmp];
1340 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1348 track->cb_color_tile_bo[tmp] = reloc->robj;
1365 tmp = (reg - CB_COLOR0_BASE) / 4;
1366 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1368 track->cb_color_base_last[tmp] = ib[idx];
1369 track->cb_color_bo[tmp] = reloc->robj;
1370 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1725 int tmp;
1733 tmp = radeon_get_ib_value(p, idx + 1);
1734 pred_op = (tmp >> 16) & 0x7;
1753 ((u64)(tmp & 0xff) << 32);
1756 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);