Lines Matching refs:tmp
127 uint32_t tmp;
131 tmp = RREG32_MC(MC_STATUS);
132 if (tmp & MC_STATUS_IDLE) {
148 unsigned pipe_select_current, gb_pipe_select, tmp;
157 tmp = RREG32(R300_DST_PIPE_CONFIG);
158 pipe_select_current = (tmp >> 2) & 3;
159 tmp = (1 << pipe_select_current) |
161 WREG32_PLL(0x000D, tmp);
174 uint32_t tmp;
178 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
179 switch (tmp) {
227 uint32_t tmp;
229 tmp = RREG32(GB_PIPE_SELECT);
230 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
231 tmp = RREG32(SU_REG_DEST);
232 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
233 tmp = RREG32(GB_TILE_CONFIG);
234 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
235 tmp = RREG32(DST_PIPE_CONFIG);
236 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
245 uint32_t tmp;
247 tmp = RREG32(0x2140);
248 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
250 tmp = RREG32(0x425C);
251 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
960 u32 tmp;
975 tmp = wm0.lb_request_fifo_depth;
976 tmp |= wm1.lb_request_fifo_depth << 16;
977 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1104 uint32_t tmp;
1121 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1122 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1123 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1125 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1127 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1128 WREG32_MC(MC_MISC_LAT_TIMER, tmp);