Lines Matching refs:tmp
414 u32 tmp;
430 tmp = 0; /* 1/2 */
432 tmp = 2; /* whole */
434 tmp = 0;
437 DC_LB_MEMORY_CONFIG(tmp));
440 switch (tmp) {
455 u32 tmp = RREG32(MC_SHARED_CHMAP);
457 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
639 u32 tmp, dmif_size = 12288;
666 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
674 lb_fill_bw = min(tmp, dfixed_trunc(b));
746 u32 tmp, arb_control3;
820 tmp = arb_control3;
821 tmp &= ~LATENCY_WATERMARK_MASK(3);
822 tmp |= LATENCY_WATERMARK_MASK(1);
823 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
828 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
829 tmp &= ~LATENCY_WATERMARK_MASK(3);
830 tmp |= LATENCY_WATERMARK_MASK(2);
831 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
1578 u32 tmp;
1662 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1663 rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
1664 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1666 si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
1674 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
1675 rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
1677 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1678 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1703 tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
1704 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
1706 tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
1707 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
1748 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1749 rdev->config.si.num_tile_pipes = (1 << tmp);
1750 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1751 rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
1752 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1753 rdev->config.si.num_shader_engines = tmp + 1;
1754 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1755 rdev->config.si.num_gpus = tmp + 1;
1756 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1757 rdev->config.si.multi_gpu_tile_size = 1 << tmp;
1758 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1759 rdev->config.si.mem_row_size_in_kb = 1 << tmp;
1859 tmp = RREG32(HDP_MISC_CNTL);
1860 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1861 WREG32(HDP_MISC_CNTL, tmp);
2082 u32 tmp;
2110 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2112 tmp |= BUF_SWAP_32BIT;
2114 WREG32(CP_RB0_CNTL, tmp);
2117 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2128 tmp |= RB_NO_UPDATE;
2133 WREG32(CP_RB0_CNTL, tmp);
2143 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2145 tmp |= BUF_SWAP_32BIT;
2147 WREG32(CP_RB1_CNTL, tmp);
2150 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2159 WREG32(CP_RB1_CNTL, tmp);
2169 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2171 tmp |= BUF_SWAP_32BIT;
2173 WREG32(CP_RB2_CNTL, tmp);
2176 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2185 WREG32(CP_RB2_CNTL, tmp);
2316 u32 tmp;
2342 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2343 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2344 WREG32(MC_VM_FB_LOCATION, tmp);
2417 u32 tmp;
2422 tmp = RREG32(MC_ARB_RAMCFG);
2423 if (tmp & CHANSIZE_OVERRIDE) {
2425 } else if (tmp & CHANSIZE_MASK) {
2430 tmp = RREG32(MC_SHARED_CHMAP);
2431 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
3111 u32 tmp;
3141 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3142 WREG32(DC_HPD1_INT_CONTROL, tmp);
3143 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3144 WREG32(DC_HPD2_INT_CONTROL, tmp);
3145 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3146 WREG32(DC_HPD3_INT_CONTROL, tmp);
3147 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3148 WREG32(DC_HPD4_INT_CONTROL, tmp);
3149 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3150 WREG32(DC_HPD5_INT_CONTROL, tmp);
3151 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3152 WREG32(DC_HPD6_INT_CONTROL, tmp);
3365 u32 tmp;
3428 tmp = RREG32(DC_HPD1_INT_CONTROL);
3429 tmp |= DC_HPDx_INT_ACK;
3430 WREG32(DC_HPD1_INT_CONTROL, tmp);
3433 tmp = RREG32(DC_HPD2_INT_CONTROL);
3434 tmp |= DC_HPDx_INT_ACK;
3435 WREG32(DC_HPD2_INT_CONTROL, tmp);
3438 tmp = RREG32(DC_HPD3_INT_CONTROL);
3439 tmp |= DC_HPDx_INT_ACK;
3440 WREG32(DC_HPD3_INT_CONTROL, tmp);
3443 tmp = RREG32(DC_HPD4_INT_CONTROL);
3444 tmp |= DC_HPDx_INT_ACK;
3445 WREG32(DC_HPD4_INT_CONTROL, tmp);
3448 tmp = RREG32(DC_HPD5_INT_CONTROL);
3449 tmp |= DC_HPDx_INT_ACK;
3450 WREG32(DC_HPD5_INT_CONTROL, tmp);
3453 tmp = RREG32(DC_HPD5_INT_CONTROL);
3454 tmp |= DC_HPDx_INT_ACK;
3455 WREG32(DC_HPD6_INT_CONTROL, tmp);
3482 u32 wptr, tmp;
3497 tmp = RREG32(IH_RB_CNTL);
3498 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3499 WREG32(IH_RB_CNTL, tmp);