Lines Matching defs:hscx

17 #include "hscx.h"
35 #define INT_HSCX_EN 0x1 /* 1 = enable IT hscx */
36 #define INT_HSCX 0x4 /* 1 = IT hscx en cours */
169 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size)
174 read_fifo(cs->hw.gazel.hscxfifo[hscx], data, size);
178 read_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size);
184 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size)
189 write_fifo(cs->hw.gazel.hscxfifo[hscx], data, size);
193 write_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size);
199 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
207 return (readreg(cs->hw.gazel.hscx[hscx], off2));
210 return (readreg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2));
216 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
224 writereg(cs->hw.gazel.hscx[hscx], off2, value);
228 writereg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2, value);
327 release_region(i + cs->hw.gazel.hscx[0], 16);
328 release_region(0xC000 + cs->hw.gazel.hscx[0], 1);
332 release_region(cs->hw.gazel.hscx[0], 0x100);
420 cs->bcs[i].hw.hscx.tsaxr0 = 0x1f;
421 cs->bcs[i].hw.hscx.tsaxr1 = 0x23;
439 base = cs->hw.gazel.hscx[0];
455 if (!request_region(adr = cs->hw.gazel.hscx[0], len = 0x100, "gazel"))
458 release_region(cs->hw.gazel.hscx[0], 0x100);
503 cs->hw.gazel.hscx[0] = card->para[1];
504 cs->hw.gazel.hscx[1] = card->para[1] + 0x4000;
507 cs->hw.gazel.hscxfifo[0] = cs->hw.gazel.hscx[0];
508 cs->hw.gazel.hscxfifo[1] = cs->hw.gazel.hscx[1];
518 "Gazel: hscx A:0x%X hscx B:0x%X\n",
519 cs->hw.gazel.hscx[0], cs->hw.gazel.hscx[1]);
589 cs->hw.gazel.hscx[0] = pci_ioaddr1;
590 cs->hw.gazel.hscx[1] = pci_ioaddr1 + 0x40;
592 cs->hw.gazel.hscxfifo[0] = cs->hw.gazel.hscx[0];
593 cs->hw.gazel.hscxfifo[1] = cs->hw.gazel.hscx[1];
606 "Gazel: hscx A:0x%X hscx B:0x%X\n",
607 cs->hw.gazel.hscx[0], cs->hw.gazel.hscx[1]);