Cross Reference: /drivers/isdn/hisax/ipacx.c

Lines Matching defs:hscx
6  * Derived from hisax_isac.c, isac.c, hscx.c and others
47 static void bch_int(struct IsdnCardState *cs, u_char hscx);
52 static void bch_init(struct IsdnCardState *cs, int hscx);
460 			bcs->hw.hscx.count = 0;
472 			bcs->hw.hscx.count = 0;
511 	u_char *ptr, hscx;
516 	hscx = bcs->hw.hscx.hscx;
521 	if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
524 		cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80);  // RMC
525 		bcs->hw.hscx.rcvidx = 0;
529 	ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
531 	while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
532 	cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80);  // RMC
534 	ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
535 	bcs->hw.hscx.rcvidx += count;
540 		t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);
554 	u_char *ptr, *p, hscx;
563 	hscx = bcs->hw.hscx.hscx;
576 	bcs->hw.hscx.count += count;
577 	while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
578 	cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
583 		t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count);
593 bch_int(struct IsdnCardState *cs, u_char hscx)
601 	bcs = cs->bcs + hscx;
602 	istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
609 		rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
613 					debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
616 					debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
619 					debugl1(cs, "bch_int() B-%d: CRC error", hscx);
620 			cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80);  // RMC
623 			count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1);
626 			if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
632 					memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
637 		bcs->hw.hscx.rcvidx = 0;
649 				memcpy(skb_put(skb, B_FIFO_SIZE), bcs->hw.hscx.rcvbuf, B_FIFO_SIZE);
652 			bcs->hw.hscx.rcvidx = 0;
659 			debugl1(cs, "bch_int() B-%d: RFO error", hscx);
660 		cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40);  // RRES
673 					bcs->ackcnt += bcs->hw.hscx.count;
679 			bcs->hw.hscx.count = 0;
683 			bcs->hw.hscx.count = 0;
699 				skb_push(bcs->tx_skb, bcs->hw.hscx.count);
700 				bcs->tx_cnt += bcs->hw.hscx.count;
701 				bcs->hw.hscx.count = 0;
703 			cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01);  // XRES
705 				debugl1(cs, "bch_int() B-%d XDU error", hscx);
716 	int hscx = bcs->hw.hscx.hscx;
720 		debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc);
725 	if (!hscx)
738 		cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0);  // rec off
739 		cs->BC_Write_Reg(cs, hscx, IPACX_EXMB,  0x30);  // std adj.
740 		cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF);  // ints off
741 		cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41);  // validate adjustments
744 		cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88);  // ext transp mode
745 		cs->BC_Write_Reg(cs, hscx, IPACX_EXMB,  0x00);  // xxx00000
746 		cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41);  // validate adjustments
747 		cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
750 		cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8);  // transp mode 0
751 		cs->BC_Write_Reg(cs, hscx, IPACX_EXMB,  0x01);  // idle=hdlc flags crc enabled
752 		cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41);  // validate adjustments
753 		cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
765 		kfree(bcs->hw.hscx.rcvbuf);
766 		bcs->hw.hscx.rcvbuf = NULL;
785 		if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
787 			       "HiSax open_bchstate(): No memory for hscx.rcvbuf\n");
795 			kfree(bcs->hw.hscx.rcvbuf);
796 			bcs->hw.hscx.rcvbuf = NULL;
805 	bcs->hw.hscx.rcvidx = 0;
828 bch_init(struct IsdnCardState *cs, int hscx)
830 	cs->bcs[hscx].BC_SetStack   = bch_setstack;
831 	cs->bcs[hscx].BC_Close      = bch_close_state;
832 	cs->bcs[hscx].hw.hscx.hscx  = hscx;
833 	cs->bcs[hscx].cs            = cs;
834 	bch_mode(cs->bcs + hscx, 0, hscx);