Lines Matching defs:cx
101 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
109 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
118 cx18_setup_page(cx, i);
121 cx18_raw_writel(cx, *src, dst);
122 if (cx18_raw_readl(cx, dst) != *src) {
125 cx18_setup_page(cx, 0);
132 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
136 cx18_setup_page(cx, SCB_OFFSET);
140 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
153 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
156 cx18_setup_page(cx, 0);
182 cx18_setup_page(cx, seghdr.addr + i);
185 cx18_raw_writel(cx, src[(offset + j) / 4],
187 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
192 cx18_setup_page(cx, 0);
199 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
204 cx18_setup_page(cx, 0);
208 void cx18_halt_firmware(struct cx18 *cx)
211 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
213 cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
217 void cx18_init_power(struct cx18 *cx, int lowpwr)
221 cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
224 cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
266 cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
267 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
270 cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
271 cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
272 cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
277 cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
278 cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
280 cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
284 cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
285 cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
286 cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
304 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
306 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
310 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
312 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
316 cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
318 cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
320 cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
322 cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
326 void cx18_init_memory(struct cx18 *cx)
329 cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
333 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
337 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
338 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
339 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
344 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
345 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
349 cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
354 cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
356 cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
359 cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
360 cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
362 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
363 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
364 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
365 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
366 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
367 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
368 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
369 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
370 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
371 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
374 int cx18_firmware_init(struct cx18 *cx)
381 cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
384 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
390 if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {
395 cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
396 cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
398 sz = load_cpu_fw_direct("v4l-cx23418-cpu.fw", cx->enc_mem, cx);
403 cx18_init_scb(cx);
406 sz = load_apu_fw_direct("v4l-cx23418-apu.fw", cx->enc_mem, cx,
412 cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,
417 retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1;
424 (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) {
438 cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
441 sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0);
446 cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);