Lines Matching refs:ctx
175 static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
178 if (ctx->src_queue_cnt >= 1 && ctx->state == MFCINST_GOT_INST)
181 if (ctx->src_queue_cnt >= 1 &&
182 ctx->state == MFCINST_RUNNING &&
183 ctx->dst_queue_cnt >= ctx->dpb_count)
186 if (ctx->state == MFCINST_FINISHING &&
187 ctx->dst_queue_cnt >= ctx->dpb_count)
190 if (ctx->src_queue_cnt >= 1 &&
191 ctx->state == MFCINST_HEAD_PARSED &&
192 ctx->capture_state == QUEUE_BUFS_MMAPED)
195 if ((ctx->state == MFCINST_RES_CHANGE_INIT ||
196 ctx->state == MFCINST_RES_CHANGE_FLUSH) &&
197 ctx->dst_queue_cnt >= ctx->dpb_count)
199 if (ctx->state == MFCINST_RES_CHANGE_END &&
200 ctx->src_queue_cnt >= 1)
202 mfc_debug(2, "ctx is not ready\n");
283 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
289 (ctx->state == MFCINST_GOT_INST || ctx->state ==
293 s5p_mfc_clean_ctx_int_flags(ctx);
294 s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_SEQ_DONE_RET,
298 ctx->state >= MFCINST_HEAD_PARSED &&
299 ctx->state < MFCINST_ABORT) {
305 pix_mp->width = ctx->buf_width;
306 pix_mp->height = ctx->buf_height;
312 pix_mp->plane_fmt[0].bytesperline = ctx->buf_width;
313 pix_mp->plane_fmt[0].sizeimage = ctx->luma_size;
314 pix_mp->plane_fmt[1].bytesperline = ctx->buf_width;
315 pix_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
323 pix_mp->plane_fmt[0].bytesperline = ctx->dec_src_buf_size;
324 pix_mp->plane_fmt[0].sizeimage = ctx->dec_src_buf_size;
325 pix_mp->pixelformat = ctx->src_fmt->fourcc;
326 pix_mp->num_planes = ctx->src_fmt->num_planes;
361 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
371 if (ctx->vq_src.streaming || ctx->vq_dst.streaming) {
388 ctx->src_fmt = fmt;
389 ctx->codec_mode = fmt->codec_mode;
390 mfc_debug(2, "The codec number is: %d\n", ctx->codec_mode);
394 ctx->dec_src_buf_size = pix_mp->plane_fmt[0].sizeimage;
396 pix_mp->plane_fmt[0].sizeimage = ctx->dec_src_buf_size =
399 ctx->state = MFCINST_INIT;
410 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
420 if (ctx->state == MFCINST_INIT) {
421 ctx->src_bufs_cnt = 0;
425 ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
430 if (ctx->output_state != QUEUE_FREE) {
435 ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
442 ctx->output_state = QUEUE_BUFS_REQUESTED;
445 ctx->dst_bufs_cnt = 0;
449 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
453 if (ctx->capture_state != QUEUE_FREE) {
457 ctx->capture_state = QUEUE_BUFS_REQUESTED;
459 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
465 if (reqbufs->count < ctx->dpb_count) {
469 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
473 ctx->total_dpb_count = reqbufs->count;
474 ret = s5p_mfc_alloc_codec_buffers(ctx);
479 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
483 if (ctx->dst_bufs_cnt == ctx->total_dpb_count) {
484 ctx->capture_state = QUEUE_BUFS_MMAPED;
489 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
490 s5p_mfc_release_codec_buffers(ctx);
494 if (s5p_mfc_ctx_ready(ctx)) {
496 set_bit(ctx->num, &dev->ctx_work_bits);
500 s5p_mfc_wait_for_done_ctx(ctx,
510 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
518 mfc_debug(2, "State: %d, buf->type: %d\n", ctx->state, buf->type);
519 if (ctx->state == MFCINST_INIT &&
521 ret = vb2_querybuf(&ctx->vq_src, buf);
522 } else if (ctx->state == MFCINST_RUNNING &&
524 ret = vb2_querybuf(&ctx->vq_dst, buf);
538 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
540 if (ctx->state == MFCINST_ERROR) {
545 return vb2_qbuf(&ctx->vq_src, buf);
547 return vb2_qbuf(&ctx->vq_dst, buf);
554 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
556 if (ctx->state == MFCINST_ERROR) {
561 return vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
563 return vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
571 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
572 struct s5p_mfc_dev *dev = ctx->dev;
579 if (ctx->state == MFCINST_INIT) {
580 ctx->dst_bufs_cnt = 0;
581 ctx->src_bufs_cnt = 0;
582 ctx->capture_state = QUEUE_FREE;
583 ctx->output_state = QUEUE_FREE;
584 s5p_mfc_alloc_instance_buffer(ctx);
585 s5p_mfc_alloc_dec_temp_buffers(ctx);
587 set_bit(ctx->num, &dev->ctx_work_bits);
589 s5p_mfc_clean_ctx_int_flags(ctx);
592 if (s5p_mfc_wait_for_done_ctx(ctx,
596 s5p_mfc_release_instance_buffer(ctx);
597 s5p_mfc_release_dec_desc_buffer(ctx);
600 mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
602 ret = vb2_streamon(&ctx->vq_src, type);
605 ret = vb2_streamon(&ctx->vq_dst, type);
614 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
617 return vb2_streamoff(&ctx->vq_src, type);
619 return vb2_streamoff(&ctx->vq_dst, type);
626 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
630 ctx->loop_filter_mpeg4 = ctrl->val;
633 ctx->display_delay_enable = ctrl->val;
636 ctx->display_delay = ctrl->val;
639 ctx->slice_interface = ctrl->val;
650 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
651 struct s5p_mfc_dev *dev = ctx->dev;
655 if (ctx->state >= MFCINST_HEAD_PARSED &&
656 ctx->state < MFCINST_ABORT) {
657 ctrl->val = ctx->dpb_count;
659 } else if (ctx->state != MFCINST_INIT) {
664 s5p_mfc_clean_ctx_int_flags(ctx);
665 s5p_mfc_wait_for_done_ctx(ctx,
667 if (ctx->state >= MFCINST_HEAD_PARSED &&
668 ctx->state < MFCINST_ABORT) {
669 ctrl->val = ctx->dpb_count;
689 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
692 if (ctx->state != MFCINST_HEAD_PARSED &&
693 ctx->state != MFCINST_RUNNING && ctx->state != MFCINST_FINISHING
694 && ctx->state != MFCINST_FINISHED) {
698 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_H264) {
699 left = s5p_mfc_read_shm(ctx, CROP_INFO_H);
702 top = s5p_mfc_read_shm(ctx, CROP_INFO_V);
707 cr->c.width = ctx->img_width - left - right;
708 cr->c.height = ctx->img_height - top - bottom;
712 ctx->buf_width, ctx->buf_height);
716 cr->c.width = ctx->img_width;
717 cr->c.height = ctx->img_height;
719 "fh=%d\n", cr->c.width, cr->c.height, ctx->buf_width,
720 ctx->buf_height);
752 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
756 if (ctx->state == MFCINST_INIT &&
766 } else if (ctx->state == MFCINST_HEAD_PARSED &&
771 if (*buf_count < ctx->dpb_count)
772 *buf_count = ctx->dpb_count;
773 if (*buf_count > ctx->dpb_count + MFC_MAX_EXTRA_DPB)
774 *buf_count = ctx->dpb_count + MFC_MAX_EXTRA_DPB;
779 ctx->state, vq->type);
784 if (ctx->state == MFCINST_HEAD_PARSED &&
786 psize[0] = ctx->luma_size;
787 psize[1] = ctx->chroma_size;
788 allocators[0] = ctx->dev->alloc_ctx[MFC_BANK2_ALLOC_CTX];
789 allocators[1] = ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
791 ctx->state == MFCINST_INIT) {
792 psize[0] = ctx->dec_src_buf_size;
793 allocators[0] = ctx->dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
803 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
804 struct s5p_mfc_dev *dev = ctx->dev;
811 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
812 struct s5p_mfc_dev *dev = ctx->dev;
820 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
824 if (ctx->capture_state == QUEUE_BUFS_MMAPED)
826 for (i = 0; i <= ctx->src_fmt->num_planes ; i++) {
833 if (vb2_plane_size(vb, 0) < ctx->luma_size ||
834 vb2_plane_size(vb, 1) < ctx->chroma_size) {
839 ctx->dst_bufs[i].b = vb;
840 ctx->dst_bufs[i].cookie.raw.luma =
842 ctx->dst_bufs[i].cookie.raw.chroma =
844 ctx->dst_bufs_cnt++;
851 if (vb2_plane_size(vb, 0) < ctx->dec_src_buf_size) {
857 ctx->src_bufs[i].b = vb;
858 ctx->src_bufs[i].cookie.stream =
860 ctx->src_bufs_cnt++;
870 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
871 struct s5p_mfc_dev *dev = ctx->dev;
874 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
875 if (ctx->state == MFCINST_FINISHING ||
876 ctx->state == MFCINST_FINISHED)
877 ctx->state = MFCINST_RUNNING;
879 if (s5p_mfc_ctx_ready(ctx)) {
881 set_bit(ctx->num, &dev->ctx_work_bits);
891 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
892 struct s5p_mfc_dev *dev = ctx->dev;
895 if ((ctx->state == MFCINST_FINISHING ||
896 ctx->state == MFCINST_RUNNING) &&
897 dev->curr_ctx == ctx->num && dev->hw_lock) {
898 ctx->state = MFCINST_ABORT;
899 s5p_mfc_wait_for_done_ctx(ctx,
905 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
906 INIT_LIST_HEAD(&ctx->dst_queue);
907 ctx->dst_queue_cnt = 0;
908 ctx->dpb_flush_flag = 1;
909 ctx->dec_dst_flag = 0;
912 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
913 INIT_LIST_HEAD(&ctx->src_queue);
914 ctx->src_queue_cnt = 0;
917 ctx->state = MFCINST_RUNNING;
926 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
927 struct s5p_mfc_dev *dev = ctx->dev;
932 mfc_buf = &ctx->src_bufs[vb->v4l2_buf.index];
935 list_add_tail(&mfc_buf->list, &ctx->src_queue);
936 ctx->src_queue_cnt++;
939 mfc_buf = &ctx->dst_bufs[vb->v4l2_buf.index];
943 set_bit(vb->v4l2_buf.index, &ctx->dec_dst_flag);
944 list_add_tail(&mfc_buf->list, &ctx->dst_queue);
945 ctx->dst_queue_cnt++;
950 if (s5p_mfc_ctx_ready(ctx)) {
952 set_bit(ctx->num, &dev->ctx_work_bits);
986 int s5p_mfc_dec_ctrls_setup(struct s5p_mfc_ctx *ctx)
991 v4l2_ctrl_handler_init(&ctx->ctrl_handler, NUM_CTRLS);
992 if (ctx->ctrl_handler.error) {
994 return ctx->ctrl_handler.error;
1010 ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
1013 ctx->ctrls[i] = v4l2_ctrl_new_std(&ctx->ctrl_handler,
1019 if (ctx->ctrl_handler.error) {
1021 return ctx->ctrl_handler.error;
1023 if (controls[i].is_volatile && ctx->ctrls[i])
1024 ctx->ctrls[i]->flags |= V4L2_CTRL_FLAG_VOLATILE;
1029 void s5p_mfc_dec_ctrls_delete(struct s5p_mfc_ctx *ctx)
1033 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1035 ctx->ctrls[i] = NULL;