Lines Matching refs:ctx
38 int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx)
41 struct s5p_mfc_dev *dev = ctx->dev;
43 ctx->desc_buf = vb2_dma_contig_memops.alloc(
45 if (IS_ERR_VALUE((int)ctx->desc_buf)) {
46 ctx->desc_buf = 0;
50 ctx->desc_phys = s5p_mfc_mem_cookie(
51 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->desc_buf);
52 BUG_ON(ctx->desc_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
53 desc_virt = vb2_dma_contig_memops.vaddr(ctx->desc_buf);
55 vb2_dma_contig_memops.put(ctx->desc_buf);
56 ctx->desc_phys = 0;
57 ctx->desc_buf = 0;
67 void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
69 if (ctx->desc_phys) {
70 vb2_dma_contig_memops.put(ctx->desc_buf);
71 ctx->desc_phys = 0;
72 ctx->desc_buf = 0;
77 int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx)
79 struct s5p_mfc_dev *dev = ctx->dev;
84 if (ctx->type == MFCINST_DECODER) {
86 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
87 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
88 } else if (ctx->type == MFCINST_ENCODER) {
89 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
90 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
93 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) {
94 enc_ref_c_size = ALIGN(ctx->img_width,
96 * ALIGN(ctx->img_height >> 1,
101 guard_width = ALIGN(ctx->img_width + 16,
103 guard_height = ALIGN((ctx->img_height >> 1) + 4,
114 switch (ctx->codec_mode) {
116 ctx->bank1_size =
120 ctx->bank2_size = ctx->total_dpb_count * ctx->mv_size;
123 ctx->bank1_size =
130 ctx->bank2_size = 0;
134 ctx->bank1_size =
141 ctx->bank2_size = 0;
144 ctx->bank1_size = 0;
145 ctx->bank2_size = 0;
148 ctx->bank1_size =
154 ctx->bank2_size = 0;
157 ctx->bank1_size = (enc_ref_y_size * 2) +
162 ctx->bank2_size = (enc_ref_y_size * 2) +
167 ctx->bank1_size = (enc_ref_y_size * 2) +
171 ctx->bank2_size = (enc_ref_y_size * 2) +
175 ctx->bank1_size = (enc_ref_y_size * 2) +
178 ctx->bank2_size = (enc_ref_y_size * 2) +
185 if (ctx->bank1_size > 0) {
186 ctx->bank1_buf = vb2_dma_contig_memops.alloc(
187 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->bank1_size);
188 if (IS_ERR(ctx->bank1_buf)) {
189 ctx->bank1_buf = 0;
194 ctx->bank1_phys = s5p_mfc_mem_cookie(
195 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->bank1_buf);
196 BUG_ON(ctx->bank1_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
199 if (ctx->bank2_size > 0) {
200 ctx->bank2_buf = vb2_dma_contig_memops.alloc(
201 dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], ctx->bank2_size);
202 if (IS_ERR(ctx->bank2_buf)) {
203 ctx->bank2_buf = 0;
207 ctx->bank2_phys = s5p_mfc_mem_cookie(
208 dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], ctx->bank2_buf);
209 BUG_ON(ctx->bank2_phys & ((1 << MFC_BANK2_ALIGN_ORDER) - 1));
215 void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx)
217 if (ctx->bank1_buf) {
218 vb2_dma_contig_memops.put(ctx->bank1_buf);
219 ctx->bank1_buf = 0;
220 ctx->bank1_phys = 0;
221 ctx->bank1_size = 0;
223 if (ctx->bank2_buf) {
224 vb2_dma_contig_memops.put(ctx->bank2_buf);
225 ctx->bank2_buf = 0;
226 ctx->bank2_phys = 0;
227 ctx->bank2_size = 0;
232 int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx)
235 struct s5p_mfc_dev *dev = ctx->dev;
237 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
238 ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC)
239 ctx->ctx_size = MFC_H264_CTX_BUF_SIZE;
241 ctx->ctx_size = MFC_CTX_BUF_SIZE;
242 ctx->ctx_buf = vb2_dma_contig_memops.alloc(
243 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx_size);
244 if (IS_ERR(ctx->ctx_buf)) {
246 ctx->ctx_phys = 0;
247 ctx->ctx_buf = 0;
250 ctx->ctx_phys = s5p_mfc_mem_cookie(
251 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx_buf);
252 BUG_ON(ctx->ctx_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
253 ctx->ctx_ofs = OFFSETA(ctx->ctx_phys);
254 context_virt = vb2_dma_contig_memops.vaddr(ctx->ctx_buf);
257 vb2_dma_contig_memops.put(ctx->ctx_buf);
258 ctx->ctx_phys = 0;
259 ctx->ctx_buf = 0;
263 memset(context_virt, 0, ctx->ctx_size);
265 if (s5p_mfc_init_shm(ctx) < 0) {
266 vb2_dma_contig_memops.put(ctx->ctx_buf);
267 ctx->ctx_phys = 0;
268 ctx->ctx_buf = 0;
275 void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx)
277 if (ctx->ctx_buf) {
278 vb2_dma_contig_memops.put(ctx->ctx_buf);
279 ctx->ctx_phys = 0;
280 ctx->ctx_buf = 0;
282 if (ctx->shm_alloc) {
283 vb2_dma_contig_memops.put(ctx->shm_alloc);
284 ctx->shm_alloc = 0;
285 ctx->shm = 0;
290 void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
292 struct s5p_mfc_dev *dev = ctx->dev;
294 mfc_write(dev, OFFSETA(ctx->desc_phys), S5P_FIMV_SI_CH0_DESC_ADR);
299 void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx)
301 struct s5p_mfc_dev *dev = ctx->dev;
302 mfc_write(dev, ctx->shm_ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
306 int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
309 struct s5p_mfc_dev *dev = ctx->dev;
312 mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE);
314 s5p_mfc_write_shm(ctx, start_num_byte, START_BYTE_NUM);
319 int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx)
323 struct s5p_mfc_dev *dev = ctx->dev;
328 buf_addr1 = ctx->bank1_phys;
329 buf_size1 = ctx->bank1_size;
330 buf_addr2 = ctx->bank2_phys;
331 buf_size2 = ctx->bank2_size;
334 mfc_write(dev, ctx->total_dpb_count | dpb,
336 s5p_mfc_set_shared_buffer(ctx);
337 switch (ctx->codec_mode) {
406 ctx->codec_mode);
410 frame_size = ctx->luma_size;
411 frame_size_ch = ctx->chroma_size;
412 frame_size_mv = ctx->mv_size;
415 for (i = 0; i < ctx->total_dpb_count; i++) {
418 ctx->dst_bufs[i].cookie.raw.luma);
419 mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma),
422 ctx->dst_bufs[i].cookie.raw.chroma);
423 mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma),
425 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) {
436 buf_size1, buf_size2, ctx->total_dpb_count);
441 s5p_mfc_write_shm(ctx, frame_size, ALLOC_LUMA_DPB_SIZE);
442 s5p_mfc_write_shm(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
443 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC)
444 s5p_mfc_write_shm(ctx, frame_size_mv, ALLOC_MV_SIZE);
446 << S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
452 int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
455 struct s5p_mfc_dev *dev = ctx->dev;
462 void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
465 struct s5p_mfc_dev *dev = ctx->dev;
471 void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
474 struct s5p_mfc_dev *dev = ctx->dev;
483 int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *ctx)
485 struct s5p_mfc_dev *dev = ctx->dev;
492 buf_addr1 = ctx->bank1_phys;
493 buf_size1 = ctx->bank1_size;
494 buf_addr2 = ctx->bank2_phys;
495 buf_size2 = ctx->bank2_size;
496 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
497 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
499 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) {
500 enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
501 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
504 guard_width = ALIGN(ctx->img_width + 16,
506 guard_height = ALIGN((ctx->img_height >> 1) + 4,
512 switch (ctx->codec_mode) {
612 ctx->codec_mode);
618 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
620 struct s5p_mfc_dev *dev = ctx->dev;
621 struct s5p_mfc_enc_params *p = &ctx->enc_params;
626 mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX);
628 mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX);
650 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
652 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
688 shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
695 s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
697 s5p_mfc_write_shm(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG);
701 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
703 struct s5p_mfc_dev *dev = ctx->dev;
704 struct s5p_mfc_enc_params *p = &ctx->enc_params;
709 s5p_mfc_set_enc_params(ctx);
729 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX);
809 shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP);
813 s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP);
816 shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
820 s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
823 shm = s5p_mfc_read_shm(ctx, SAMPLE_ASPECT_RATIO_IDC);
826 s5p_mfc_write_shm(ctx, shm, SAMPLE_ASPECT_RATIO_IDC);
829 shm = s5p_mfc_read_shm(ctx, EXTENDED_SAR);
833 s5p_mfc_write_shm(ctx, shm, EXTENDED_SAR);
837 shm = s5p_mfc_read_shm(ctx, H264_I_PERIOD);
846 s5p_mfc_write_shm(ctx, shm, H264_I_PERIOD);
848 shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
855 s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
859 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
861 struct s5p_mfc_dev *dev = ctx->dev;
862 struct s5p_mfc_enc_params *p = &ctx->enc_params;
868 s5p_mfc_set_enc_params(ctx);
888 shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP);
892 s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP);
901 shm = s5p_mfc_read_shm(ctx, RC_VOP_TIMING);
906 s5p_mfc_write_shm(ctx, shm, RC_VOP_TIMING);
927 shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
934 s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
938 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
940 struct s5p_mfc_dev *dev = ctx->dev;
941 struct s5p_mfc_enc_params *p = &ctx->enc_params;
946 s5p_mfc_set_enc_params(ctx);
949 shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP);
952 s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP);
976 shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
983 s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
988 int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx)
990 struct s5p_mfc_dev *dev = ctx->dev;
992 s5p_mfc_set_shared_buffer(ctx);
994 if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_DEC)
995 mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL);
998 mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) <<
999 S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable <<
1000 S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay &
1005 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1009 static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1011 struct s5p_mfc_dev *dev = ctx->dev;
1024 int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx,
1027 struct s5p_mfc_dev *dev = ctx->dev;
1029 mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF);
1030 s5p_mfc_set_shared_buffer(ctx);
1031 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1037 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1041 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1045 S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
1053 int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx)
1055 struct s5p_mfc_dev *dev = ctx->dev;
1057 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC)
1058 s5p_mfc_set_enc_params_h264(ctx);
1059 else if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_ENC)
1060 s5p_mfc_set_enc_params_mpeg4(ctx);
1061 else if (ctx->codec_mode == S5P_FIMV_CODEC_H263_ENC)
1062 s5p_mfc_set_enc_params_h263(ctx);
1065 ctx->codec_mode);
1068 s5p_mfc_set_shared_buffer(ctx);
1070 (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1075 int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx)
1077 struct s5p_mfc_dev *dev = ctx->dev;
1079 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
1081 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
1083 s5p_mfc_set_shared_buffer(ctx);
1085 (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1110 static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx)
1112 struct s5p_mfc_dev *dev = ctx->dev;
1114 s5p_mfc_set_dec_stream_buffer(ctx, 0, 0, 0);
1115 dev->curr_ctx = ctx->num;
1116 s5p_mfc_clean_ctx_int_flags(ctx);
1117 s5p_mfc_decode_one_frame(ctx, MFC_DEC_RES_CHANGE);
1120 static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame)
1122 struct s5p_mfc_dev *dev = ctx->dev;
1129 if (list_empty(&ctx->src_queue)) {
1135 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1137 s5p_mfc_set_dec_stream_buffer(ctx,
1138 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), ctx->consumed_stream,
1142 dev->curr_ctx = ctx->num;
1143 s5p_mfc_clean_ctx_int_flags(ctx);
1146 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1147 ctx->state = MFCINST_FINISHING;
1149 s5p_mfc_decode_one_frame(ctx, last_frame);
1153 static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1155 struct s5p_mfc_dev *dev = ctx->dev;
1163 if (list_empty(&ctx->src_queue)) {
1168 if (list_empty(&ctx->dst_queue)) {
1173 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1177 s5p_mfc_set_enc_frame_buffer(ctx, src_y_addr, src_c_addr);
1178 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1182 s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
1184 dev->curr_ctx = ctx->num;
1185 s5p_mfc_clean_ctx_int_flags(ctx);
1186 s5p_mfc_encode_one_frame(ctx);
1190 static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1192 struct s5p_mfc_dev *dev = ctx->dev;
1199 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1200 s5p_mfc_set_dec_desc_buffer(ctx);
1202 s5p_mfc_set_dec_stream_buffer(ctx,
1206 dev->curr_ctx = ctx->num;
1207 s5p_mfc_clean_ctx_int_flags(ctx);
1208 s5p_mfc_init_decode(ctx);
1211 static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1213 struct s5p_mfc_dev *dev = ctx->dev;
1219 s5p_mfc_set_enc_ref_buffer(ctx);
1221 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1224 s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);
1226 dev->curr_ctx = ctx->num;
1227 s5p_mfc_clean_ctx_int_flags(ctx);
1228 s5p_mfc_init_encode(ctx);
1231 static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1233 struct s5p_mfc_dev *dev = ctx->dev;
1242 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1249 if (list_empty(&ctx->src_queue)) {
1255 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1257 s5p_mfc_set_dec_stream_buffer(ctx,
1261 dev->curr_ctx = ctx->num;
1262 s5p_mfc_clean_ctx_int_flags(ctx);
1263 ret = s5p_mfc_set_dec_frame_buffer(ctx);
1266 ctx->state = MFCINST_ERROR;
1274 struct s5p_mfc_ctx *ctx;
1284 /* This is perfectly ok, the scheduled ctx should wait */
1296 mfc_debug(1, "No ctx is scheduled to be run\n");
1299 ctx = dev->ctx[new_ctx];
1300 /* Got context to run in ctx */
1306 if (ctx->type == MFCINST_DECODER) {
1307 s5p_mfc_set_dec_desc_buffer(ctx);
1308 switch (ctx->state) {
1310 s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME);
1313 ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME);
1316 s5p_mfc_clean_ctx_int_flags(ctx);
1317 ret = s5p_mfc_open_inst_cmd(ctx);
1320 s5p_mfc_clean_ctx_int_flags(ctx);
1321 ret = s5p_mfc_close_inst_cmd(ctx);
1324 s5p_mfc_run_init_dec(ctx);
1327 ret = s5p_mfc_run_init_dec_buffers(ctx);
1331 s5p_mfc_run_res_change(ctx);
1334 s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME);
1338 ctx->capture_state = QUEUE_FREE;
1340 s5p_mfc_run_init_dec(ctx);
1345 } else if (ctx->type == MFCINST_ENCODER) {
1346 switch (ctx->state) {
1349 ret = s5p_mfc_run_enc_frame(ctx);
1352 s5p_mfc_clean_ctx_int_flags(ctx);
1353 ret = s5p_mfc_open_inst_cmd(ctx);
1356 s5p_mfc_clean_ctx_int_flags(ctx);
1357 ret = s5p_mfc_close_inst_cmd(ctx);
1360 s5p_mfc_run_init_enc(ctx);
1366 mfc_err("Invalid context type: %d\n", ctx->type);