Lines Matching defs:asic
92 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
94 iowrite16(value, asic->mapping +
95 (reg >> asic->bus_shift));
99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
101 return ioread16(asic->mapping +
102 (reg >> asic->bus_shift));
106 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
111 spin_lock_irqsave(&asic->lock, flags);
112 val = asic3_read_register(asic, reg);
117 asic3_write_register(asic, reg, val);
118 spin_unlock_irqrestore(&asic->lock, flags);
126 static void asic3_irq_flip_edge(struct asic3 *asic,
132 spin_lock_irqsave(&asic->lock, flags);
133 edge = asic3_read_register(asic,
136 asic3_write_register(asic,
138 spin_unlock_irqrestore(&asic->lock, flags);
143 struct asic3 *asic = irq_desc_get_handler_data(desc);
154 spin_lock_irqsave(&asic->lock, flags);
155 status = asic3_read_register(asic,
157 spin_unlock_irqrestore(&asic->lock, flags);
171 spin_lock_irqsave(&asic->lock, flags);
172 istat = asic3_read_register(asic,
176 asic3_write_register(asic,
179 spin_unlock_irqrestore(&asic->lock, flags);
188 irqnr = asic->irq_base +
192 if (asic->irq_bothedge[bank] & bit)
193 asic3_irq_flip_edge(asic, base,
203 generic_handle_irq(asic->irq_base + i);
208 dev_err(asic->dev, "interrupt processing overrun\n");
211 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
215 n = (irq - asic->irq_base) >> 4;
220 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
222 return (irq - asic->irq_base) & 0xf;
227 struct asic3 *asic = irq_data_get_irq_chip_data(data);
231 bank = asic3_irq_to_bank(asic, data->irq);
232 index = asic3_irq_to_index(asic, data->irq);
234 spin_lock_irqsave(&asic->lock, flags);
235 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
237 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
238 spin_unlock_irqrestore(&asic->lock, flags);
243 struct asic3 *asic = irq_data_get_irq_chip_data(data);
247 spin_lock_irqsave(&asic->lock, flags);
248 regval = asic3_read_register(asic,
253 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
255 asic3_write_register(asic,
259 spin_unlock_irqrestore(&asic->lock, flags);
264 struct asic3 *asic = irq_data_get_irq_chip_data(data);
268 bank = asic3_irq_to_bank(asic, data->irq);
269 index = asic3_irq_to_index(asic, data->irq);
271 spin_lock_irqsave(&asic->lock, flags);
272 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
274 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
275 spin_unlock_irqrestore(&asic->lock, flags);
280 struct asic3 *asic = irq_data_get_irq_chip_data(data);
284 spin_lock_irqsave(&asic->lock, flags);
285 regval = asic3_read_register(asic,
290 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
292 asic3_write_register(asic,
296 spin_unlock_irqrestore(&asic->lock, flags);
301 struct asic3 *asic = irq_data_get_irq_chip_data(data);
306 bank = asic3_irq_to_bank(asic, data->irq);
307 index = asic3_irq_to_index(asic, data->irq);
310 spin_lock_irqsave(&asic->lock, flags);
311 level = asic3_read_register(asic,
313 edge = asic3_read_register(asic,
315 trigger = asic3_read_register(asic,
317 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
327 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
331 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
344 dev_notice(asic->dev, "irq type not changed\n");
346 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
348 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
350 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
352 spin_unlock_irqrestore(&asic->lock, flags);
373 struct asic3 *asic = platform_get_drvdata(pdev);
381 asic->irq_nr = ret;
385 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
388 irq_base = asic->irq_base;
391 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
396 irq_set_chip_data(irq, asic);
401 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
404 irq_set_chained_handler(asic->irq_nr, asic3_irq_demux);
405 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
406 irq_set_handler_data(asic->irq_nr, asic);
413 struct asic3 *asic = platform_get_drvdata(pdev);
416 irq_base = asic->irq_base;
423 irq_set_chained_handler(asic->irq_nr, NULL);
433 struct asic3 *asic;
435 asic = container_of(chip, struct asic3, gpio);
439 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
444 spin_lock_irqsave(&asic->lock, flags);
446 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
454 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
456 spin_unlock_irqrestore(&asic->lock, flags);
479 struct asic3 *asic;
481 asic = container_of(chip, struct asic3, gpio);
485 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
490 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
499 struct asic3 *asic;
501 asic = container_of(chip, struct asic3, gpio);
505 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
512 spin_lock_irqsave(&asic->lock, flags);
514 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
521 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
523 spin_unlock_irqrestore(&asic->lock, flags);
530 struct asic3 *asic = container_of(chip, struct asic3, gpio);
532 return (offset < ASIC3_NUM_GPIOS) ? asic->irq_base + offset : -ENXIO;
538 struct asic3 *asic = platform_get_drvdata(pdev);
549 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
550 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
551 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
552 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
572 asic3_write_register(asic,
576 asic3_write_register(asic,
579 asic3_write_register(asic,
585 return gpiochip_add(&asic->gpio);
590 struct asic3 *asic = platform_get_drvdata(pdev);
592 return gpiochip_remove(&asic->gpio);
595 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
600 spin_lock_irqsave(&asic->lock, flags);
602 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
604 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
606 spin_unlock_irqrestore(&asic->lock, flags);
609 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
616 spin_lock_irqsave(&asic->lock, flags);
618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
620 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
622 spin_unlock_irqrestore(&asic->lock, flags);
646 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
649 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
650 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
651 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
655 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
658 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
661 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
670 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
672 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
675 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
676 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
677 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
694 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
696 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
701 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
703 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
727 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
730 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
732 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
734 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
736 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
739 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
743 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
747 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
750 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
751 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
754 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
758 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
762 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
770 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
773 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
777 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
778 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
779 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
780 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
805 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
807 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
815 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
817 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
825 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
827 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
830 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
866 struct asic3 *asic = platform_get_drvdata(pdev);
872 dev_dbg(asic->dev, "no SDIO MEM resource\n");
876 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
879 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
882 ds1wm_resources[0].start >>= asic->bus_shift;
883 ds1wm_resources[0].end >>= asic->bus_shift;
886 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
888 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
889 if (!asic->tmio_cnf) {
891 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
894 asic3_mmc_resources[0].start >>= asic->bus_shift;
895 asic3_mmc_resources[0].end >>= asic->bus_shift;
898 &asic3_cell_ds1wm, 1, mem, asic->irq_base);
926 struct asic3 *asic = platform_get_drvdata(pdev);
929 iounmap(asic->tmio_cnf);
936 struct asic3 *asic;
941 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
942 if (asic == NULL) {
947 spin_lock_init(&asic->lock);
948 platform_set_drvdata(pdev, asic);
949 asic->dev = &pdev->dev;
954 dev_err(asic->dev, "no MEM resource\n");
958 asic->mapping = ioremap(mem->start, resource_size(mem));
959 if (!asic->mapping) {
961 dev_err(asic->dev, "Couldn't ioremap\n");
965 asic->irq_base = pdata->irq_base;
968 asic->bus_shift = 2 - (resource_size(mem) >> 12);
971 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
975 dev_err(asic->dev, "Couldn't probe IRQs\n");
979 asic->gpio.label = "asic3";
980 asic->gpio.base = pdata->gpio_base;
981 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
982 asic->gpio.get = asic3_gpio_get;
983 asic->gpio.set = asic3_gpio_set;
984 asic->gpio.direction_input = asic3_gpio_direction_input;
985 asic->gpio.direction_output = asic3_gpio_direction_output;
986 asic->gpio.to_irq = asic3_gpio_to_irq;
992 dev_err(asic->dev, "GPIO probe failed\n");
999 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1003 dev_info(asic->dev, "ASIC3 Core driver\n");
1011 iounmap(asic->mapping);
1014 kfree(asic);
1022 struct asic3 *asic = platform_get_drvdata(pdev);
1031 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1033 iounmap(asic->mapping);
1035 kfree(asic);