Cross Reference: /drivers/net/can/cc770/cc770.c

Lines Matching defs:priv
115 	struct cc770_priv *priv = netdev_priv(dev);
120 	for (o = 0; o < ARRAY_SIZE(priv->obj_flags); o++) {
121 		obj_flags = priv->obj_flags[o];
129 			if (priv->control_normal_mode & CTRL_EAF) {
150 			cc770_write_reg(priv, msgobj[mo].config, msgcfg);
151 			cc770_write_reg(priv, msgobj[mo].ctrl0,
156 				cc770_write_reg(priv, msgobj[mo].ctrl1,
160 				cc770_write_reg(priv, msgobj[mo].ctrl1,
167 			cc770_write_reg(priv, msgobj[mo].ctrl1,
170 			cc770_write_reg(priv, msgobj[mo].ctrl0,
177 static void disable_all_objs(const struct cc770_priv *priv)
181 	for (o = 0; o <  ARRAY_SIZE(priv->obj_flags); o++) {
184 		if (priv->obj_flags[o] & CC770_OBJ_FLAG_RX) {
185 			if (o > 0 && priv->control_normal_mode & CTRL_EAF)
188 			cc770_write_reg(priv, msgobj[mo].ctrl1,
191 			cc770_write_reg(priv, msgobj[mo].ctrl0,
196 			cc770_write_reg(priv, msgobj[mo].ctrl1,
199 			cc770_write_reg(priv, msgobj[mo].ctrl0,
208 	struct cc770_priv *priv = netdev_priv(dev);
211 	cc770_write_reg(priv, control, CTRL_CCE | CTRL_INI);
213 	priv->can.state = CAN_STATE_STOPPED;
216 	cc770_read_reg(priv, interrupt);
219 	cc770_write_reg(priv, status, 0);
222 	disable_all_objs(priv);
227 	struct cc770_priv *priv = netdev_priv(dev);
230 	cc770_read_reg(priv, interrupt);
233 	cc770_write_reg(priv, status, STAT_LEC_MASK);
242 	cc770_write_reg(priv, control, priv->control_normal_mode);
244 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
247 static void chipset_init(struct cc770_priv *priv)
252 	cc770_write_reg(priv, control, (CTRL_CCE | CTRL_INI));
255 	cc770_write_reg(priv, clkout, priv->clkout);
258 	cc770_write_reg(priv, cpu_interface, priv->cpu_interface);
261 	cc770_write_reg(priv, bus_config, priv->bus_config);
264 	cc770_read_reg(priv, interrupt);
267 	cc770_write_reg(priv, status, 0);
271 		cc770_write_reg(priv, msgobj[mo].ctrl0,
274 		cc770_write_reg(priv, msgobj[mo].ctrl0,
277 		cc770_write_reg(priv, msgobj[mo].ctrl1,
281 			cc770_write_reg(priv, msgobj[mo].data[data], 0);
283 			cc770_write_reg(priv, msgobj[mo].id[id], 0);
284 		cc770_write_reg(priv, msgobj[mo].config, 0);
288 	cc770_write_reg(priv, global_mask_std[0], 0);
289 	cc770_write_reg(priv, global_mask_std[1], 0);
290 	cc770_write_reg(priv, global_mask_ext[0], 0);
291 	cc770_write_reg(priv, global_mask_ext[1], 0);
292 	cc770_write_reg(priv, global_mask_ext[2], 0);
293 	cc770_write_reg(priv, global_mask_ext[3], 0);
299 	struct cc770_priv *priv = netdev_priv(dev);
302 	cc770_write_reg(priv, control, CTRL_CCE | CTRL_EAF | CTRL_INI);
304 	cc770_write_reg(priv, cpu_interface, priv->cpu_interface);
310 	if (cc770_read_reg(priv, cpu_interface) & CPUIF_RST) {
312 			    priv->reg_base);
317 	cc770_write_reg(priv, msgobj[1].data[1], 0x25);
318 	cc770_write_reg(priv, msgobj[2].data[3], 0x52);
319 	cc770_write_reg(priv, msgobj[10].data[6], 0xc3);
320 	if ((cc770_read_reg(priv, msgobj[1].data[1]) != 0x25) ||
321 	    (cc770_read_reg(priv, msgobj[2].data[3]) != 0x52) ||
322 	    (cc770_read_reg(priv, msgobj[10].data[6]) != 0xc3)) {
324 			    priv->reg_base);
329 	if (cc770_read_reg(priv, control) & CTRL_EAF)
330 		priv->control_normal_mode |= CTRL_EAF;
337 	struct cc770_priv *priv = netdev_priv(dev);
340 	if (priv->can.state != CAN_STATE_STOPPED)
364 	struct cc770_priv *priv = netdev_priv(dev);
365 	struct can_bittiming *bt = &priv->can.bittiming;
371 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
376 	cc770_write_reg(priv, bit_timing_0, btr0);
377 	cc770_write_reg(priv, bit_timing_1, btr1);
385 	struct cc770_priv *priv = netdev_priv(dev);
387 	bec->txerr = cc770_read_reg(priv, tx_error_counter);
388 	bec->rxerr = cc770_read_reg(priv, rx_error_counter);
395 	struct cc770_priv *priv = netdev_priv(dev);
406 	if ((cc770_read_reg(priv,
420 	cc770_write_reg(priv, msgobj[mo].ctrl1,
422 	cc770_write_reg(priv, msgobj[mo].ctrl0,
426 		cc770_write_reg(priv, msgobj[mo].config,
428 		cc770_write_reg(priv, msgobj[mo].id[3], id << 3);
429 		cc770_write_reg(priv, msgobj[mo].id[2], id >> 5);
430 		cc770_write_reg(priv, msgobj[mo].id[1], id >> 13);
431 		cc770_write_reg(priv, msgobj[mo].id[0], id >> 21);
434 		cc770_write_reg(priv, msgobj[mo].config, (dlc << 4) | rtr);
435 		cc770_write_reg(priv, msgobj[mo].id[0], id >> 3);
436 		cc770_write_reg(priv, msgobj[mo].id[1], id << 5);
440 		cc770_write_reg(priv, msgobj[mo].data[i], cf->data[i]);
445 	cc770_write_reg(priv, msgobj[mo].ctrl1,
456 	cc770_write_reg(priv, msgobj[mo].ctrl0,
464 	struct cc770_priv *priv = netdev_priv(dev);
476 	config = cc770_read_reg(priv, msgobj[mo].config);
490 			id = cc770_read_reg(priv, msgobj[mo].id[3]);
491 			id |= cc770_read_reg(priv, msgobj[mo].id[2]) << 8;
492 			id |= cc770_read_reg(priv, msgobj[mo].id[1]) << 16;
493 			id |= cc770_read_reg(priv, msgobj[mo].id[0]) << 24;
497 			id = cc770_read_reg(priv, msgobj[mo].id[1]);
498 			id |= cc770_read_reg(priv, msgobj[mo].id[0]) << 8;
505 			cf->data[i] = cc770_read_reg(priv, msgobj[mo].data[i]);
515 	struct cc770_priv *priv = netdev_priv(dev);
528 	if (priv->control_normal_mode & CTRL_EAF) {
529 		cf->data[6] = cc770_read_reg(priv, tx_error_counter);
530 		cf->data[7] = cc770_read_reg(priv, rx_error_counter);
535 		cc770_write_reg(priv, control, CTRL_INI);
537 		priv->can.state = CAN_STATE_BUS_OFF;
545 			priv->can.state = CAN_STATE_ERROR_PASSIVE;
546 			priv->can.can_stats.error_passive++;
550 			priv->can.state = CAN_STATE_ERROR_WARNING;
551 			priv->can.can_stats.error_warning++;
557 		priv->can.state = CAN_STATE_ERROR_ACTIVE;
596 	struct cc770_priv *priv = netdev_priv(dev);
599 	status = cc770_read_reg(priv, status);
601 	cc770_write_reg(priv, status, STAT_LEC_MASK);
614 	struct cc770_priv *priv = netdev_priv(dev);
621 		ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1);
625 			if (priv->control_normal_mode & CTRL_EAF) {
626 				if (!(cc770_read_reg(priv, msgobj[mo].ctrl0) &
639 			cc770_write_reg(priv, msgobj[mo].ctrl1,
644 		cc770_write_reg(priv, msgobj[mo].ctrl0,
647 		cc770_write_reg(priv, msgobj[mo].ctrl1,
655 	struct cc770_priv *priv = netdev_priv(dev);
661 		ctrl0 = cc770_read_reg(priv, msgobj[mo].ctrl0);
665 		ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1);
668 		cc770_write_reg(priv, msgobj[mo].ctrl0,
671 		cc770_write_reg(priv, msgobj[mo].ctrl1,
679 	struct cc770_priv *priv = netdev_priv(dev);
684 	cc770_write_reg(priv, msgobj[mo].ctrl0,
690 	cc770_write_reg(priv, msgobj[mo].ctrl0,
701 	struct cc770_priv *priv = netdev_priv(dev);
706 	if (priv->can.state == CAN_STATE_STOPPED)
709 	if (priv->pre_irq)
710 		priv->pre_irq(priv);
714 		intid = cc770_read_reg(priv, interrupt);
732 			if (priv->obj_flags[o] & CC770_OBJ_FLAG_RTR)
734 			else if (priv->obj_flags[o] & CC770_OBJ_FLAG_RX)
741 	if (priv->post_irq)
742 		priv->post_irq(priv);
752 	struct cc770_priv *priv = netdev_priv(dev);
763 	err = request_irq(dev->irq, &cc770_interrupt, priv->irq_flags,
792 	struct cc770_priv *priv;
799 	priv = netdev_priv(dev);
801 	priv->dev = dev;
802 	priv->can.bittiming_const = &cc770_bittiming_const;
803 	priv->can.do_set_bittiming = cc770_set_bittiming;
804 	priv->can.do_set_mode = cc770_set_mode;
805 	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
807 	memcpy(priv->obj_flags, cc770_obj_flags, sizeof(cc770_obj_flags));
810 		priv->priv = (void *)priv + sizeof(struct cc770_priv);
830 	struct cc770_priv *priv = netdev_priv(dev);
842 	if (!i82527_compat && priv->control_normal_mode & CTRL_EAF) {
843 		priv->can.do_get_berr_counter = cc770_get_berr_counter;
844 		priv->control_normal_mode = CTRL_IE | CTRL_EAF | CTRL_EIE;
847 		priv->control_normal_mode = CTRL_IE | CTRL_EIE;
851 	chipset_init(priv);