Lines Matching defs:priv

120 static u8 cc770_isa_mem_read_reg(const struct cc770_priv *priv, int reg)
122 return readb(priv->reg_base + reg);
125 static void cc770_isa_mem_write_reg(const struct cc770_priv *priv,
128 writeb(val, priv->reg_base + reg);
131 static u8 cc770_isa_port_read_reg(const struct cc770_priv *priv, int reg)
133 return inb((unsigned long)priv->reg_base + reg);
136 static void cc770_isa_port_write_reg(const struct cc770_priv *priv,
139 outb(val, (unsigned long)priv->reg_base + reg);
142 static u8 cc770_isa_port_read_reg_indirect(const struct cc770_priv *priv,
145 unsigned long base = (unsigned long)priv->reg_base;
157 static void cc770_isa_port_write_reg_indirect(const struct cc770_priv *priv,
160 unsigned long base = (unsigned long)priv->reg_base;
172 struct cc770_priv *priv;
206 priv = netdev_priv(dev);
209 priv->irq_flags = IRQF_SHARED;
211 priv->reg_base = base;
213 priv->read_reg = cc770_isa_mem_read_reg;
214 priv->write_reg = cc770_isa_mem_write_reg;
216 priv->reg_base = (void __iomem *)port[idx];
220 priv->read_reg = cc770_isa_port_read_reg_indirect;
221 priv->write_reg = cc770_isa_port_write_reg_indirect;
223 priv->read_reg = cc770_isa_port_read_reg;
224 priv->write_reg = cc770_isa_port_write_reg;
234 priv->can.clock.freq = clktmp;
237 priv->cpu_interface = cir[idx];
239 priv->cpu_interface = cir[0];
243 priv->cpu_interface |= CPUIF_DSC;
248 priv->cpu_interface |= CPUIF_DMC;
251 if (priv->cpu_interface & CPUIF_DSC)
252 priv->can.clock.freq /= 2;
255 priv->bus_config = bcr[idx];
257 priv->bus_config = bcr[0];
259 priv->bus_config = BCR_DEFAULT;
262 priv->clkout = cor[idx];
264 priv->clkout = cor[0];
266 priv->clkout = COR_DEFAULT;
279 priv->reg_base, dev->irq);
297 struct cc770_priv *priv = netdev_priv(dev);
304 iounmap(priv->reg_base);
307 if (priv->read_reg == cc770_isa_port_read_reg_indirect)