Lines Matching defs:priv
84 static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
92 spin_lock_irqsave(&priv->cmdreg_lock, flags);
93 priv->write_reg(priv, REG_CMR, val);
94 priv->read_reg(priv, REG_SR);
95 spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
98 static int sja1000_is_absent(struct sja1000_priv *priv)
100 return (priv->read_reg(priv, REG_MOD) == 0xFF);
105 struct sja1000_priv *priv = netdev_priv(dev);
107 if (priv->reg_base && sja1000_is_absent(priv)) {
117 struct sja1000_priv *priv = netdev_priv(dev);
118 unsigned char status = priv->read_reg(priv, REG_MOD);
122 priv->write_reg(priv, REG_IER, IRQ_OFF);
127 priv->can.state = CAN_STATE_STOPPED;
131 priv->write_reg(priv, REG_MOD, MOD_RM); /* reset chip */
133 status = priv->read_reg(priv, REG_MOD);
141 struct sja1000_priv *priv = netdev_priv(dev);
142 unsigned char status = priv->read_reg(priv, REG_MOD);
148 priv->can.state = CAN_STATE_ERROR_ACTIVE;
150 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
151 priv->write_reg(priv, REG_IER, IRQ_ALL);
153 priv->write_reg(priv, REG_IER,
159 priv->write_reg(priv, REG_MOD, 0x00);
161 status = priv->read_reg(priv, REG_MOD);
169 struct sja1000_priv *priv = netdev_priv(dev);
172 if (priv->can.state != CAN_STATE_STOPPED)
176 priv->write_reg(priv, REG_TXERR, 0x0);
177 priv->write_reg(priv, REG_RXERR, 0x0);
178 priv->read_reg(priv, REG_ECC);
186 struct sja1000_priv *priv = netdev_priv(dev);
188 if (!priv->open_time)
207 struct sja1000_priv *priv = netdev_priv(dev);
208 struct can_bittiming *bt = &priv->can.bittiming;
214 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
219 priv->write_reg(priv, REG_BTR0, btr0);
220 priv->write_reg(priv, REG_BTR1, btr1);
228 struct sja1000_priv *priv = netdev_priv(dev);
230 bec->txerr = priv->read_reg(priv, REG_TXERR);
231 bec->rxerr = priv->read_reg(priv, REG_RXERR);
246 struct sja1000_priv *priv = netdev_priv(dev);
249 priv->write_reg(priv, REG_CDR, priv->cdr | CDR_PELICAN);
252 priv->write_reg(priv, REG_ACCC0, 0x00);
253 priv->write_reg(priv, REG_ACCC1, 0x00);
254 priv->write_reg(priv, REG_ACCC2, 0x00);
255 priv->write_reg(priv, REG_ACCC3, 0x00);
257 priv->write_reg(priv, REG_ACCM0, 0xFF);
258 priv->write_reg(priv, REG_ACCM1, 0xFF);
259 priv->write_reg(priv, REG_ACCM2, 0xFF);
260 priv->write_reg(priv, REG_ACCM3, 0xFF);
262 priv->write_reg(priv, REG_OCR, priv->ocr | OCR_MODE_NORMAL);
274 struct sja1000_priv *priv = netdev_priv(dev);
296 priv->write_reg(priv, REG_FI, fi);
297 priv->write_reg(priv, REG_ID1, (id & 0x1fe00000) >> (5 + 16));
298 priv->write_reg(priv, REG_ID2, (id & 0x001fe000) >> (5 + 8));
299 priv->write_reg(priv, REG_ID3, (id & 0x00001fe0) >> 5);
300 priv->write_reg(priv, REG_ID4, (id & 0x0000001f) << 3);
303 priv->write_reg(priv, REG_FI, fi);
304 priv->write_reg(priv, REG_ID1, (id & 0x000007f8) >> 3);
305 priv->write_reg(priv, REG_ID2, (id & 0x00000007) << 5);
309 priv->write_reg(priv, dreg++, cf->data[i]);
313 sja1000_write_cmdreg(priv, CMD_TR);
320 struct sja1000_priv *priv = netdev_priv(dev);
334 fi = priv->read_reg(priv, REG_FI);
339 id = (priv->read_reg(priv, REG_ID1) << (5 + 16))
340 | (priv->read_reg(priv, REG_ID2) << (5 + 8))
341 | (priv->read_reg(priv, REG_ID3) << 5)
342 | (priv->read_reg(priv, REG_ID4) >> 3);
347 id = (priv->read_reg(priv, REG_ID1) << 3)
348 | (priv->read_reg(priv, REG_ID2) >> 5);
356 cf->data[i] = priv->read_reg(priv, dreg++);
362 sja1000_write_cmdreg(priv, CMD_RRB);
372 struct sja1000_priv *priv = netdev_priv(dev);
376 enum can_state state = priv->can.state;
390 sja1000_write_cmdreg(priv, CMD_CDO); /* clear bit */
408 priv->can.can_stats.bus_error++;
411 ecc = priv->read_reg(priv, REG_ECC);
445 alc = priv->read_reg(priv, REG_ALC);
446 priv->can.can_stats.arbitration_lost++;
452 if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
454 uint8_t rxerr = priv->read_reg(priv, REG_RXERR);
455 uint8_t txerr = priv->read_reg(priv, REG_TXERR);
458 priv->can.can_stats.error_warning++;
463 priv->can.can_stats.error_passive++;
472 priv->can.state = state;
485 struct sja1000_priv *priv = netdev_priv(dev);
491 if (priv->read_reg(priv, REG_IER) == IRQ_OFF)
494 if (priv->pre_irq)
495 priv->pre_irq(priv);
497 while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
499 status = priv->read_reg(priv, REG_SR);
501 if (status == 0xFF && sja1000_is_absent(priv))
509 stats->tx_bytes += priv->read_reg(priv, REG_FI) & 0xf;
518 status = priv->read_reg(priv, REG_SR);
520 if (status == 0xFF && sja1000_is_absent(priv))
531 if (priv->post_irq)
532 priv->post_irq(priv);
543 struct sja1000_priv *priv = netdev_priv(dev);
555 if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER)) {
556 err = request_irq(dev->irq, sja1000_interrupt, priv->irq_flags,
566 priv->open_time = jiffies;
575 struct sja1000_priv *priv = netdev_priv(dev);
580 if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER))
585 priv->open_time = 0;
593 struct sja1000_priv *priv;
600 priv = netdev_priv(dev);
602 priv->dev = dev;
603 priv->can.bittiming_const = &sja1000_bittiming_const;
604 priv->can.do_set_bittiming = sja1000_set_bittiming;
605 priv->can.do_set_mode = sja1000_set_mode;
606 priv->can.do_get_berr_counter = sja1000_get_berr_counter;
607 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
610 spin_lock_init(&priv->cmdreg_lock);
613 priv->priv = (void *)priv + sizeof(struct sja1000_priv);